From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH v3 13/30] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP
Date: Fri, 23 Jul 2021 10:42:22 -0700 [thread overview]
Message-ID: <20210723174239.1551352-14-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210723174239.1551352-1-matthew.d.roper@intel.com>
From: Lucas De Marchi <lucas.demarchi@intel.com>
Instead of maintaining the same if ladder in 3 different places, add a
function to read RP_STATE_CAP.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +++-----
drivers/gpu/drm/i915/gt/intel_rps.c | 17 ++++++++++++-----
drivers/gpu/drm/i915/gt/intel_rps.h | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++-----
4 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 4270b5a34a83..1061a62bdfce 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -309,13 +309,11 @@ static int frequency_show(struct seq_file *m, void *unused)
int max_freq;
rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
- if (IS_GEN9_LP(i915)) {
- rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
+ rp_state_cap = intel_rps_read_state_cap(rps);
+ if (IS_GEN9_LP(i915))
gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
- } else {
- rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
+ else
gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
- }
/* RPSTAT1 is in the GT power well */
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 06e9a8ed4e03..490bc1513480 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -975,20 +975,16 @@ int intel_rps_set(struct intel_rps *rps, u8 val)
static void gen6_rps_init(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- struct intel_uncore *uncore = rps_to_uncore(rps);
+ u32 rp_state_cap = intel_rps_read_state_cap(rps);
/* All of these values are in units of 50MHz */
/* static values from HW: RP0 > RP1 > RPn (min_freq) */
if (IS_GEN9_LP(i915)) {
- u32 rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
-
rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
rps->min_freq = (rp_state_cap >> 0) & 0xff;
} else {
- u32 rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
-
rps->rp0_freq = (rp_state_cap >> 0) & 0xff;
rps->rp1_freq = (rp_state_cap >> 8) & 0xff;
rps->min_freq = (rp_state_cap >> 16) & 0xff;
@@ -1936,6 +1932,17 @@ u32 intel_rps_read_actual_frequency(struct intel_rps *rps)
return freq;
}
+u32 intel_rps_read_state_cap(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ struct intel_uncore *uncore = rps_to_uncore(rps);
+
+ if (IS_GEN9_LP(i915))
+ return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
+ else
+ return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
+}
+
/* External interface for intel_ips.ko */
static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 1d2cfc98b510..6e06dd61f818 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -31,6 +31,7 @@ int intel_gpu_freq(struct intel_rps *rps, int val);
int intel_freq_opcode(struct intel_rps *rps, int val);
u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1);
u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
+u32 intel_rps_read_state_cap(struct intel_rps *rps);
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0529576f069c..37056b2c044a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -420,13 +420,11 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
int max_freq;
rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS);
- if (IS_GEN9_LP(dev_priv)) {
- rp_state_cap = intel_uncore_read(&dev_priv->uncore, BXT_RP_STATE_CAP);
+ rp_state_cap = intel_rps_read_state_cap(rps);
+ if (IS_GEN9_LP(dev_priv))
gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS);
- } else {
- rp_state_cap = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_CAP);
+ else
gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS);
- }
/* RPSTAT1 is in the GT power well */
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
--
2.25.4
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next prev parent reply other threads:[~2021-07-23 17:43 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-23 17:42 [Intel-gfx] [PATCH v3 00/30] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 01/30] drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP() Matt Roper
2021-07-27 18:34 ` Yokoyama, Caz
2021-07-27 18:38 ` Matt Roper
2021-07-27 19:00 ` Yokoyama, Caz
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 02/30] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper
2021-07-23 17:54 ` Lucas De Marchi
2021-07-23 17:55 ` Matt Roper
2021-07-23 19:10 ` [Intel-gfx] [PATCH v4 2/2] " Matt Roper
2021-07-24 0:47 ` Lucas De Marchi
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 03/30] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 04/30] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 05/30] drm/i915/xehp: Xe_HP forcewake support Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 06/30] drm/i915/xehp: handle new steering options Matt Roper
2021-07-27 19:11 ` Yokoyama, Caz
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 07/30] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 08/30] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 09/30] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 10/30] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 11/30] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 12/30] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper
2021-07-23 17:42 ` Matt Roper [this message]
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 14/30] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 15/30] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 16/30] drm/i915/dg2: Add forcewake table Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 17/30] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 18/30] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 19/30] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 20/30] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 21/30] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-29 15:08 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 22/30] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-29 15:14 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 23/30] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper
2021-07-29 15:06 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 24/30] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 25/30] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 26/30] drm/i915/dg2: Update modeset sequences Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 27/30] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper
2021-07-24 4:19 ` kernel test robot
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 28/30] drm/i915/dg2: Update lane disable power state during PSR Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 29/30] drm/i915/dg2: Update to bigjoiner path Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 30/30] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-07-23 21:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev6) Patchwork
2021-07-23 21:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-23 21:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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