From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3 16/30] drm/i915/dg2: Add forcewake table
Date: Fri, 23 Jul 2021 10:42:25 -0700 [thread overview]
Message-ID: <20210723174239.1551352-17-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210723174239.1551352-1-matthew.d.roper@intel.com>
The DG2 forcewake table is very similar to the one used by XeHP SDV (and
both platforms are even presented as a single table in the bspec). For
the most part DG2 starts using a few additional ranges that were
'reserved' on XeHP SDV and stops using some others. However there is a
single range (0xd800-0xd87f) that needs to be handled differently
between the two platforms (it needs GT wake on XeHP SDV, but render wake
on DG2) so unless we want to wake both domains (which could waste power)
or define new types of forcewake domains for this special case we need
to have separate tables for the two platforms. Let's define the ranges
for both platforms with a parameterized macro so that we don't actually
need to duplicate everything in the code.
It should be fine for DG2 to re-use the Xe_HP shadow register list so we
can continue to use the 'xehpsdv' MMIO write functions and don't need to
spin up a separate DG2 instance.
Bspec: 66534
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 305 +++++++++++++++-------------
1 file changed, 168 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 8cf53f54559d..6b38bc2811c1 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1317,143 +1317,170 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
0x1d3f00 - 0x1d3fff: VD2 */
};
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
-static const struct intel_forcewake_range __xehp_fw_ranges[] = {
- GEN_FW_RANGE(0x0, 0x1fff, 0), /*
- 0x0 - 0xaff: reserved
- 0xb00 - 0x1fff: always on */
- GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x4b00, 0x51ff, 0), /*
- 0x4b00 - 0x4fff: reserved
- 0x5000 - 0x51ff: always on */
- GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
- GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
- 0x8160 - 0x817f: reserved
- 0x8180 - 0x81ff: always on */
- GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /*
- 0x8500 - 0x87ff: gt
- 0x8800 - 0x8fff: reserved
- 0x9000 - 0x947f: gt
- 0x9480 - 0x94cf: reserved */
- GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x9560, 0x97ff, 0), /*
- 0x9560 - 0x95ff: always on
- 0x9600 - 0x97ff: reserved */
- GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
- 0x9800 - 0xb4ff: gt
- 0xb500 - 0xbfff: reserved
- 0xc000 - 0xcfff: gt */
- GEN_FW_RANGE(0xd000, 0xd7ff, 0),
- GEN_FW_RANGE(0xd800, 0xdbff, FORCEWAKE_GT),
- GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
- 0xdd00 - 0xddff: gt
- 0xde00 - 0xde7f: reserved */
- GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
- 0xde80 - 0xdfff: render
- 0xe000 - 0xe0ff: reserved
- 0xe100 - 0xe8ff: render */
- GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /*
- 0xe900 - 0xe9ff: gt
- 0xea00 - 0xefff: reserved
- 0xf000 - 0xffff: gt */
- GEN_FW_RANGE(0x10000, 0x13fff, 0), /*
- 0x10000 - 0x11fff: reserved
- 0x12000 - 0x127ff: always on
- 0x12800 - 0x13fff: reserved */
- GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0),
- GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2),
- GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4),
- GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6),
- GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /*
- 0x14800 - 0x14fff: render
- 0x15000 - 0x16dff: reserved
- 0x16e00 - 0x1ffff: render */
- GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*
- 0x20000 - 0x20fff: VD0
- 0x21000 - 0x21fff: reserved */
- GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
- 0x24000 - 0x2407f: always on
- 0x24080 - 0x2417f: reserved */
- GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
- 0x24180 - 0x241ff: gt
- 0x24200 - 0x249ff: reserved */
- GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
- 0x24a00 - 0x24a7f: render
- 0x24a80 - 0x251ff: reserved */
- GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /*
- 0x25200 - 0x252ff: gt
- 0x25300 - 0x25fff: reserved */
- GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /*
- 0x26000 - 0x27fff: render
- 0x28000 - 0x29fff: reserved
- 0x2a000 - 0x2ffff: undocumented */
- GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
- GEN_FW_RANGE(0x40000, 0x1bffff, 0),
- GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
- 0x1c0000 - 0x1c2bff: VD0
- 0x1c2c00 - 0x1c2cff: reserved
- 0x1c2d00 - 0x1c2dff: VD0
- 0x1c2e00 - 0x1c3eff: reserved
- 0x1c3f00 - 0x1c3fff: VD0 */
- GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /*
- 0x1c4000 - 0x1c6bff: VD1
- 0x1c6c00 - 0x1c6cff: reserved
- 0x1c6d00 - 0x1c6dff: VD1
- 0x1c6e00 - 0x1c7fff: reserved */
- GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
- 0x1c8000 - 0x1ca0ff: VE0
- 0x1ca100 - 0x1cbfff: reserved */
- GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0),
- GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2),
- GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4),
- GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6),
- GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
- 0x1d0000 - 0x1d2bff: VD2
- 0x1d2c00 - 0x1d2cff: reserved
- 0x1d2d00 - 0x1d2dff: VD2
- 0x1d2e00 - 0x1d3eff: reserved
- 0x1d3f00 - 0x1d3fff: VD2 */
- GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /*
- 0x1d4000 - 0x1d6bff: VD3
- 0x1d6c00 - 0x1d6cff: reserved
- 0x1d6d00 - 0x1d6dff: VD3
- 0x1d6e00 - 0x1d7fff: reserved */
- GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /*
- 0x1d8000 - 0x1da0ff: VE1
- 0x1da100 - 0x1dffff: reserved */
- GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /*
- 0x1e0000 - 0x1e2bff: VD4
- 0x1e2c00 - 0x1e2cff: reserved
- 0x1e2d00 - 0x1e2dff: VD4
- 0x1e2e00 - 0x1e3eff: reserved
- 0x1e3f00 - 0x1e3fff: VD4 */
- GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /*
- 0x1e4000 - 0x1e6bff: VD5
- 0x1e6c00 - 0x1e6cff: reserved
- 0x1e6d00 - 0x1e6dff: VD5
- 0x1e6e00 - 0x1e7fff: reserved */
- GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /*
- 0x1e8000 - 0x1ea0ff: VE2
- 0x1ea100 - 0x1effff: reserved */
- GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /*
- 0x1f0000 - 0x1f2bff: VD6
- 0x1f2c00 - 0x1f2cff: reserved
- 0x1f2d00 - 0x1f2dff: VD6
- 0x1f2e00 - 0x1f3eff: reserved
- 0x1f3f00 - 0x1f3fff: VD6 */
- GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /*
- 0x1f4000 - 0x1f6bff: VD7
- 0x1f6c00 - 0x1f6cff: reserved
- 0x1f6d00 - 0x1f6dff: VD7
- 0x1f6e00 - 0x1f7fff: reserved */
+/*
+ * Graphics IP version 12.55 brings a slight change to the 0xd800 range,
+ * switching it from the GT domain to the render domain.
+ *
+ * *Must* be sorted by offset ranges! See intel_fw_table_check().
+ */
+#define XEHP_FWRANGES(FW_RANGE_D800) \
+ GEN_FW_RANGE(0x0, 0x1fff, 0), /* \
+ 0x0 - 0xaff: reserved \
+ 0xb00 - 0x1fff: always on */ \
+ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), \
+ GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT), \
+ GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* \
+ 0x4b00 - 0x4fff: reserved \
+ 0x5000 - 0x51ff: always on */ \
+ GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), \
+ GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), \
+ GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), \
+ GEN_FW_RANGE(0x8160, 0x81ff, 0), /* \
+ 0x8160 - 0x817f: reserved \
+ 0x8180 - 0x81ff: always on */ \
+ GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), \
+ GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), \
+ GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /* \
+ 0x8500 - 0x87ff: gt \
+ 0x8800 - 0x8c7f: reserved \
+ 0x8c80 - 0x8cff: gt (DG2 only) */ \
+ GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /* \
+ 0x8d00 - 0x8dff: render (DG2 only) \
+ 0x8e00 - 0x8fff: reserved */ \
+ GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /* \
+ 0x9000 - 0x947f: gt \
+ 0x9480 - 0x94cf: reserved */ \
+ GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), \
+ GEN_FW_RANGE(0x9560, 0x967f, 0), /* \
+ 0x9560 - 0x95ff: always on \
+ 0x9600 - 0x967f: reserved */ \
+ GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* \
+ 0x9680 - 0x96ff: render (DG2 only) \
+ 0x9700 - 0x97ff: reserved */ \
+ GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* \
+ 0x9800 - 0xb4ff: gt \
+ 0xb500 - 0xbfff: reserved \
+ 0xc000 - 0xcfff: gt */ \
+ GEN_FW_RANGE(0xd000, 0xd7ff, 0), \
+ GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800), \
+ GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), \
+ GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), \
+ GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* \
+ 0xdd00 - 0xddff: gt \
+ 0xde00 - 0xde7f: reserved */ \
+ GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* \
+ 0xde80 - 0xdfff: render \
+ 0xe000 - 0xe0ff: reserved \
+ 0xe100 - 0xe8ff: render */ \
+ GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /* \
+ 0xe900 - 0xe9ff: gt \
+ 0xea00 - 0xefff: reserved \
+ 0xf000 - 0xffff: gt */ \
+ GEN_FW_RANGE(0x10000, 0x12fff, 0), /* \
+ 0x10000 - 0x11fff: reserved \
+ 0x12000 - 0x127ff: always on \
+ 0x12800 - 0x12fff: reserved */ \
+ GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */ \
+ GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \
+ 0x13200 - 0x133ff: VD2 (DG2 only) \
+ 0x13400 - 0x13fff: reserved */ \
+ GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \
+ GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \
+ GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \
+ GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \
+ GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \
+ GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \
+ 0x15000 - 0x15fff: gt (DG2 only) \
+ 0x16000 - 0x16dff: reserved */ \
+ GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \
+ GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \
+ 0x20000 - 0x20fff: VD0 (XEHPSDV only) \
+ 0x21000 - 0x21fff: reserved */ \
+ GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \
+ GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \
+ 0x24000 - 0x2407f: always on \
+ 0x24080 - 0x2417f: reserved */ \
+ GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* \
+ 0x24180 - 0x241ff: gt \
+ 0x24200 - 0x249ff: reserved */ \
+ GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* \
+ 0x24a00 - 0x24a7f: render \
+ 0x24a80 - 0x251ff: reserved */ \
+ GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /* \
+ 0x25200 - 0x252ff: gt \
+ 0x25300 - 0x25fff: reserved */ \
+ GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /* \
+ 0x26000 - 0x27fff: render \
+ 0x28000 - 0x29fff: reserved \
+ 0x2a000 - 0x2ffff: undocumented */ \
+ GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), \
+ GEN_FW_RANGE(0x40000, 0x1bffff, 0), \
+ GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* \
+ 0x1c0000 - 0x1c2bff: VD0 \
+ 0x1c2c00 - 0x1c2cff: reserved \
+ 0x1c2d00 - 0x1c2dff: VD0 \
+ 0x1c2e00 - 0x1c3eff: VD0 (DG2 only) \
+ 0x1c3f00 - 0x1c3fff: VD0 */ \
+ GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /* \
+ 0x1c4000 - 0x1c6bff: VD1 \
+ 0x1c6c00 - 0x1c6cff: reserved \
+ 0x1c6d00 - 0x1c6dff: VD1 \
+ 0x1c6e00 - 0x1c7fff: reserved */ \
+ GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* \
+ 0x1c8000 - 0x1ca0ff: VE0 \
+ 0x1ca100 - 0x1cbfff: reserved */ \
+ GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0), \
+ GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2), \
+ GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4), \
+ GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6), \
+ GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* \
+ 0x1d0000 - 0x1d2bff: VD2 \
+ 0x1d2c00 - 0x1d2cff: reserved \
+ 0x1d2d00 - 0x1d2dff: VD2 \
+ 0x1d2e00 - 0x1d3dff: VD2 (DG2 only) \
+ 0x1d3e00 - 0x1d3eff: reserved \
+ 0x1d3f00 - 0x1d3fff: VD2 */ \
+ GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /* \
+ 0x1d4000 - 0x1d6bff: VD3 \
+ 0x1d6c00 - 0x1d6cff: reserved \
+ 0x1d6d00 - 0x1d6dff: VD3 \
+ 0x1d6e00 - 0x1d7fff: reserved */ \
+ GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /* \
+ 0x1d8000 - 0x1da0ff: VE1 \
+ 0x1da100 - 0x1dffff: reserved */ \
+ GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /* \
+ 0x1e0000 - 0x1e2bff: VD4 \
+ 0x1e2c00 - 0x1e2cff: reserved \
+ 0x1e2d00 - 0x1e2dff: VD4 \
+ 0x1e2e00 - 0x1e3eff: reserved \
+ 0x1e3f00 - 0x1e3fff: VD4 */ \
+ GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /* \
+ 0x1e4000 - 0x1e6bff: VD5 \
+ 0x1e6c00 - 0x1e6cff: reserved \
+ 0x1e6d00 - 0x1e6dff: VD5 \
+ 0x1e6e00 - 0x1e7fff: reserved */ \
+ GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /* \
+ 0x1e8000 - 0x1ea0ff: VE2 \
+ 0x1ea100 - 0x1effff: reserved */ \
+ GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /* \
+ 0x1f0000 - 0x1f2bff: VD6 \
+ 0x1f2c00 - 0x1f2cff: reserved \
+ 0x1f2d00 - 0x1f2dff: VD6 \
+ 0x1f2e00 - 0x1f3eff: reserved \
+ 0x1f3f00 - 0x1f3fff: VD6 */ \
+ GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /* \
+ 0x1f4000 - 0x1f6bff: VD7 \
+ 0x1f6c00 - 0x1f6cff: reserved \
+ 0x1f6d00 - 0x1f6dff: VD7 \
+ 0x1f6e00 - 0x1f7fff: reserved */ \
GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
+
+static const struct intel_forcewake_range __xehp_fw_ranges[] = {
+ XEHP_FWRANGES(FORCEWAKE_GT)
+};
+
+static const struct intel_forcewake_range __dg2_fw_ranges[] = {
+ XEHP_FWRANGES(FORCEWAKE_RENDER)
};
static void
@@ -2084,7 +2111,11 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
return ret;
forcewake_early_sanitize(uncore, 0);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
+ ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fwtable);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
+ } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fwtable);
ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
--
2.25.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-23 17:43 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-23 17:42 [Intel-gfx] [PATCH v3 00/30] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 01/30] drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP() Matt Roper
2021-07-27 18:34 ` Yokoyama, Caz
2021-07-27 18:38 ` Matt Roper
2021-07-27 19:00 ` Yokoyama, Caz
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 02/30] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper
2021-07-23 17:54 ` Lucas De Marchi
2021-07-23 17:55 ` Matt Roper
2021-07-23 19:10 ` [Intel-gfx] [PATCH v4 2/2] " Matt Roper
2021-07-24 0:47 ` Lucas De Marchi
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 03/30] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 04/30] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 05/30] drm/i915/xehp: Xe_HP forcewake support Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 06/30] drm/i915/xehp: handle new steering options Matt Roper
2021-07-27 19:11 ` Yokoyama, Caz
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 07/30] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 08/30] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 09/30] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 10/30] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 11/30] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 12/30] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 13/30] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 14/30] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 15/30] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-23 17:42 ` Matt Roper [this message]
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 17/30] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 18/30] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 19/30] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 20/30] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 21/30] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-29 15:08 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 22/30] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-29 15:14 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 23/30] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper
2021-07-29 15:06 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 24/30] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 25/30] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 26/30] drm/i915/dg2: Update modeset sequences Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 27/30] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper
2021-07-24 4:19 ` kernel test robot
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 28/30] drm/i915/dg2: Update lane disable power state during PSR Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 29/30] drm/i915/dg2: Update to bigjoiner path Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 30/30] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-07-23 21:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev6) Patchwork
2021-07-23 21:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-23 21:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210723174239.1551352-17-matthew.d.roper@intel.com \
--to=matthew.d.roper@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).