From: Matt Roper <matthew.d.roper@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Tomas Winkler <tomas.winkler@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3 02/30] drm/i915/xehp: Extra media engines - Part 1 (engine definitions)
Date: Fri, 23 Jul 2021 10:55:32 -0700 [thread overview]
Message-ID: <20210723175532.GE1229765@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20210723175407.tiu6zy5z4g3nmn23@ldmartin-desk2>
On Fri, Jul 23, 2021 at 10:54:07AM -0700, Lucas De Marchi wrote:
> On Fri, Jul 23, 2021 at 10:42:11AM -0700, Matt Roper wrote:
> > From: John Harrison <John.C.Harrison@Intel.com>
> >
> > Xe_HP can have a lot of extra media engines. This patch adds the basic
> > definitions for them.
> >
> > v2:
> > - Re-order intel_gt_info and intel_device_info slightly to avoid
> > unnecessary padding now that we've increased the size of
> > intel_engine_mask_t. (Tvrtko)
> > v3:
> > - Drop the .hw_id assignments. (Lucas)
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 ++--
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 44 ++++++++++++++++++++
> > drivers/gpu/drm/i915/gt/intel_engine_types.h | 14 +++++--
> > drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 ++-
> > drivers/gpu/drm/i915/i915_pci.c | 5 ++-
> > drivers/gpu/drm/i915/i915_reg.h | 6 +++
> > drivers/gpu/drm/i915/intel_device_info.h | 3 +-
> > 7 files changed, 71 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index b29eb9fd0009..461844dffd7e 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -279,7 +279,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
> > if (mode & EMIT_INVALIDATE)
> > aux_inv = rq->engine->mask & ~BIT(BCS0);
> > if (aux_inv)
> > - cmd += 2 * hweight8(aux_inv) + 2;
> > + cmd += 2 * hweight32(aux_inv) + 2;
> >
> > cs = intel_ring_begin(rq, cmd);
> > if (IS_ERR(cs))
> > @@ -313,9 +313,8 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
> > struct intel_engine_cs *engine;
> > unsigned int tmp;
> >
> > - *cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));
> > - for_each_engine_masked(engine, rq->engine->gt,
> > - aux_inv, tmp) {
> > + *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));
> > + for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {
> > *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
> > *cs++ = AUX_INV;
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 4168b9fc59e1..1fc1bd4ad5e3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -101,6 +101,34 @@ static const struct engine_info intel_engines[] = {
> > { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
> > },
> > },
> > + [VCS4] = {
> > + .class = VIDEO_DECODE_CLASS,
> > + .instance = 4,
> > + .mmio_bases = {
> > + { .graphics_ver = 11, .base = XEHP_BSD5_RING_BASE }
>
> another thing I raised in my previous review was this ver == 11 here.
> Was this not changed on purpose ?
Woops, looks like I missed that comment in the mix of discussion about
hw_id. I'll respin this one.
Matt
>
> Lucas De Marchi
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-23 17:55 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-23 17:42 [Intel-gfx] [PATCH v3 00/30] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 01/30] drm/i915/xehpsdv: Correct parameters for IS_XEHPSDV_GT_STEP() Matt Roper
2021-07-27 18:34 ` Yokoyama, Caz
2021-07-27 18:38 ` Matt Roper
2021-07-27 19:00 ` Yokoyama, Caz
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 02/30] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper
2021-07-23 17:54 ` Lucas De Marchi
2021-07-23 17:55 ` Matt Roper [this message]
2021-07-23 19:10 ` [Intel-gfx] [PATCH v4 2/2] " Matt Roper
2021-07-24 0:47 ` Lucas De Marchi
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 03/30] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 04/30] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 05/30] drm/i915/xehp: Xe_HP forcewake support Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 06/30] drm/i915/xehp: handle new steering options Matt Roper
2021-07-27 19:11 ` Yokoyama, Caz
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 07/30] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 08/30] drm/i915/xehp: Changes to ss/eu definitions Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 09/30] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 10/30] drm/i915/xehpsdv: Add compute DSS type Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 11/30] drm/i915/xehpsdv: Define steering tables Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 12/30] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 13/30] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 14/30] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 15/30] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 16/30] drm/i915/dg2: Add forcewake table Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 17/30] drm/i915/dg2: Update LNCF steering ranges Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 18/30] drm/i915/dg2: Add SQIDI steering Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 19/30] drm/i915/dg2: Add new LRI reg offsets Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 20/30] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 21/30] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper
2021-07-29 15:08 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 22/30] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
2021-07-29 15:14 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 23/30] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper
2021-07-29 15:06 ` Matt Atwood
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 24/30] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 25/30] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 26/30] drm/i915/dg2: Update modeset sequences Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 27/30] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper
2021-07-24 4:19 ` kernel test robot
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 28/30] drm/i915/dg2: Update lane disable power state during PSR Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 29/30] drm/i915/dg2: Update to bigjoiner path Matt Roper
2021-07-23 17:42 ` [Intel-gfx] [PATCH v3 30/30] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper
2021-07-23 21:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms (rev6) Patchwork
2021-07-23 21:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-23 21:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210723175532.GE1229765@mdroper-desk1.amr.corp.intel.com \
--to=matthew.d.roper@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=lucas.demarchi@intel.com \
--cc=tomas.winkler@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).