[Intel-gfx] [PATCH 00/30] Remove CNL support

[Intel-gfx] [PATCH 00/30] Remove CNL support

[Lucas De Marchi]

Patches 1 and 2 are already being reviewed elsewhere. Discussion on 2nd
patch made me revive something I started after comment from Ville
at https://patchwork.freedesktop.org/patch/428168/?series=88988&rev=1#comment_768918

This removes CNL completely from the driver, while trying to rename
functions and macros where appropriate (usually to GLK when dealing with
display or with ICL otherwise). It starts with display, which is more
straightforward, and then proceed to the rest of i915.

diff stat removing 1600 lines of dead code seems to pay the pain of
doing this.


Lucas De Marchi (30):
  drm/i915: fix not reading DSC disable fuse in GLK
  drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
  drm/i915/display: remove PORT_F workaround for CNL
  drm/i915/display: remove explicit CNL handling from intel_cdclk.c
  drm/i915/display: remove explicit CNL handling from intel_color.c
  drm/i915/display: remove explicit CNL handling from intel_combo_phy.c
  drm/i915/display: remove explicit CNL handling from intel_crtc.c
  drm/i915/display: remove explicit CNL handling from intel_ddi.c
  drm/i915/display: remove explicit CNL handling from
    intel_display_debugfs.c
  drm/i915/display: remove explicit CNL handling from intel_dmc.c
  drm/i915/display: remove explicit CNL handling from intel_dp.c
  drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c
  drm/i915/display: remove explicit CNL handling from intel_vdsc.c
  drm/i915/display: remove explicit CNL handling from
    skl_universal_plane.c
  drm/i915/display: remove explicit CNL handling from
    intel_display_power.c
  drm/i915/display: remove CNL ddi buf translation tables
  drm/i915/display: rename CNL references in skl_scaler.c
  drm/i915: remove explicit CNL handling from i915_irq.c
  drm/i915: remove explicit CNL handling from intel_pm.c
  drm/i915: remove explicit CNL handling from intel_mocs.c
  drm/i915: remove explicit CNL handling from intel_pch.c
  drm/i915: remove explicit CNL handling from intel_wopcm.c
  drm/i915/gt: remove explicit CNL handling from intel_sseu.c
  drm/i915: rename CNL references in intel_dram.c
  drm/i915/gt: rename CNL references in intel_engine.h
  drm/i915: finish removal of CNL
  drm/i915: remove GRAPHICS_VER == 10
  drm/i915: rename/remove CNL registers
  drm/i915: replace random CNL comments
  drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER

 drivers/gpu/drm/i915/display/intel_bios.c     |   8 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  72 +-
 drivers/gpu/drm/i915/display/intel_color.c    |   5 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    | 106 +--
 drivers/gpu/drm/i915/display/intel_crtc.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 266 +-------
 .../drm/i915/display/intel_ddi_buf_trans.c    | 616 +++++-------------
 .../drm/i915/display/intel_ddi_buf_trans.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
 .../drm/i915/display/intel_display_debugfs.c  |   2 +-
 .../drm/i915/display/intel_display_power.c    | 289 --------
 .../drm/i915/display/intel_display_power.h    |   2 -
 drivers/gpu/drm/i915/display/intel_dmc.c      |   9 -
 drivers/gpu/drm/i915/display/intel_dp.c       |  35 +-
 drivers/gpu/drm/i915/display/intel_dp_aux.c   |   1 -
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 586 +++--------------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   1 -
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |   2 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |   5 +-
 drivers/gpu/drm/i915/display/skl_scaler.c     |  10 +-
 .../drm/i915/display/skl_universal_plane.c    |  14 +-
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c    |   1 -
 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c       |  10 +-
 drivers/gpu/drm/i915/gt/intel_engine.h        |   2 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |   3 -
 drivers/gpu/drm/i915/gt/intel_ggtt.c          |   4 +-
 .../gpu/drm/i915/gt/intel_gt_clock_utils.c    |  10 +-
 drivers/gpu/drm/i915/gt/intel_gtt.c           |   6 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  42 +-
 drivers/gpu/drm/i915/gt/intel_mocs.c          |   2 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |   2 +-
 drivers/gpu/drm/i915/gt/intel_rps.c           |   4 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c          |  79 ---
 drivers/gpu/drm/i915/gt/intel_sseu.h          |   2 +-
 drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c  |   6 +-
 drivers/gpu/drm/i915/gvt/gtt.c                |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |   6 +-
 drivers/gpu/drm/i915/i915_drv.h               |  13 +-
 drivers/gpu/drm/i915/i915_irq.c               |   7 +-
 drivers/gpu/drm/i915/i915_pci.c               |  23 +-
 drivers/gpu/drm/i915/i915_perf.c              |  22 +-
 drivers/gpu/drm/i915/i915_reg.h               | 245 ++-----
 drivers/gpu/drm/i915/intel_device_info.c      |  23 +-
 drivers/gpu/drm/i915/intel_device_info.h      |   4 +-
 drivers/gpu/drm/i915/intel_dram.c             |  32 +-
 drivers/gpu/drm/i915/intel_pch.c              |   5 +-
 drivers/gpu/drm/i915/intel_pm.c               |  41 +-
 drivers/gpu/drm/i915/intel_wopcm.c            |  10 +-
 48 files changed, 516 insertions(+), 2128 deletions(-)

-- 
2.31.1

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[Intel-gfx] [PATCH 01/30] drm/i915: fix not reading DSC disable fuse in GLK

[Lucas De Marchi]

We were using GRAPHICS_VER() to handle SKL_DFSM register, which means we
were not handling GLK correctly since that has GRAPHICS_VER == 9, but
DISPLAY_VER == 10. Switch the entire branch to check DISPLAY_VER
which makes it more in line with Bspec.

Even though the Bspec has an exception for RKL in
TGL_DFSM_PIPE_D_DISABLE, we don't have to do anything as the bit has
disable semantic and RKL doesn't have pipe D.

Bspec: 50075, 7548
Fixes: 2b5a4562edd0 ("drm/i915/display: Simplify GLK display version tests")
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d5cf5977938a..99b51c292942 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -335,7 +335,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 			info->pipe_mask &= ~BIT(PIPE_C);
 			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 		}
-	} else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {
+	} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
 		u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
 
 		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
@@ -350,7 +350,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 			info->pipe_mask &= ~BIT(PIPE_C);
 			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 		}
-		if (GRAPHICS_VER(dev_priv) >= 12 &&
+
+		if (DISPLAY_VER(dev_priv) >= 12 &&
 		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
 			info->pipe_mask &= ~BIT(PIPE_D);
 			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
@@ -362,10 +363,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
 			info->display.has_fbc = 0;
 
-		if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
+		if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
 			info->display.has_dmc = 0;
 
-		if (GRAPHICS_VER(dev_priv) >= 10 &&
+		if (DISPLAY_VER(dev_priv) >= 10 &&
 		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
 			info->display.has_dsc = 0;
 	}
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 01/30] drm/i915: fix not reading DSC disable fuse in GLK

[Matt Roper]

On Fri, Jul 23, 2021 at 05:10:45PM -0700, Lucas De Marchi wrote:
> We were using GRAPHICS_VER() to handle SKL_DFSM register, which means we
> were not handling GLK correctly since that has GRAPHICS_VER == 9, but
> DISPLAY_VER == 10. Switch the entire branch to check DISPLAY_VER
> which makes it more in line with Bspec.
> 
> Even though the Bspec has an exception for RKL in
> TGL_DFSM_PIPE_D_DISABLE, we don't have to do anything as the bit has
> disable semantic and RKL doesn't have pipe D.
> 
> Bspec: 50075, 7548
> Fixes: 2b5a4562edd0 ("drm/i915/display: Simplify GLK display version tests")
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_device_info.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index d5cf5977938a..99b51c292942 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -335,7 +335,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			info->pipe_mask &= ~BIT(PIPE_C);
>  			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
>  		}
> -	} else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {
> +	} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
>  		u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
>  
>  		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
> @@ -350,7 +350,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			info->pipe_mask &= ~BIT(PIPE_C);
>  			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
>  		}
> -		if (GRAPHICS_VER(dev_priv) >= 12 &&
> +
> +		if (DISPLAY_VER(dev_priv) >= 12 &&
>  		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
>  			info->pipe_mask &= ~BIT(PIPE_D);
>  			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
> @@ -362,10 +363,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
>  			info->display.has_fbc = 0;
>  
> -		if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
> +		if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
>  			info->display.has_dmc = 0;
>  
> -		if (GRAPHICS_VER(dev_priv) >= 10 &&
> +		if (DISPLAY_VER(dev_priv) >= 10 &&
>  		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
>  			info->display.has_dsc = 0;
>  	}
> -- 
> 2.31.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH 02/30] drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()

[Lucas De Marchi]

Commit 5a9d38b20a5a ("drm/i915/display: hide workaround for broken vbt
in intel_bios.c") moved the workaround for broken or missing VBT to
intel_bios.c. However is_port_valid() only protects the handling of
different skus of the same display version. Since in
intel_setup_outputs() we share the code path with version 9, this would
also create port F for SKL/KBL, which does not exist.

Missing VBT can be reproduced when starting a headless QEMU with no
opregion available.

Avoid the issue by splitting versions 9 and 10 in intel_setup_outputs(),
which also makes it more clear what code path it's taking for each
version.

v2: move generic display version after Geminilake since that one has
a different set of outputs

Fixes: 5a9d38b20a5a ("drm/i915/display: hide workaround for broken vbt in intel_bios.c")
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reported-by: Christoph Hellwig <hch@infradead.org>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210722232922.3796835-1-lucas.demarchi@intel.com
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 400f062d785a..4633d4e00e6b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11409,13 +11409,19 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
 		vlv_dsi_init(dev_priv);
-	} else if (DISPLAY_VER(dev_priv) >= 9) {
+	} else if (DISPLAY_VER(dev_priv) == 10) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
 		intel_ddi_init(dev_priv, PORT_D);
 		intel_ddi_init(dev_priv, PORT_E);
 		intel_ddi_init(dev_priv, PORT_F);
+	} else if (DISPLAY_VER(dev_priv) >= 9) {
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_B);
+		intel_ddi_init(dev_priv, PORT_C);
+		intel_ddi_init(dev_priv, PORT_D);
+		intel_ddi_init(dev_priv, PORT_E);
 	} else if (HAS_DDI(dev_priv)) {
 		u32 found;
 
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 02/30] drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()

[Christoph Hellwig]

Still tests fine:

Tested-by: Christoph Hellwig <hch@lst.de>
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Re: [Intel-gfx] [PATCH 02/30] drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()

[Lucas De Marchi]

On Sat, Jul 24, 2021 at 06:41:21PM +0100, Christoph Hellwig wrote:
>Still tests fine:
>
>Tested-by: Christoph Hellwig <hch@lst.de>

I just pushed this  to drm-intel-next as part of another series and
added your Tested-by.

Rodrigo, can you pick this up for -fixes? This should go with your other
patch to fix the port mask, too.

Thanks for the bug report and test.

Lucas De Marchi
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Re: [Intel-gfx] [PATCH 02/30] drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()

[Rodrigo Vivi]

On Sat, Jul 24, 2021 at 10:02:15PM -0700, Lucas De Marchi wrote:
> On Sat, Jul 24, 2021 at 06:41:21PM +0100, Christoph Hellwig wrote:
> > Still tests fine:
> > 
> > Tested-by: Christoph Hellwig <hch@lst.de>
> 
> I just pushed this  to drm-intel-next as part of another series and
> added your Tested-by.
> 
> Rodrigo, can you pick this up for -fixes? This should go with your other
> patch to fix the port mask, too.

done.

But while doing this and reviewing this series at the same time
I got myself wondering if we shouldn't remove the PORT_F support
entirely...

> 
> Thanks for the bug report and test.
> 
> Lucas De Marchi
> _______________________________________________
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Re: [Intel-gfx] [PATCH 02/30] drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()

[Lucas De Marchi]

On Mon, Jul 26, 2021 at 06:20:03AM -0400, Rodrigo Vivi wrote:
>On Sat, Jul 24, 2021 at 10:02:15PM -0700, Lucas De Marchi wrote:
>> On Sat, Jul 24, 2021 at 06:41:21PM +0100, Christoph Hellwig wrote:
>> > Still tests fine:
>> >
>> > Tested-by: Christoph Hellwig <hch@lst.de>
>>
>> I just pushed this  to drm-intel-next as part of another series and
>> added your Tested-by.
>>
>> Rodrigo, can you pick this up for -fixes? This should go with your other
>> patch to fix the port mask, too.
>
>done.
>
>But while doing this and reviewing this series at the same time
>I got myself wondering if we shouldn't remove the PORT_F support
>entirely...

well, there is still ICL with some skus having it. I'm not sure we
actually have that sku out in the wild, but if we do, we wouldn't be
able to remove it.

Lucas De Marchi

>
>>
>> Thanks for the bug report and test.
>>
>> Lucas De Marchi
>> _______________________________________________
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[Intel-gfx] [PATCH 03/30] drm/i915/display: remove PORT_F workaround for CNL

[Lucas De Marchi]

Explicit support for CNL is being removed from the driver as it's not
expected to work. Remove the workaround for PORT_F from
display/intel_bios.c so we can also remove the generic DISPLAY_VER == 10
calls to intel_ddi_init(): the only platform with that display version
is already handled separately (GLK).

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c    | 6 +++---
 drivers/gpu/drm/i915/display/intel_display.c | 7 -------
 2 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index aa667fa71158..4172c8ee6aa6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1871,12 +1871,12 @@ intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata)
 static bool is_port_valid(struct drm_i915_private *i915, enum port port)
 {
 	/*
-	 * On some ICL/CNL SKUs port F is not present, but broken VBTs mark
+	 * On some ICL SKUs port F is not present, but broken VBTs mark
 	 * the port as present. Only try to initialize port F for the
 	 * SKUs that may actually have it.
 	 */
-	if (port == PORT_F && (IS_ICELAKE(i915) || IS_CANNONLAKE(i915)))
-		return IS_ICL_WITH_PORT_F(i915) || IS_CNL_WITH_PORT_F(i915);
+	if (port == PORT_F && IS_ICELAKE(i915))
+		return IS_ICL_WITH_PORT_F(i915);
 
 	return true;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4633d4e00e6b..ee6d5f8de24b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11409,13 +11409,6 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
 		vlv_dsi_init(dev_priv);
-	} else if (DISPLAY_VER(dev_priv) == 10) {
-		intel_ddi_init(dev_priv, PORT_A);
-		intel_ddi_init(dev_priv, PORT_B);
-		intel_ddi_init(dev_priv, PORT_C);
-		intel_ddi_init(dev_priv, PORT_D);
-		intel_ddi_init(dev_priv, PORT_E);
-		intel_ddi_init(dev_priv, PORT_F);
 	} else if (DISPLAY_VER(dev_priv) >= 9) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 03/30] drm/i915/display: remove PORT_F workaround for CNL

[Matt Roper]

On Fri, Jul 23, 2021 at 05:10:47PM -0700, Lucas De Marchi wrote:
> Explicit support for CNL is being removed from the driver as it's not
> expected to work. Remove the workaround for PORT_F from
> display/intel_bios.c so we can also remove the generic DISPLAY_VER == 10
> calls to intel_ddi_init(): the only platform with that display version
> is already handled separately (GLK).
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c    | 6 +++---
>  drivers/gpu/drm/i915/display/intel_display.c | 7 -------
>  2 files changed, 3 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index aa667fa71158..4172c8ee6aa6 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1871,12 +1871,12 @@ intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata)
>  static bool is_port_valid(struct drm_i915_private *i915, enum port port)
>  {
>  	/*
> -	 * On some ICL/CNL SKUs port F is not present, but broken VBTs mark
> +	 * On some ICL SKUs port F is not present, but broken VBTs mark
>  	 * the port as present. Only try to initialize port F for the
>  	 * SKUs that may actually have it.
>  	 */
> -	if (port == PORT_F && (IS_ICELAKE(i915) || IS_CANNONLAKE(i915)))
> -		return IS_ICL_WITH_PORT_F(i915) || IS_CNL_WITH_PORT_F(i915);
> +	if (port == PORT_F && IS_ICELAKE(i915))
> +		return IS_ICL_WITH_PORT_F(i915);
>  
>  	return true;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4633d4e00e6b..ee6d5f8de24b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11409,13 +11409,6 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>  		intel_ddi_init(dev_priv, PORT_B);
>  		intel_ddi_init(dev_priv, PORT_C);
>  		vlv_dsi_init(dev_priv);
> -	} else if (DISPLAY_VER(dev_priv) == 10) {
> -		intel_ddi_init(dev_priv, PORT_A);
> -		intel_ddi_init(dev_priv, PORT_B);
> -		intel_ddi_init(dev_priv, PORT_C);
> -		intel_ddi_init(dev_priv, PORT_D);
> -		intel_ddi_init(dev_priv, PORT_E);
> -		intel_ddi_init(dev_priv, PORT_F);
>  	} else if (DISPLAY_VER(dev_priv) >= 9) {
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_B);
> -- 
> 2.31.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 04/30] drm/i915/display: remove explicit CNL handling from intel_cdclk.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
any checks and supporting code for CNL. Remove code and rename
functions/macros accordingly.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++-----------------
 drivers/gpu/drm/i915/i915_reg.h            |  4 +-
 2 files changed, 18 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ff35c29508d5..34fa4130d5c4 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1195,17 +1195,6 @@ static const struct intel_cdclk_vals glk_cdclk_table[] = {
 	{}
 };
 
-static const struct intel_cdclk_vals cnl_cdclk_table[] = {
-	{ .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
-	{ .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
-	{ .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
-
-	{ .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
-	{ .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
-	{ .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
-	{}
-};
-
 static const struct intel_cdclk_vals icl_cdclk_table[] = {
 	{ .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
 	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
@@ -1339,16 +1328,6 @@ static u8 bxt_calc_voltage_level(int cdclk)
 	return DIV_ROUND_UP(cdclk, 25000);
 }
 
-static u8 cnl_calc_voltage_level(int cdclk)
-{
-	if (cdclk > 336000)
-		return 2;
-	else if (cdclk > 168000)
-		return 1;
-	else
-		return 0;
-}
-
 static u8 icl_calc_voltage_level(int cdclk)
 {
 	if (cdclk > 556800)
@@ -1383,15 +1362,6 @@ static u8 tgl_calc_voltage_level(int cdclk)
 		return 0;
 }
 
-static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
-			       struct intel_cdclk_config *cdclk_config)
-{
-	if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
-		cdclk_config->ref = 24000;
-	else
-		cdclk_config->ref = 19200;
-}
-
 static void icl_readout_refclk(struct drm_i915_private *dev_priv,
 			       struct intel_cdclk_config *cdclk_config)
 {
@@ -1422,8 +1392,6 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
 		cdclk_config->ref = 38400;
 	else if (DISPLAY_VER(dev_priv) >= 11)
 		icl_readout_refclk(dev_priv, cdclk_config);
-	else if (IS_CANNONLAKE(dev_priv))
-		cnl_readout_refclk(dev_priv, cdclk_config);
 	else
 		cdclk_config->ref = 19200;
 
@@ -1439,11 +1407,11 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
 	}
 
 	/*
-	 * CNL+ have the ratio directly in the PLL enable register, gen9lp had
-	 * it in a separate PLL control register.
+	 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
+	 * gen9lp had it in a separate PLL control register.
 	 */
-	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
-		ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
+	if (DISPLAY_VER(dev_priv) >= 11)
+		ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
 	else
 		ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
 
@@ -1530,7 +1498,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
 	dev_priv->cdclk.hw.vco = vco;
 }
 
-static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
+static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
 {
 	intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
 		     BXT_DE_PLL_PLL_ENABLE, 0);
@@ -1542,12 +1510,12 @@ static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
 	dev_priv->cdclk.hw.vco = 0;
 }
 
-static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
+static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
 {
 	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
 	u32 val;
 
-	val = CNL_CDCLK_PLL_RATIO(ratio);
+	val = ICL_CDCLK_PLL_RATIO(ratio);
 	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
 
 	val |= BXT_DE_PLL_PLL_ENABLE;
@@ -1566,7 +1534,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
 	u32 val;
 
 	/* Write PLL ratio without disabling */
-	val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
+	val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
 	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
 
 	/* Submit freq change request */
@@ -1635,7 +1603,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	int ret;
 
 	/* Inform power controller of upcoming frequency change. */
-	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 11)
 		ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 					SKL_CDCLK_PREPARE_FOR_CHANGE,
 					SKL_CDCLK_READY_FOR_CHANGE,
@@ -1659,13 +1627,13 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
 		if (dev_priv->cdclk.hw.vco != vco)
 			adlp_cdclk_pll_crawl(dev_priv, vco);
-	} else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
+	} else if (DISPLAY_VER(dev_priv) >= 11) {
 		if (dev_priv->cdclk.hw.vco != 0 &&
 		    dev_priv->cdclk.hw.vco != vco)
-			cnl_cdclk_pll_disable(dev_priv);
+			icl_cdclk_pll_disable(dev_priv);
 
 		if (dev_priv->cdclk.hw.vco != vco)
-			cnl_cdclk_pll_enable(dev_priv, vco);
+			icl_cdclk_pll_enable(dev_priv, vco);
 	} else {
 		if (dev_priv->cdclk.hw.vco != 0 &&
 		    dev_priv->cdclk.hw.vco != vco)
@@ -1691,7 +1659,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	if (pipe != INVALID_PIPE)
 		intel_wait_for_vblank(dev_priv, pipe);
 
-	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
+	if (DISPLAY_VER(dev_priv) >= 11) {
 		ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 					      cdclk_config->voltage_level);
 	} else {
@@ -1716,7 +1684,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 
 	intel_update_cdclk(dev_priv);
 
-	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 11)
 		/*
 		 * Can't read out the voltage level :(
 		 * Let's just assume everything is as expected.
@@ -2125,7 +2093,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	    crtc_state->port_clock >= 540000 &&
 	    crtc_state->lane_count == 4) {
 		if (DISPLAY_VER(dev_priv) == 10) {
-			/* Display WA #1145: glk,cnl */
+			/* Display WA #1145: glk */
 			min_cdclk = max(316800, min_cdclk);
 		} else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
 			/* Display WA #1144: skl,bxt */
@@ -2246,7 +2214,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
 
 /*
  * Account for port clock min voltage level requirements.
- * This only really does something on CNL+ but can be
+ * This only really does something on DISPLA_VER >= 11 but can be
  * called on earlier platforms as well.
  *
  * Note that this functions assumes that 0 is
@@ -2660,8 +2628,6 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 			dev_priv->max_cdclk_freq = 648000;
 		else
 			dev_priv->max_cdclk_freq = 652800;
-	} else if (IS_CANNONLAKE(dev_priv)) {
-		dev_priv->max_cdclk_freq = 528000;
 	} else if (IS_GEMINILAKE(dev_priv)) {
 		dev_priv->max_cdclk_freq = 316800;
 	} else if (IS_BROXTON(dev_priv)) {
@@ -2925,12 +2891,6 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
-	} else if (IS_CANNONLAKE(dev_priv)) {
-		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
-		dev_priv->cdclk.table = cnl_cdclk_table;
 	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8e1392028184..6a894ffd91e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11016,8 +11016,8 @@ enum skl_power_gate {
 #define   BXT_DE_PLL_LOCK		(1 << 30)
 #define   BXT_DE_PLL_FREQ_REQ		(1 << 23)
 #define   BXT_DE_PLL_FREQ_REQ_ACK	(1 << 22)
-#define   CNL_CDCLK_PLL_RATIO(x)	(x)
-#define   CNL_CDCLK_PLL_RATIO_MASK	0xff
+#define   ICL_CDCLK_PLL_RATIO(x)	(x)
+#define   ICL_CDCLK_PLL_RATIO_MASK	0xff
 
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 04/30] drm/i915/display: remove explicit CNL handling from intel_cdclk.c

[Matt Roper]

On Fri, Jul 23, 2021 at 05:10:48PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
> any checks and supporting code for CNL. Remove code and rename
> functions/macros accordingly.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++-----------------
>  drivers/gpu/drm/i915/i915_reg.h            |  4 +-
>  2 files changed, 18 insertions(+), 58 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ff35c29508d5..34fa4130d5c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1195,17 +1195,6 @@ static const struct intel_cdclk_vals glk_cdclk_table[] = {
>  	{}
>  };
>  
> -static const struct intel_cdclk_vals cnl_cdclk_table[] = {
> -	{ .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
> -	{ .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
> -	{ .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
> -
> -	{ .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
> -	{ .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
> -	{ .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
> -	{}
> -};
> -
>  static const struct intel_cdclk_vals icl_cdclk_table[] = {
>  	{ .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
>  	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> @@ -1339,16 +1328,6 @@ static u8 bxt_calc_voltage_level(int cdclk)
>  	return DIV_ROUND_UP(cdclk, 25000);
>  }
>  
> -static u8 cnl_calc_voltage_level(int cdclk)
> -{
> -	if (cdclk > 336000)
> -		return 2;
> -	else if (cdclk > 168000)
> -		return 1;
> -	else
> -		return 0;
> -}
> -
>  static u8 icl_calc_voltage_level(int cdclk)
>  {
>  	if (cdclk > 556800)
> @@ -1383,15 +1362,6 @@ static u8 tgl_calc_voltage_level(int cdclk)
>  		return 0;
>  }
>  
> -static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
> -			       struct intel_cdclk_config *cdclk_config)
> -{
> -	if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
> -		cdclk_config->ref = 24000;
> -	else
> -		cdclk_config->ref = 19200;
> -}
> -
>  static void icl_readout_refclk(struct drm_i915_private *dev_priv,
>  			       struct intel_cdclk_config *cdclk_config)
>  {
> @@ -1422,8 +1392,6 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
>  		cdclk_config->ref = 38400;
>  	else if (DISPLAY_VER(dev_priv) >= 11)
>  		icl_readout_refclk(dev_priv, cdclk_config);
> -	else if (IS_CANNONLAKE(dev_priv))
> -		cnl_readout_refclk(dev_priv, cdclk_config);
>  	else
>  		cdclk_config->ref = 19200;
>  
> @@ -1439,11 +1407,11 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
>  	}
>  
>  	/*
> -	 * CNL+ have the ratio directly in the PLL enable register, gen9lp had
> -	 * it in a separate PLL control register.
> +	 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
> +	 * gen9lp had it in a separate PLL control register.
>  	 */
> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> -		ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
> +	if (DISPLAY_VER(dev_priv) >= 11)
> +		ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
>  	else
>  		ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
>  
> @@ -1530,7 +1498,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
>  	dev_priv->cdclk.hw.vco = vco;
>  }
>  
> -static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
> +static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
>  {
>  	intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
>  		     BXT_DE_PLL_PLL_ENABLE, 0);
> @@ -1542,12 +1510,12 @@ static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
>  	dev_priv->cdclk.hw.vco = 0;
>  }
>  
> -static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
> +static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
>  {
>  	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
>  	u32 val;
>  
> -	val = CNL_CDCLK_PLL_RATIO(ratio);
> +	val = ICL_CDCLK_PLL_RATIO(ratio);
>  	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
>  
>  	val |= BXT_DE_PLL_PLL_ENABLE;
> @@ -1566,7 +1534,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
>  	u32 val;
>  
>  	/* Write PLL ratio without disabling */
> -	val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
> +	val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
>  	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
>  
>  	/* Submit freq change request */
> @@ -1635,7 +1603,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	int ret;
>  
>  	/* Inform power controller of upcoming frequency change. */
> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> +	if (DISPLAY_VER(dev_priv) >= 11)
>  		ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
>  					SKL_CDCLK_PREPARE_FOR_CHANGE,
>  					SKL_CDCLK_READY_FOR_CHANGE,
> @@ -1659,13 +1627,13 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
>  		if (dev_priv->cdclk.hw.vco != vco)
>  			adlp_cdclk_pll_crawl(dev_priv, vco);
> -	} else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> +	} else if (DISPLAY_VER(dev_priv) >= 11) {
>  		if (dev_priv->cdclk.hw.vco != 0 &&
>  		    dev_priv->cdclk.hw.vco != vco)
> -			cnl_cdclk_pll_disable(dev_priv);
> +			icl_cdclk_pll_disable(dev_priv);
>  
>  		if (dev_priv->cdclk.hw.vco != vco)
> -			cnl_cdclk_pll_enable(dev_priv, vco);
> +			icl_cdclk_pll_enable(dev_priv, vco);
>  	} else {
>  		if (dev_priv->cdclk.hw.vco != 0 &&
>  		    dev_priv->cdclk.hw.vco != vco)
> @@ -1691,7 +1659,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  	if (pipe != INVALID_PIPE)
>  		intel_wait_for_vblank(dev_priv, pipe);
>  
> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> +	if (DISPLAY_VER(dev_priv) >= 11) {
>  		ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
>  					      cdclk_config->voltage_level);
>  	} else {
> @@ -1716,7 +1684,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  
>  	intel_update_cdclk(dev_priv);
>  
> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> +	if (DISPLAY_VER(dev_priv) >= 11)
>  		/*
>  		 * Can't read out the voltage level :(
>  		 * Let's just assume everything is as expected.
> @@ -2125,7 +2093,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	    crtc_state->port_clock >= 540000 &&
>  	    crtc_state->lane_count == 4) {
>  		if (DISPLAY_VER(dev_priv) == 10) {
> -			/* Display WA #1145: glk,cnl */
> +			/* Display WA #1145: glk */
>  			min_cdclk = max(316800, min_cdclk);
>  		} else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
>  			/* Display WA #1144: skl,bxt */
> @@ -2246,7 +2214,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
>  
>  /*
>   * Account for port clock min voltage level requirements.
> - * This only really does something on CNL+ but can be
> + * This only really does something on DISPLA_VER >= 11 but can be
>   * called on earlier platforms as well.
>   *
>   * Note that this functions assumes that 0 is
> @@ -2660,8 +2628,6 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>  			dev_priv->max_cdclk_freq = 648000;
>  		else
>  			dev_priv->max_cdclk_freq = 652800;
> -	} else if (IS_CANNONLAKE(dev_priv)) {
> -		dev_priv->max_cdclk_freq = 528000;
>  	} else if (IS_GEMINILAKE(dev_priv)) {
>  		dev_priv->max_cdclk_freq = 316800;
>  	} else if (IS_BROXTON(dev_priv)) {
> @@ -2925,12 +2891,6 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
>  		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
>  		dev_priv->cdclk.table = icl_cdclk_table;
> -	} else if (IS_CANNONLAKE(dev_priv)) {
> -		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
> -		dev_priv->cdclk.table = cnl_cdclk_table;
>  	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
>  		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8e1392028184..6a894ffd91e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11016,8 +11016,8 @@ enum skl_power_gate {
>  #define   BXT_DE_PLL_LOCK		(1 << 30)
>  #define   BXT_DE_PLL_FREQ_REQ		(1 << 23)
>  #define   BXT_DE_PLL_FREQ_REQ_ACK	(1 << 22)
> -#define   CNL_CDCLK_PLL_RATIO(x)	(x)
> -#define   CNL_CDCLK_PLL_RATIO_MASK	0xff
> +#define   ICL_CDCLK_PLL_RATIO(x)	(x)
> +#define   ICL_CDCLK_PLL_RATIO_MASK	0xff

We could take this opportunity to switch to REG_GENMASK, REG_FIELD_PREP
here.  Otherwise,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  
>  /* GEN9 DC */
>  #define DC_STATE_EN			_MMIO(0x45504)
> -- 
> 2.31.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 04/30] drm/i915/display: remove explicit CNL handling from intel_cdclk.c

[Lucas De Marchi]

On Sat, Jul 24, 2021 at 11:12:07AM -0700, Matt Roper wrote:
>On Fri, Jul 23, 2021 at 05:10:48PM -0700, Lucas De Marchi wrote:
>> The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
>> any checks and supporting code for CNL. Remove code and rename
>> functions/macros accordingly.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +++++-----------------
>>  drivers/gpu/drm/i915/i915_reg.h            |  4 +-
>>  2 files changed, 18 insertions(+), 58 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index ff35c29508d5..34fa4130d5c4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -1195,17 +1195,6 @@ static const struct intel_cdclk_vals glk_cdclk_table[] = {
>>  	{}
>>  };
>>
>> -static const struct intel_cdclk_vals cnl_cdclk_table[] = {
>> -	{ .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
>> -	{ .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
>> -	{ .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
>> -
>> -	{ .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
>> -	{ .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
>> -	{ .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
>> -	{}
>> -};
>> -
>>  static const struct intel_cdclk_vals icl_cdclk_table[] = {
>>  	{ .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
>>  	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
>> @@ -1339,16 +1328,6 @@ static u8 bxt_calc_voltage_level(int cdclk)
>>  	return DIV_ROUND_UP(cdclk, 25000);
>>  }
>>
>> -static u8 cnl_calc_voltage_level(int cdclk)
>> -{
>> -	if (cdclk > 336000)
>> -		return 2;
>> -	else if (cdclk > 168000)
>> -		return 1;
>> -	else
>> -		return 0;
>> -}
>> -
>>  static u8 icl_calc_voltage_level(int cdclk)
>>  {
>>  	if (cdclk > 556800)
>> @@ -1383,15 +1362,6 @@ static u8 tgl_calc_voltage_level(int cdclk)
>>  		return 0;
>>  }
>>
>> -static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
>> -			       struct intel_cdclk_config *cdclk_config)
>> -{
>> -	if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
>> -		cdclk_config->ref = 24000;
>> -	else
>> -		cdclk_config->ref = 19200;
>> -}
>> -
>>  static void icl_readout_refclk(struct drm_i915_private *dev_priv,
>>  			       struct intel_cdclk_config *cdclk_config)
>>  {
>> @@ -1422,8 +1392,6 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
>>  		cdclk_config->ref = 38400;
>>  	else if (DISPLAY_VER(dev_priv) >= 11)
>>  		icl_readout_refclk(dev_priv, cdclk_config);
>> -	else if (IS_CANNONLAKE(dev_priv))
>> -		cnl_readout_refclk(dev_priv, cdclk_config);
>>  	else
>>  		cdclk_config->ref = 19200;
>>
>> @@ -1439,11 +1407,11 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
>>  	}
>>
>>  	/*
>> -	 * CNL+ have the ratio directly in the PLL enable register, gen9lp had
>> -	 * it in a separate PLL control register.
>> +	 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
>> +	 * gen9lp had it in a separate PLL control register.
>>  	 */
>> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
>> -		ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
>> +	if (DISPLAY_VER(dev_priv) >= 11)
>> +		ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
>>  	else
>>  		ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
>>
>> @@ -1530,7 +1498,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
>>  	dev_priv->cdclk.hw.vco = vco;
>>  }
>>
>> -static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
>> +static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
>>  {
>>  	intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
>>  		     BXT_DE_PLL_PLL_ENABLE, 0);
>> @@ -1542,12 +1510,12 @@ static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
>>  	dev_priv->cdclk.hw.vco = 0;
>>  }
>>
>> -static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
>> +static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
>>  {
>>  	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
>>  	u32 val;
>>
>> -	val = CNL_CDCLK_PLL_RATIO(ratio);
>> +	val = ICL_CDCLK_PLL_RATIO(ratio);
>>  	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
>>
>>  	val |= BXT_DE_PLL_PLL_ENABLE;
>> @@ -1566,7 +1534,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
>>  	u32 val;
>>
>>  	/* Write PLL ratio without disabling */
>> -	val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
>> +	val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
>>  	intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
>>
>>  	/* Submit freq change request */
>> @@ -1635,7 +1603,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>  	int ret;
>>
>>  	/* Inform power controller of upcoming frequency change. */
>> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
>> +	if (DISPLAY_VER(dev_priv) >= 11)
>>  		ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
>>  					SKL_CDCLK_PREPARE_FOR_CHANGE,
>>  					SKL_CDCLK_READY_FOR_CHANGE,
>> @@ -1659,13 +1627,13 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>  	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
>>  		if (dev_priv->cdclk.hw.vco != vco)
>>  			adlp_cdclk_pll_crawl(dev_priv, vco);
>> -	} else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
>> +	} else if (DISPLAY_VER(dev_priv) >= 11) {
>>  		if (dev_priv->cdclk.hw.vco != 0 &&
>>  		    dev_priv->cdclk.hw.vco != vco)
>> -			cnl_cdclk_pll_disable(dev_priv);
>> +			icl_cdclk_pll_disable(dev_priv);
>>
>>  		if (dev_priv->cdclk.hw.vco != vco)
>> -			cnl_cdclk_pll_enable(dev_priv, vco);
>> +			icl_cdclk_pll_enable(dev_priv, vco);
>>  	} else {
>>  		if (dev_priv->cdclk.hw.vco != 0 &&
>>  		    dev_priv->cdclk.hw.vco != vco)
>> @@ -1691,7 +1659,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>  	if (pipe != INVALID_PIPE)
>>  		intel_wait_for_vblank(dev_priv, pipe);
>>
>> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
>> +	if (DISPLAY_VER(dev_priv) >= 11) {
>>  		ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
>>  					      cdclk_config->voltage_level);
>>  	} else {
>> @@ -1716,7 +1684,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>
>>  	intel_update_cdclk(dev_priv);
>>
>> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
>> +	if (DISPLAY_VER(dev_priv) >= 11)
>>  		/*
>>  		 * Can't read out the voltage level :(
>>  		 * Let's just assume everything is as expected.
>> @@ -2125,7 +2093,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>>  	    crtc_state->port_clock >= 540000 &&
>>  	    crtc_state->lane_count == 4) {
>>  		if (DISPLAY_VER(dev_priv) == 10) {
>> -			/* Display WA #1145: glk,cnl */
>> +			/* Display WA #1145: glk */
>>  			min_cdclk = max(316800, min_cdclk);
>>  		} else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
>>  			/* Display WA #1144: skl,bxt */
>> @@ -2246,7 +2214,7 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
>>
>>  /*
>>   * Account for port clock min voltage level requirements.
>> - * This only really does something on CNL+ but can be
>> + * This only really does something on DISPLA_VER >= 11 but can be
>>   * called on earlier platforms as well.
>>   *
>>   * Note that this functions assumes that 0 is
>> @@ -2660,8 +2628,6 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>>  			dev_priv->max_cdclk_freq = 648000;
>>  		else
>>  			dev_priv->max_cdclk_freq = 652800;
>> -	} else if (IS_CANNONLAKE(dev_priv)) {
>> -		dev_priv->max_cdclk_freq = 528000;
>>  	} else if (IS_GEMINILAKE(dev_priv)) {
>>  		dev_priv->max_cdclk_freq = 316800;
>>  	} else if (IS_BROXTON(dev_priv)) {
>> @@ -2925,12 +2891,6 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>>  		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
>>  		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
>>  		dev_priv->cdclk.table = icl_cdclk_table;
>> -	} else if (IS_CANNONLAKE(dev_priv)) {
>> -		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
>> -		dev_priv->display.set_cdclk = bxt_set_cdclk;
>> -		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
>> -		dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
>> -		dev_priv->cdclk.table = cnl_cdclk_table;
>>  	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
>>  		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
>>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 8e1392028184..6a894ffd91e1 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -11016,8 +11016,8 @@ enum skl_power_gate {
>>  #define   BXT_DE_PLL_LOCK		(1 << 30)
>>  #define   BXT_DE_PLL_FREQ_REQ		(1 << 23)
>>  #define   BXT_DE_PLL_FREQ_REQ_ACK	(1 << 22)
>> -#define   CNL_CDCLK_PLL_RATIO(x)	(x)
>> -#define   CNL_CDCLK_PLL_RATIO_MASK	0xff
>> +#define   ICL_CDCLK_PLL_RATIO(x)	(x)
>> +#define   ICL_CDCLK_PLL_RATIO_MASK	0xff
>
>We could take this opportunity to switch to REG_GENMASK, REG_FIELD_PREP
>here.  Otherwise,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

I'd rather have a single big patch converting all of i915_reg.h

We are doing this conversion piece by piece for a long time and it seems
we are never going to achieve the desired end result.

todo++

thanks
Lucas De Marchi

>
>>
>>  /* GEN9 DC */
>>  #define DC_STATE_EN			_MMIO(0x45504)
>> --
>> 2.31.1
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 05/30] drm/i915/display: remove explicit CNL handling from intel_color.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
any checks and supporting code for CNL. For DISPLAY_VER >= 11,
ilk_load_csc_matrix() is not used, so make it handle GLK only.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index dab892d2251b..afcb4bf3826c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -305,13 +305,12 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 				    ilk_csc_postoff_limited_range);
 	} else if (crtc_state->csc_enable) {
 		/*
-		 * On GLK+ both pipe CSC and degamma LUT are controlled
+		 * On GLK both pipe CSC and degamma LUT are controlled
 		 * by csc_enable. Hence for the cases where the degama
 		 * LUT is needed but CSC is not we need to load an
 		 * identity matrix.
 		 */
-		drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&
-			    !IS_GEMINILAKE(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv));
 
 		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 				    ilk_csc_coeff_identity,
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 05/30] drm/i915/display: remove explicit CNL handling from intel_color.c

[Matt Roper]

On Fri, Jul 23, 2021 at 05:10:49PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
> any checks and supporting code for CNL. For DISPLAY_VER >= 11,
> ilk_load_csc_matrix() is not used, so make it handle GLK only.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index dab892d2251b..afcb4bf3826c 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -305,13 +305,12 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>  				    ilk_csc_postoff_limited_range);
>  	} else if (crtc_state->csc_enable) {
>  		/*
> -		 * On GLK+ both pipe CSC and degamma LUT are controlled
> +		 * On GLK both pipe CSC and degamma LUT are controlled
>  		 * by csc_enable. Hence for the cases where the degama
>  		 * LUT is needed but CSC is not we need to load an
>  		 * identity matrix.
>  		 */
> -		drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&
> -			    !IS_GEMINILAKE(dev_priv));
> +		drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv));
>  
>  		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
>  				    ilk_csc_coeff_identity,
> -- 
> 2.31.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 06/30] drm/i915/display: remove explicit CNL handling from intel_combo_phy.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK, that doesn't have
combo phys. We don't need to handle CNL explicitly in
intel_combo_phy.c.

Remove code and rename functions/macros accordingly to use ICL prefix.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../gpu/drm/i915/display/intel_combo_phy.c    | 106 ++++--------------
 1 file changed, 20 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 487c54cd5982..bacdf8a16bcb 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -23,9 +23,9 @@ enum {
 	PROCMON_1_05V_DOT_1,
 };
 
-static const struct cnl_procmon {
+static const struct icl_procmon {
 	u32 dw1, dw9, dw10;
-} cnl_procmon_values[] = {
+} icl_procmon_values[] = {
 	[PROCMON_0_85V_DOT_0] =
 		{ .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
 	[PROCMON_0_95V_DOT_0] =
@@ -38,15 +38,10 @@ static const struct cnl_procmon {
 		{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
 };
 
-/*
- * CNL has just one set of registers, while gen11 has a set for each combo PHY.
- * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
- * call the ICL macros even though the function has CNL on its name.
- */
-static const struct cnl_procmon *
-cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
+static const struct icl_procmon *
+icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	const struct cnl_procmon *procmon;
+	const struct icl_procmon *procmon;
 	u32 val;
 
 	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
@@ -55,32 +50,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
 		MISSING_CASE(val);
 		fallthrough;
 	case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
-		procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
+		procmon = &icl_procmon_values[PROCMON_0_85V_DOT_0];
 		break;
 	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
-		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
+		procmon = &icl_procmon_values[PROCMON_0_95V_DOT_0];
 		break;
 	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
-		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
+		procmon = &icl_procmon_values[PROCMON_0_95V_DOT_1];
 		break;
 	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
-		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
+		procmon = &icl_procmon_values[PROCMON_1_05V_DOT_0];
 		break;
 	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
-		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
+		procmon = &icl_procmon_values[PROCMON_1_05V_DOT_1];
 		break;
 	}
 
 	return procmon;
 }
 
-static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
+static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
 				       enum phy phy)
 {
-	const struct cnl_procmon *procmon;
+	const struct icl_procmon *procmon;
 	u32 val;
 
-	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
+	procmon = icl_get_procmon_ref_values(dev_priv, phy);
 
 	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));
 	val &= ~((0xff << 16) | 0xff);
@@ -109,13 +104,13 @@ static bool check_phy_reg(struct drm_i915_private *dev_priv,
 	return true;
 }
 
-static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
+static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
 					  enum phy phy)
 {
-	const struct cnl_procmon *procmon;
+	const struct icl_procmon *procmon;
 	bool ret;
 
-	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
+	procmon = icl_get_procmon_ref_values(dev_priv, phy);
 
 	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
 			    (0xff << 16) | 0xff, procmon->dw1);
@@ -127,61 +122,6 @@ static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
 	return ret;
 }
 
-static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
-{
-	return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
-		(intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT);
-}
-
-static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
-{
-	enum phy phy = PHY_A;
-	bool ret;
-
-	if (!cnl_combo_phy_enabled(dev_priv))
-		return false;
-
-	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
-
-	ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
-			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
-
-	return ret;
-}
-
-static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
-{
-	u32 val;
-
-	val = intel_de_read(dev_priv, CHICKEN_MISC_2);
-	val &= ~CNL_COMP_PWR_DOWN;
-	intel_de_write(dev_priv, CHICKEN_MISC_2, val);
-
-	/* Dummy PORT_A to get the correct CNL register from the ICL macro */
-	cnl_set_procmon_ref_values(dev_priv, PHY_A);
-
-	val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0);
-	val |= COMP_INIT;
-	intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val);
-
-	val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
-	val |= CL_POWER_DOWN_ENABLE;
-	intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
-}
-
-static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
-{
-	u32 val;
-
-	if (!cnl_combo_phy_verify_state(dev_priv))
-		drm_warn(&dev_priv->drm,
-			 "Combo PHY HW state changed unexpectedly.\n");
-
-	val = intel_de_read(dev_priv, CHICKEN_MISC_2);
-	val |= CNL_COMP_PWR_DOWN;
-	intel_de_write(dev_priv, CHICKEN_MISC_2, val);
-}
-
 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
 {
 	/*
@@ -291,7 +231,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 				     DCC_MODE_SELECT_CONTINUOSLY);
 	}
 
-	ret &= cnl_verify_procmon_ref_values(dev_priv, phy);
+	ret &= icl_verify_procmon_ref_values(dev_priv, phy);
 
 	if (phy_is_master(dev_priv, phy)) {
 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
@@ -415,7 +355,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
 		}
 
-		cnl_set_procmon_ref_values(dev_priv, phy);
+		icl_set_procmon_ref_values(dev_priv, phy);
 
 		if (phy_is_master(dev_priv, phy)) {
 			val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
@@ -474,16 +414,10 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 
 void intel_combo_phy_init(struct drm_i915_private *i915)
 {
-	if (DISPLAY_VER(i915) >= 11)
-		icl_combo_phys_init(i915);
-	else if (IS_CANNONLAKE(i915))
-		cnl_combo_phys_init(i915);
+	icl_combo_phys_init(i915);
 }
 
 void intel_combo_phy_uninit(struct drm_i915_private *i915)
 {
-	if (DISPLAY_VER(i915) >= 11)
-		icl_combo_phys_uninit(i915);
-	else if (IS_CANNONLAKE(i915))
-		cnl_combo_phys_uninit(i915);
+	icl_combo_phys_uninit(i915);
 }
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 06/30] drm/i915/display: remove explicit CNL handling from intel_combo_phy.c

[Matt Roper]

On Fri, Jul 23, 2021 at 05:10:50PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK, that doesn't have
> combo phys. We don't need to handle CNL explicitly in
> intel_combo_phy.c.
> 
> Remove code and rename functions/macros accordingly to use ICL prefix.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_combo_phy.c    | 106 ++++--------------
>  1 file changed, 20 insertions(+), 86 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 487c54cd5982..bacdf8a16bcb 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -23,9 +23,9 @@ enum {
>  	PROCMON_1_05V_DOT_1,
>  };
>  
> -static const struct cnl_procmon {
> +static const struct icl_procmon {
>  	u32 dw1, dw9, dw10;
> -} cnl_procmon_values[] = {
> +} icl_procmon_values[] = {
>  	[PROCMON_0_85V_DOT_0] =
>  		{ .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
>  	[PROCMON_0_95V_DOT_0] =
> @@ -38,15 +38,10 @@ static const struct cnl_procmon {
>  		{ .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
>  };
>  
> -/*
> - * CNL has just one set of registers, while gen11 has a set for each combo PHY.
> - * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
> - * call the ICL macros even though the function has CNL on its name.
> - */
> -static const struct cnl_procmon *
> -cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
> +static const struct icl_procmon *
> +icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
>  {
> -	const struct cnl_procmon *procmon;
> +	const struct icl_procmon *procmon;
>  	u32 val;
>  
>  	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
> @@ -55,32 +50,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
>  		MISSING_CASE(val);
>  		fallthrough;
>  	case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
> -		procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
> +		procmon = &icl_procmon_values[PROCMON_0_85V_DOT_0];
>  		break;
>  	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
> -		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
> +		procmon = &icl_procmon_values[PROCMON_0_95V_DOT_0];
>  		break;
>  	case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
> -		procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
> +		procmon = &icl_procmon_values[PROCMON_0_95V_DOT_1];
>  		break;
>  	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
> -		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
> +		procmon = &icl_procmon_values[PROCMON_1_05V_DOT_0];
>  		break;
>  	case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
> -		procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
> +		procmon = &icl_procmon_values[PROCMON_1_05V_DOT_1];
>  		break;
>  	}
>  
>  	return procmon;
>  }
>  
> -static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
> +static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
>  				       enum phy phy)
>  {
> -	const struct cnl_procmon *procmon;
> +	const struct icl_procmon *procmon;
>  	u32 val;
>  
> -	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
> +	procmon = icl_get_procmon_ref_values(dev_priv, phy);
>  
>  	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));
>  	val &= ~((0xff << 16) | 0xff);
> @@ -109,13 +104,13 @@ static bool check_phy_reg(struct drm_i915_private *dev_priv,
>  	return true;
>  }
>  
> -static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
> +static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
>  					  enum phy phy)
>  {
> -	const struct cnl_procmon *procmon;
> +	const struct icl_procmon *procmon;
>  	bool ret;
>  
> -	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
> +	procmon = icl_get_procmon_ref_values(dev_priv, phy);
>  
>  	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
>  			    (0xff << 16) | 0xff, procmon->dw1);
> @@ -127,61 +122,6 @@ static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
>  	return ret;
>  }
>  
> -static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
> -{
> -	return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
> -		(intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT);
> -}
> -
> -static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
> -{
> -	enum phy phy = PHY_A;
> -	bool ret;
> -
> -	if (!cnl_combo_phy_enabled(dev_priv))
> -		return false;
> -
> -	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
> -
> -	ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
> -			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
> -
> -	return ret;
> -}
> -
> -static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
> -{
> -	u32 val;
> -
> -	val = intel_de_read(dev_priv, CHICKEN_MISC_2);
> -	val &= ~CNL_COMP_PWR_DOWN;
> -	intel_de_write(dev_priv, CHICKEN_MISC_2, val);
> -
> -	/* Dummy PORT_A to get the correct CNL register from the ICL macro */
> -	cnl_set_procmon_ref_values(dev_priv, PHY_A);
> -
> -	val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0);
> -	val |= COMP_INIT;
> -	intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val);
> -
> -	val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
> -	val |= CL_POWER_DOWN_ENABLE;
> -	intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
> -}
> -
> -static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
> -{
> -	u32 val;
> -
> -	if (!cnl_combo_phy_verify_state(dev_priv))
> -		drm_warn(&dev_priv->drm,
> -			 "Combo PHY HW state changed unexpectedly.\n");
> -
> -	val = intel_de_read(dev_priv, CHICKEN_MISC_2);
> -	val |= CNL_COMP_PWR_DOWN;
> -	intel_de_write(dev_priv, CHICKEN_MISC_2, val);
> -}
> -
>  static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
>  {
>  	/*
> @@ -291,7 +231,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
>  				     DCC_MODE_SELECT_CONTINUOSLY);
>  	}
>  
> -	ret &= cnl_verify_procmon_ref_values(dev_priv, phy);
> +	ret &= icl_verify_procmon_ref_values(dev_priv, phy);
>  
>  	if (phy_is_master(dev_priv, phy)) {
>  		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
> @@ -415,7 +355,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
>  			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
>  		}
>  
> -		cnl_set_procmon_ref_values(dev_priv, phy);
> +		icl_set_procmon_ref_values(dev_priv, phy);
>  
>  		if (phy_is_master(dev_priv, phy)) {
>  			val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
> @@ -474,16 +414,10 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
>  
>  void intel_combo_phy_init(struct drm_i915_private *i915)
>  {
> -	if (DISPLAY_VER(i915) >= 11)
> -		icl_combo_phys_init(i915);
> -	else if (IS_CANNONLAKE(i915))
> -		cnl_combo_phys_init(i915);
> +	icl_combo_phys_init(i915);
>  }
>  
>  void intel_combo_phy_uninit(struct drm_i915_private *i915)
>  {
> -	if (DISPLAY_VER(i915) >= 11)
> -		icl_combo_phys_uninit(i915);
> -	else if (IS_CANNONLAKE(i915))
> -		cnl_combo_phys_uninit(i915);
> +	icl_combo_phys_uninit(i915);
>  }
> -- 
> 2.31.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 07/30] drm/i915/display: remove explicit CNL handling from intel_crtc.c

[Lucas De Marchi]

No need for special CNL handling as there is no real platform with that
configuration.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 448c4d99ac35..254e67141a77 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -335,7 +335,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 		dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
 	}
 
-	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 11)
 		drm_crtc_create_scaling_filter_property(&crtc->base,
 						BIT(DRM_SCALING_FILTER_DEFAULT) |
 						BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 07/30] drm/i915/display: remove explicit CNL handling from intel_crtc.c

[Matt Roper]

On Fri, Jul 23, 2021 at 05:10:51PM -0700, Lucas De Marchi wrote:
> No need for special CNL handling as there is no real platform with that
> configuration.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 448c4d99ac35..254e67141a77 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -335,7 +335,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
>  	}
>  
> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> +	if (DISPLAY_VER(dev_priv) >= 11)
>  		drm_crtc_create_scaling_filter_property(&crtc->base,
>  						BIT(DRM_SCALING_FILTER_DEFAULT) |
>  						BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
> -- 
> 2.31.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 08/30] drm/i915/display: remove explicit CNL handling from intel_ddi.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_ddi.c.

Remove code and rename functions/macros accordingly to use ICL prefix.
There's one leftover reference to cnl that comes from the struct
intel_ddi_buf_trans. This will be renamed later when we get rid of the
additional CNL tables.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 254 ++---------------------
 1 file changed, 20 insertions(+), 234 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 26a3aa73fcc4..8367462842fa 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -822,7 +822,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 static enum intel_display_power_domain
 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 {
-	/* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
+	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 	 * DC states enabled at the same time, while for driver initiated AUX
 	 * transfers we need the same AUX IOs to be powered but with DC states
 	 * disabled. Accordingly use the AUX power domain here which leaves DC
@@ -1017,126 +1017,6 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
 	return DP_TRAIN_PRE_EMPH_LEVEL_3;
 }
 
-static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
-				   const struct intel_crtc_state *crtc_state,
-				   int level)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	const struct intel_ddi_buf_trans *ddi_translations;
-	enum port port = encoder->port;
-	int n_entries, ln;
-	u32 val;
-
-	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
-	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
-		return;
-	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
-		level = n_entries - 1;
-
-	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
-	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
-	val &= ~SCALING_MODE_SEL_MASK;
-	val |= SCALING_MODE_SEL(2);
-	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
-
-	/* Program PORT_TX_DW2 */
-	val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
-	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
-		 RCOMP_SCALAR_MASK);
-	val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
-	val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
-	/* Rcomp scalar is fixed as 0x98 for every table entry */
-	val |= RCOMP_SCALAR(0x98);
-	intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
-
-	/* Program PORT_TX_DW4 */
-	/* We cannot write to GRP. It would overrite individual loadgen */
-	for (ln = 0; ln < 4; ln++) {
-		val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
-		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
-			 CURSOR_COEFF_MASK);
-		val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
-		val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
-		val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
-		intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
-	}
-
-	/* Program PORT_TX_DW5 */
-	/* All DW5 values are fixed for every table entry */
-	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
-	val &= ~RTERM_SELECT_MASK;
-	val |= RTERM_SELECT(6);
-	val |= TAP3_DISABLE;
-	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
-
-	/* Program PORT_TX_DW7 */
-	val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
-	val &= ~N_SCALAR_MASK;
-	val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
-	intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
-}
-
-static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    const struct intel_crtc_state *crtc_state,
-				    int level)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum port port = encoder->port;
-	int width, rate, ln;
-	u32 val;
-
-	width = crtc_state->lane_count;
-	rate = crtc_state->port_clock;
-
-	/*
-	 * 1. If port type is eDP or DP,
-	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
-	 * else clear to 0b.
-	 */
-	val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-		val &= ~COMMON_KEEPER_EN;
-	else
-		val |= COMMON_KEEPER_EN;
-	intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
-
-	/* 2. Program loadgen select */
-	/*
-	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
-	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
-	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
-	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
-	 */
-	for (ln = 0; ln <= 3; ln++) {
-		val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
-		val &= ~LOADGEN_SELECT;
-
-		if ((rate <= 600000 && width == 4 && ln >= 1)  ||
-		    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
-			val |= LOADGEN_SELECT;
-		}
-		intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
-	}
-
-	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
-	val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
-	val |= SUS_CLOCK_CONFIG;
-	intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
-
-	/* 4. Clear training enable to change swing values */
-	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
-	val &= ~TX_TRAINING_EN;
-	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
-
-	/* 5. Program swing and de-emphasis */
-	cnl_ddi_vswing_program(encoder, crtc_state, level);
-
-	/* 6. Set training enable to trigger update */
-	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
-	val |= TX_TRAINING_EN;
-	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
-}
-
 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 					 const struct intel_crtc_state *crtc_state,
 					 int level)
@@ -1515,16 +1395,6 @@ icl_set_signal_levels(struct intel_dp *intel_dp,
 	icl_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
-static void
-cnl_set_signal_levels(struct intel_dp *intel_dp,
-		      const struct intel_crtc_state *crtc_state)
-{
-	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
-	int level = intel_ddi_dp_level(intel_dp);
-
-	cnl_ddi_vswing_sequence(encoder, crtc_state, level);
-}
-
 static void
 bxt_set_signal_levels(struct intel_dp *intel_dp,
 		      const struct intel_crtc_state *crtc_state)
@@ -1560,7 +1430,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
 }
 
-static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
+static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
 				  u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
 {
 	mutex_lock(&i915->dpll.lock);
@@ -1576,7 +1446,7 @@ static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
 	mutex_unlock(&i915->dpll.lock);
 }
 
-static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
+static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
 				   u32 clk_off)
 {
 	mutex_lock(&i915->dpll.lock);
@@ -1586,14 +1456,14 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg
 	mutex_unlock(&i915->dpll.lock);
 }
 
-static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
+static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
 				      u32 clk_off)
 {
 	return !(intel_de_read(i915, reg) & clk_off);
 }
 
 static struct intel_shared_dpll *
-_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
+_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
 		 u32 clk_sel_mask, u32 clk_sel_shift)
 {
 	enum intel_dpll_id id;
@@ -1613,7 +1483,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder,
 	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
-	_cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
+	_icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
 			      ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
 			      pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
 			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
@@ -1624,7 +1494,7 @@ static void adls_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	_cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
+	_icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
 			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
@@ -1633,7 +1503,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
+	return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
 					 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
@@ -1642,7 +1512,7 @@ static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
+	return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
 				ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
 				ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
 }
@@ -1657,7 +1527,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
 	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
-	_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
+	_icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
 			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
 			      RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
@@ -1668,7 +1538,7 @@ static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
+	_icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
 			       RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
@@ -1677,7 +1547,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
+	return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
 					 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
@@ -1686,7 +1556,7 @@ static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+	return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
 				RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 				RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
 }
@@ -1710,7 +1580,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 			(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
 		return;
 
-	_cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
+	_icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
 			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
 			      DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
@@ -1721,7 +1591,7 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	_cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
+	_icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
 			       DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
@@ -1730,7 +1600,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	return _cnl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
+	return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
 					 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
@@ -1767,7 +1637,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
-	_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
+	_icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
 			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
 			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
@@ -1778,7 +1648,7 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
+	_icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
 			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
@@ -1787,7 +1657,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
+	return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
 					 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 }
 
@@ -1796,7 +1666,7 @@ struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
-	return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+	return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
 				ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 				ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
 }
@@ -1929,50 +1799,6 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
 	return intel_get_shared_dpll_by_id(i915, id);
 }
 
-static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
-				 const struct intel_crtc_state *crtc_state)
-{
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
-	enum port port = encoder->port;
-
-	if (drm_WARN_ON(&i915->drm, !pll))
-		return;
-
-	_cnl_ddi_enable_clock(i915, DPCLKA_CFGCR0,
-			      DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
-			      DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port),
-			      DPCLKA_CFGCR0_DDI_CLK_OFF(port));
-}
-
-static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
-{
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-	enum port port = encoder->port;
-
-	_cnl_ddi_disable_clock(i915, DPCLKA_CFGCR0,
-			       DPCLKA_CFGCR0_DDI_CLK_OFF(port));
-}
-
-static bool cnl_ddi_is_clock_enabled(struct intel_encoder *encoder)
-{
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-	enum port port = encoder->port;
-
-	return _cnl_ddi_is_clock_enabled(i915, DPCLKA_CFGCR0,
-					 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
-}
-
-static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder)
-{
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-	enum port port = encoder->port;
-
-	return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0,
-				DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
-				DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port));
-}
-
 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
@@ -2657,8 +2483,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 
 	if (DISPLAY_VER(dev_priv) >= 11)
 		icl_ddi_vswing_sequence(encoder, crtc_state, level);
-	else if (IS_CANNONLAKE(dev_priv))
-		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
@@ -3105,8 +2929,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 		tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (DISPLAY_VER(dev_priv) == 11)
 		icl_ddi_vswing_sequence(encoder, crtc_state, level);
-	else if (IS_CANNONLAKE(dev_priv))
-		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
@@ -3470,8 +3292,6 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 		crtc_state->min_voltage_level = 3;
 	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 1;
-	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
-		crtc_state->min_voltage_level = 2;
 }
 
 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
@@ -3812,13 +3632,6 @@ static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
 	intel_ddi_get_config(encoder, crtc_state);
 }
 
-static void cnl_ddi_get_config(struct intel_encoder *encoder,
-			       struct intel_crtc_state *crtc_state)
-{
-	intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder));
-	intel_ddi_get_config(encoder, crtc_state);
-}
-
 static void bxt_ddi_get_config(struct intel_encoder *encoder,
 			       struct intel_crtc_state *crtc_state)
 {
@@ -4069,8 +3882,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
 		dig_port->dp.set_signal_levels = tgl_set_signal_levels;
 	else if (DISPLAY_VER(dev_priv) >= 11)
 		dig_port->dp.set_signal_levels = icl_set_signal_levels;
-	else if (IS_CANNONLAKE(dev_priv))
-		dig_port->dp.set_signal_levels = cnl_set_signal_levels;
 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 		dig_port->dp.set_signal_levels = bxt_set_signal_levels;
 	else
@@ -4317,15 +4128,6 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 		return true;
 
-	/* Cannonlake: Most of SKUs don't support DDI_E, and the only
-	 *             one who does also have a full A/E split called
-	 *             DDI_F what makes DDI_E useless. However for this
-	 *             case let's trust VBT info.
-	 */
-	if (IS_CANNONLAKE(dev_priv) &&
-	    !intel_bios_is_port_present(dev_priv, PORT_E))
-		return true;
-
 	return false;
 }
 
@@ -4430,15 +4232,6 @@ static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
 	return HPD_PORT_A + port - PORT_A;
 }
 
-static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,
-				enum port port)
-{
-	if (port == PORT_F)
-		return HPD_PORT_E;
-
-	return HPD_PORT_A + port - PORT_A;
-}
-
 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
 {
 	if (HAS_PCH_TGP(dev_priv))
@@ -4645,11 +4438,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 			encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
 			encoder->get_config = icl_ddi_combo_get_config;
 		}
-	} else if (IS_CANNONLAKE(dev_priv)) {
-		encoder->enable_clock = cnl_ddi_enable_clock;
-		encoder->disable_clock = cnl_ddi_disable_clock;
-		encoder->is_clock_enabled = cnl_ddi_is_clock_enabled;
-		encoder->get_config = cnl_ddi_get_config;
 	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 		/* BXT/GLK have fixed PLL->port mapping */
 		encoder->get_config = bxt_ddi_get_config;
@@ -4679,8 +4467,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) == 11)
 		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
-	else if (IS_CANNONLAKE(dev_priv))
-		encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
 	else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
 		encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
 	else
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 08/30] drm/i915/display: remove explicit CNL handling from intel_ddi.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:10:52PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in intel_ddi.c.
> 
> Remove code and rename functions/macros accordingly to use ICL prefix.
> There's one leftover reference to cnl that comes from the struct
> intel_ddi_buf_trans. This will be renamed later when we get rid of the
> additional CNL tables.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 254 ++---------------------
>  1 file changed, 20 insertions(+), 234 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 26a3aa73fcc4..8367462842fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -822,7 +822,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>  static enum intel_display_power_domain
>  intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
>  {
> -	/* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
> +	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
>  	 * DC states enabled at the same time, while for driver initiated AUX
>  	 * transfers we need the same AUX IOs to be powered but with DC states
>  	 * disabled. Accordingly use the AUX power domain here which leaves DC
> @@ -1017,126 +1017,6 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
>  	return DP_TRAIN_PRE_EMPH_LEVEL_3;
>  }
>  
> -static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
> -				   const struct intel_crtc_state *crtc_state,
> -				   int level)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	const struct intel_ddi_buf_trans *ddi_translations;
> -	enum port port = encoder->port;
> -	int n_entries, ln;
> -	u32 val;
> -
> -	ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
> -	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> -		return;
> -	if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
> -		level = n_entries - 1;
> -
> -	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
> -	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
> -	val &= ~SCALING_MODE_SEL_MASK;
> -	val |= SCALING_MODE_SEL(2);
> -	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
> -
> -	/* Program PORT_TX_DW2 */
> -	val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
> -	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> -		 RCOMP_SCALAR_MASK);
> -	val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
> -	val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
> -	/* Rcomp scalar is fixed as 0x98 for every table entry */
> -	val |= RCOMP_SCALAR(0x98);
> -	intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
> -
> -	/* Program PORT_TX_DW4 */
> -	/* We cannot write to GRP. It would overrite individual loadgen */
> -	for (ln = 0; ln < 4; ln++) {
> -		val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
> -		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> -			 CURSOR_COEFF_MASK);
> -		val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
> -		val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
> -		val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
> -		intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
> -	}
> -
> -	/* Program PORT_TX_DW5 */
> -	/* All DW5 values are fixed for every table entry */
> -	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
> -	val &= ~RTERM_SELECT_MASK;
> -	val |= RTERM_SELECT(6);
> -	val |= TAP3_DISABLE;
> -	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
> -
> -	/* Program PORT_TX_DW7 */
> -	val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
> -	val &= ~N_SCALAR_MASK;
> -	val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
> -	intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
> -}
> -
> -static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> -				    const struct intel_crtc_state *crtc_state,
> -				    int level)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum port port = encoder->port;
> -	int width, rate, ln;
> -	u32 val;
> -
> -	width = crtc_state->lane_count;
> -	rate = crtc_state->port_clock;
> -
> -	/*
> -	 * 1. If port type is eDP or DP,
> -	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
> -	 * else clear to 0b.
> -	 */
> -	val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> -		val &= ~COMMON_KEEPER_EN;
> -	else
> -		val |= COMMON_KEEPER_EN;
> -	intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
> -
> -	/* 2. Program loadgen select */
> -	/*
> -	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
> -	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
> -	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
> -	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
> -	 */
> -	for (ln = 0; ln <= 3; ln++) {
> -		val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
> -		val &= ~LOADGEN_SELECT;
> -
> -		if ((rate <= 600000 && width == 4 && ln >= 1)  ||
> -		    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
> -			val |= LOADGEN_SELECT;
> -		}
> -		intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
> -	}
> -
> -	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
> -	val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
> -	val |= SUS_CLOCK_CONFIG;
> -	intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
> -
> -	/* 4. Clear training enable to change swing values */
> -	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
> -	val &= ~TX_TRAINING_EN;
> -	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
> -
> -	/* 5. Program swing and de-emphasis */
> -	cnl_ddi_vswing_program(encoder, crtc_state, level);
> -
> -	/* 6. Set training enable to trigger update */
> -	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
> -	val |= TX_TRAINING_EN;
> -	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
> -}
> -
>  static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  					 const struct intel_crtc_state *crtc_state,
>  					 int level)
> @@ -1515,16 +1395,6 @@ icl_set_signal_levels(struct intel_dp *intel_dp,
>  	icl_ddi_vswing_sequence(encoder, crtc_state, level);
>  }
>  
> -static void
> -cnl_set_signal_levels(struct intel_dp *intel_dp,
> -		      const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> -	int level = intel_ddi_dp_level(intel_dp);
> -
> -	cnl_ddi_vswing_sequence(encoder, crtc_state, level);
> -}
> -
>  static void
>  bxt_set_signal_levels(struct intel_dp *intel_dp,
>  		      const struct intel_crtc_state *crtc_state)
> @@ -1560,7 +1430,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
>  	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>  }
>  
> -static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
> +static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
>  				  u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
>  {
>  	mutex_lock(&i915->dpll.lock);
> @@ -1576,7 +1446,7 @@ static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
>  	mutex_unlock(&i915->dpll.lock);
>  }
>  
> -static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
> +static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
>  				   u32 clk_off)
>  {
>  	mutex_lock(&i915->dpll.lock);
> @@ -1586,14 +1456,14 @@ static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg
>  	mutex_unlock(&i915->dpll.lock);
>  }
>  
> -static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
> +static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
>  				      u32 clk_off)
>  {
>  	return !(intel_de_read(i915, reg) & clk_off);
>  }
>  
>  static struct intel_shared_dpll *
> -_cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
> +_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
>  		 u32 clk_sel_mask, u32 clk_sel_shift)
>  {
>  	enum intel_dpll_id id;
> @@ -1613,7 +1483,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder,
>  	if (drm_WARN_ON(&i915->drm, !pll))
>  		return;
>  
> -	_cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
> +	_icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
>  			      ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
>  			      pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
>  			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> @@ -1624,7 +1494,7 @@ static void adls_ddi_disable_clock(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	_cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
> +	_icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
>  			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>  }
>  
> @@ -1633,7 +1503,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
> +	return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
>  					 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>  }
>  
> @@ -1642,7 +1512,7 @@ static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
> +	return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
>  				ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
>  				ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
>  }
> @@ -1657,7 +1527,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
>  	if (drm_WARN_ON(&i915->drm, !pll))
>  		return;
>  
> -	_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
> +	_icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
>  			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
>  			      RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
>  			      RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> @@ -1668,7 +1538,7 @@ static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
> +	_icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
>  			       RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>  }
>  
> @@ -1677,7 +1547,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
> +	return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
>  					 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>  }
>  
> @@ -1686,7 +1556,7 @@ static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
> +	return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
>  				RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
>  				RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
>  }
> @@ -1710,7 +1580,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
>  			(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
>  		return;
>  
> -	_cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
> +	_icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
>  			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
>  			      DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
>  			      DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> @@ -1721,7 +1591,7 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	_cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
> +	_icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
>  			       DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>  }
>  
> @@ -1730,7 +1600,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	return _cnl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
> +	return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
>  					 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>  }
>  
> @@ -1767,7 +1637,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
>  	if (drm_WARN_ON(&i915->drm, !pll))
>  		return;
>  
> -	_cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
> +	_icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
>  			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
>  			      ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
>  			      ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> @@ -1778,7 +1648,7 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	_cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
> +	_icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
>  			       ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>  }
>  
> @@ -1787,7 +1657,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
> +	return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
>  					 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>  }
>  
> @@ -1796,7 +1666,7 @@ struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
> -	return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
> +	return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
>  				ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
>  				ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
>  }
> @@ -1929,50 +1799,6 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
>  	return intel_get_shared_dpll_by_id(i915, id);
>  }
>  
> -static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
> -				 const struct intel_crtc_state *crtc_state)
> -{
> -	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> -	enum port port = encoder->port;
> -
> -	if (drm_WARN_ON(&i915->drm, !pll))
> -		return;
> -
> -	_cnl_ddi_enable_clock(i915, DPCLKA_CFGCR0,
> -			      DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
> -			      DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port),
> -			      DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> -}
> -
> -static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
> -{
> -	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -	enum port port = encoder->port;
> -
> -	_cnl_ddi_disable_clock(i915, DPCLKA_CFGCR0,
> -			       DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> -}
> -
> -static bool cnl_ddi_is_clock_enabled(struct intel_encoder *encoder)
> -{
> -	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -	enum port port = encoder->port;
> -
> -	return _cnl_ddi_is_clock_enabled(i915, DPCLKA_CFGCR0,
> -					 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> -}
> -
> -static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder)
> -{
> -	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -	enum port port = encoder->port;
> -
> -	return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0,
> -				DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
> -				DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port));
> -}
> -
>  static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> @@ -2657,8 +2483,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
>  
>  	if (DISPLAY_VER(dev_priv) >= 11)
>  		icl_ddi_vswing_sequence(encoder, crtc_state, level);
> -	else if (IS_CANNONLAKE(dev_priv))
> -		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>  		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else
> @@ -3105,8 +2929,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>  		tgl_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else if (DISPLAY_VER(dev_priv) == 11)
>  		icl_ddi_vswing_sequence(encoder, crtc_state, level);
> -	else if (IS_CANNONLAKE(dev_priv))
> -		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>  		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
>  	else
> @@ -3470,8 +3292,6 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
>  		crtc_state->min_voltage_level = 3;
>  	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
>  		crtc_state->min_voltage_level = 1;
> -	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
> -		crtc_state->min_voltage_level = 2;
>  }
>  
>  static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
> @@ -3812,13 +3632,6 @@ static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
>  	intel_ddi_get_config(encoder, crtc_state);
>  }
>  
> -static void cnl_ddi_get_config(struct intel_encoder *encoder,
> -			       struct intel_crtc_state *crtc_state)
> -{
> -	intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder));
> -	intel_ddi_get_config(encoder, crtc_state);
> -}
> -
>  static void bxt_ddi_get_config(struct intel_encoder *encoder,
>  			       struct intel_crtc_state *crtc_state)
>  {
> @@ -4069,8 +3882,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
>  		dig_port->dp.set_signal_levels = tgl_set_signal_levels;
>  	else if (DISPLAY_VER(dev_priv) >= 11)
>  		dig_port->dp.set_signal_levels = icl_set_signal_levels;
> -	else if (IS_CANNONLAKE(dev_priv))
> -		dig_port->dp.set_signal_levels = cnl_set_signal_levels;
>  	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>  		dig_port->dp.set_signal_levels = bxt_set_signal_levels;
>  	else
> @@ -4317,15 +4128,6 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
>  	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>  		return true;
>  
> -	/* Cannonlake: Most of SKUs don't support DDI_E, and the only
> -	 *             one who does also have a full A/E split called
> -	 *             DDI_F what makes DDI_E useless. However for this
> -	 *             case let's trust VBT info.
> -	 */
> -	if (IS_CANNONLAKE(dev_priv) &&
> -	    !intel_bios_is_port_present(dev_priv, PORT_E))
> -		return true;
> -
>  	return false;
>  }
>  
> @@ -4430,15 +4232,6 @@ static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
>  	return HPD_PORT_A + port - PORT_A;
>  }
>  
> -static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,
> -				enum port port)
> -{
> -	if (port == PORT_F)
> -		return HPD_PORT_E;
> -
> -	return HPD_PORT_A + port - PORT_A;
> -}
> -
>  static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
>  {
>  	if (HAS_PCH_TGP(dev_priv))
> @@ -4645,11 +4438,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  			encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
>  			encoder->get_config = icl_ddi_combo_get_config;
>  		}
> -	} else if (IS_CANNONLAKE(dev_priv)) {
> -		encoder->enable_clock = cnl_ddi_enable_clock;
> -		encoder->disable_clock = cnl_ddi_disable_clock;
> -		encoder->is_clock_enabled = cnl_ddi_is_clock_enabled;
> -		encoder->get_config = cnl_ddi_get_config;
>  	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
>  		/* BXT/GLK have fixed PLL->port mapping */
>  		encoder->get_config = bxt_ddi_get_config;
> @@ -4679,8 +4467,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
>  	else if (DISPLAY_VER(dev_priv) == 11)
>  		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
> -	else if (IS_CANNONLAKE(dev_priv))
> -		encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
>  	else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
>  		encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
>  	else
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 09/30] drm/i915/display: remove explicit CNL handling from intel_display_debugfs.c

[Lucas De Marchi]

Only one reference to CNL that is not needed, but code is the same for
DISPLAY_VER >= 11, so leave the code around and just remove the special
case for CNL.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2cf742a0b957..8fdacb252bb1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2500,7 +2500,7 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
 				    connector, &i915_hdcp_sink_capability_fops);
 	}
 
-	if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) &&
+	if (DISPLAY_VER(dev_priv) >= 11 &&
 	    ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
 	    !to_intel_connector(connector)->mst_port) ||
 	    connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 09/30] drm/i915/display: remove explicit CNL handling from intel_display_debugfs.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:10:53PM -0700, Lucas De Marchi wrote:
> Only one reference to CNL that is not needed, but code is the same for
> DISPLAY_VER >= 11, so leave the code around and just remove the special
> case for CNL.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 2cf742a0b957..8fdacb252bb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2500,7 +2500,7 @@ int intel_connector_debugfs_add(struct drm_connector *connector)
>  				    connector, &i915_hdcp_sink_capability_fops);
>  	}
>  
> -	if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) &&
> +	if (DISPLAY_VER(dev_priv) >= 11 &&
>  	    ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
>  	    !to_intel_connector(connector)->mst_port) ||
>  	    connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 10/30] drm/i915/display: remove explicit CNL handling from intel_dmc.c

[Lucas De Marchi]

Remove DMC firmware for CNL.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 9895fd957df9..3c3c6cb5c0df 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -70,11 +70,6 @@ MODULE_FIRMWARE(TGL_DMC_PATH);
 #define ICL_DMC_MAX_FW_SIZE		0x6000
 MODULE_FIRMWARE(ICL_DMC_PATH);
 
-#define CNL_DMC_PATH			DMC_PATH(cnl, 1, 07)
-#define CNL_DMC_VERSION_REQUIRED	DMC_VERSION(1, 7)
-#define CNL_DMC_MAX_FW_SIZE		GLK_DMC_MAX_FW_SIZE
-MODULE_FIRMWARE(CNL_DMC_PATH);
-
 #define GLK_DMC_PATH			DMC_PATH(glk, 1, 04)
 #define GLK_DMC_VERSION_REQUIRED	DMC_VERSION(1, 4)
 #define GLK_DMC_MAX_FW_SIZE		0x4000
@@ -718,10 +713,6 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 		dmc->fw_path = ICL_DMC_PATH;
 		dmc->required_version = ICL_DMC_VERSION_REQUIRED;
 		dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
-	} else if (IS_CANNONLAKE(dev_priv)) {
-		dmc->fw_path = CNL_DMC_PATH;
-		dmc->required_version = CNL_DMC_VERSION_REQUIRED;
-		dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
 	} else if (IS_GEMINILAKE(dev_priv)) {
 		dmc->fw_path = GLK_DMC_PATH;
 		dmc->required_version = GLK_DMC_VERSION_REQUIRED;
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 10/30] drm/i915/display: remove explicit CNL handling from intel_dmc.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:10:54PM -0700, Lucas De Marchi wrote:
> Remove DMC firmware for CNL.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>

We need to remove the binary from linux-firmware.git as well

> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 9 ---------
>  1 file changed, 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 9895fd957df9..3c3c6cb5c0df 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -70,11 +70,6 @@ MODULE_FIRMWARE(TGL_DMC_PATH);
>  #define ICL_DMC_MAX_FW_SIZE		0x6000
>  MODULE_FIRMWARE(ICL_DMC_PATH);
>  
> -#define CNL_DMC_PATH			DMC_PATH(cnl, 1, 07)
> -#define CNL_DMC_VERSION_REQUIRED	DMC_VERSION(1, 7)
> -#define CNL_DMC_MAX_FW_SIZE		GLK_DMC_MAX_FW_SIZE
> -MODULE_FIRMWARE(CNL_DMC_PATH);
> -
>  #define GLK_DMC_PATH			DMC_PATH(glk, 1, 04)
>  #define GLK_DMC_VERSION_REQUIRED	DMC_VERSION(1, 4)
>  #define GLK_DMC_MAX_FW_SIZE		0x4000
> @@ -718,10 +713,6 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
>  		dmc->fw_path = ICL_DMC_PATH;
>  		dmc->required_version = ICL_DMC_VERSION_REQUIRED;
>  		dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
> -	} else if (IS_CANNONLAKE(dev_priv)) {
> -		dmc->fw_path = CNL_DMC_PATH;
> -		dmc->required_version = CNL_DMC_VERSION_REQUIRED;
> -		dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
>  	} else if (IS_GEMINILAKE(dev_priv)) {
>  		dmc->fw_path = GLK_DMC_PATH;
>  		dmc->required_version = GLK_DMC_VERSION_REQUIRED;
> -- 
> 2.31.1
> 
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Re: [Intel-gfx] [PATCH 10/30] drm/i915/display: remove explicit CNL handling from intel_dmc.c

[Matt Roper]

On Fri, Jul 23, 2021 at 05:10:54PM -0700, Lucas De Marchi wrote:
> Remove DMC firmware for CNL.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 9 ---------
>  1 file changed, 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 9895fd957df9..3c3c6cb5c0df 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -70,11 +70,6 @@ MODULE_FIRMWARE(TGL_DMC_PATH);
>  #define ICL_DMC_MAX_FW_SIZE		0x6000
>  MODULE_FIRMWARE(ICL_DMC_PATH);
>  
> -#define CNL_DMC_PATH			DMC_PATH(cnl, 1, 07)
> -#define CNL_DMC_VERSION_REQUIRED	DMC_VERSION(1, 7)
> -#define CNL_DMC_MAX_FW_SIZE		GLK_DMC_MAX_FW_SIZE
> -MODULE_FIRMWARE(CNL_DMC_PATH);
> -
>  #define GLK_DMC_PATH			DMC_PATH(glk, 1, 04)
>  #define GLK_DMC_VERSION_REQUIRED	DMC_VERSION(1, 4)
>  #define GLK_DMC_MAX_FW_SIZE		0x4000
> @@ -718,10 +713,6 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
>  		dmc->fw_path = ICL_DMC_PATH;
>  		dmc->required_version = ICL_DMC_VERSION_REQUIRED;
>  		dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
> -	} else if (IS_CANNONLAKE(dev_priv)) {
> -		dmc->fw_path = CNL_DMC_PATH;
> -		dmc->required_version = CNL_DMC_VERSION_REQUIRED;
> -		dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
>  	} else if (IS_GEMINILAKE(dev_priv)) {
>  		dmc->fw_path = GLK_DMC_PATH;
>  		dmc->required_version = GLK_DMC_VERSION_REQUIRED;
> -- 
> 2.31.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH 11/30] drm/i915/display: remove explicit CNL handling from intel_dp.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_dp.c.

Remove code and rename functions/macros accordingly to use ICL prefix.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 35 ++++---------------------
 1 file changed, 5 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c386ef8eb200..db701ec5a221 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -222,29 +222,6 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 		 encoder->port != PORT_A);
 }
 
-static int cnl_max_source_rate(struct intel_dp *intel_dp)
-{
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-	enum port port = dig_port->base.port;
-
-	u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-
-	/* Low voltage SKUs are limited to max of 5.4G */
-	if (voltage == VOLTAGE_INFO_0_85V)
-		return 540000;
-
-	/* For this SKU 8.1G is supported in all ports */
-	if (IS_CNL_WITH_PORT_F(dev_priv))
-		return 810000;
-
-	/* For other SKUs, max rate on ports A and D is 5.4G */
-	if (port == PORT_A || port == PORT_D)
-		return 540000;
-
-	return 810000;
-}
-
 static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -270,7 +247,7 @@ static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
 	/* The values must be in increasing order */
-	static const int cnl_rates[] = {
+	static const int icl_rates[] = {
 		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 	};
 	static const int bxt_rates[] = {
@@ -295,12 +272,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 	drm_WARN_ON(&dev_priv->drm,
 		    intel_dp->source_rates || intel_dp->num_source_rates);
 
-	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
-		source_rates = cnl_rates;
-		size = ARRAY_SIZE(cnl_rates);
-		if (DISPLAY_VER(dev_priv) == 10)
-			max_rate = cnl_max_source_rate(intel_dp);
-		else if (IS_JSL_EHL(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 11) {
+		source_rates = icl_rates;
+		size = ARRAY_SIZE(icl_rates);
+		if (IS_JSL_EHL(dev_priv))
 			max_rate = ehl_max_source_rate(intel_dp);
 		else
 			max_rate = icl_max_source_rate(intel_dp);
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 11/30] drm/i915/display: remove explicit CNL handling from intel_dp.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:10:55PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in intel_dp.c.
> 
> Remove code and rename functions/macros accordingly to use ICL prefix.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 35 ++++---------------------
>  1 file changed, 5 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c386ef8eb200..db701ec5a221 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -222,29 +222,6 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
>  		 encoder->port != PORT_A);
>  }
>  
> -static int cnl_max_source_rate(struct intel_dp *intel_dp)
> -{
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> -	enum port port = dig_port->base.port;
> -
> -	u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -
> -	/* Low voltage SKUs are limited to max of 5.4G */
> -	if (voltage == VOLTAGE_INFO_0_85V)
> -		return 540000;
> -
> -	/* For this SKU 8.1G is supported in all ports */
> -	if (IS_CNL_WITH_PORT_F(dev_priv))
> -		return 810000;
> -
> -	/* For other SKUs, max rate on ports A and D is 5.4G */
> -	if (port == PORT_A || port == PORT_D)
> -		return 540000;
> -
> -	return 810000;
> -}
> -
>  static int icl_max_source_rate(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -270,7 +247,7 @@ static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>  	/* The values must be in increasing order */
> -	static const int cnl_rates[] = {
> +	static const int icl_rates[] = {
>  		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
>  	};
>  	static const int bxt_rates[] = {
> @@ -295,12 +272,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  	drm_WARN_ON(&dev_priv->drm,
>  		    intel_dp->source_rates || intel_dp->num_source_rates);
>  
> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> -		source_rates = cnl_rates;
> -		size = ARRAY_SIZE(cnl_rates);
> -		if (DISPLAY_VER(dev_priv) == 10)
> -			max_rate = cnl_max_source_rate(intel_dp);
> -		else if (IS_JSL_EHL(dev_priv))
> +	if (DISPLAY_VER(dev_priv) >= 11) {
> +		source_rates = icl_rates;
> +		size = ARRAY_SIZE(icl_rates);
> +		if (IS_JSL_EHL(dev_priv))
>  			max_rate = ehl_max_source_rate(intel_dp);
>  		else
>  			max_rate = icl_max_source_rate(intel_dp);
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 12/30] drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_ddi.c.

A lot of special code for CNL can be removed. There were some
__cnl.*() functions that were created to share the implementation
between ICL and CNL. Those are now embedded in the only caller, in ICL.

Remove code and rename functions/macros accordingly to use ICL prefix
for those that are still needed.

Verified with:

	make EXTRA_CFLAGS=-Wunused drivers/gpu/drm/i915/display/intel_dpll_mgr.o

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 586 +++---------------
 drivers/gpu/drm/i915/i915_reg.h               |   4 +-
 2 files changed, 96 insertions(+), 494 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8e2bd8fa090a..0d72917e5670 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -168,7 +168,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
 	else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
 		return MG_PLL_ENABLE(0);
 
-	return CNL_DPLL_ENABLE(pll->info->id);
+	return ICL_DPLL_ENABLE(pll->info->id);
 }
 
 static i915_reg_t
@@ -2346,160 +2346,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
 	.dump_hw_state = bxt_dump_hw_state,
 };
 
-static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
-			       struct intel_shared_dpll *pll)
-{
-	const enum intel_dpll_id id = pll->info->id;
-	u32 val;
-
-	/* 1. Enable DPLL power in DPLL_ENABLE. */
-	val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
-	val |= PLL_POWER_ENABLE;
-	intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
-
-	/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
-	if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id),
-				  PLL_POWER_STATE, 5))
-		drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id);
-
-	/*
-	 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
-	 * select DP mode, and set DP link rate.
-	 */
-	val = pll->state.hw_state.cfgcr0;
-	intel_de_write(dev_priv, CNL_DPLL_CFGCR0(id), val);
-
-	/* 4. Reab back to ensure writes completed */
-	intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR0(id));
-
-	/* 3. Configure DPLL_CFGCR0 */
-	/* Avoid touch CFGCR1 if HDMI mode is not enabled */
-	if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
-		val = pll->state.hw_state.cfgcr1;
-		intel_de_write(dev_priv, CNL_DPLL_CFGCR1(id), val);
-		/* 4. Reab back to ensure writes completed */
-		intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR1(id));
-	}
-
-	/*
-	 * 5. If the frequency will result in a change to the voltage
-	 * requirement, follow the Display Voltage Frequency Switching
-	 * Sequence Before Frequency Change
-	 *
-	 * Note: DVFS is actually handled via the cdclk code paths,
-	 * hence we do nothing here.
-	 */
-
-	/* 6. Enable DPLL in DPLL_ENABLE. */
-	val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
-	val |= PLL_ENABLE;
-	intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
-
-	/* 7. Wait for PLL lock status in DPLL_ENABLE. */
-	if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
-		drm_err(&dev_priv->drm, "PLL %d not locked\n", id);
-
-	/*
-	 * 8. If the frequency will result in a change to the voltage
-	 * requirement, follow the Display Voltage Frequency Switching
-	 * Sequence After Frequency Change
-	 *
-	 * Note: DVFS is actually handled via the cdclk code paths,
-	 * hence we do nothing here.
-	 */
-
-	/*
-	 * 9. turn on the clock for the DDI and map the DPLL to the DDI
-	 * Done at intel_ddi_clk_select
-	 */
-}
-
-static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
-				struct intel_shared_dpll *pll)
-{
-	const enum intel_dpll_id id = pll->info->id;
-	u32 val;
-
-	/*
-	 * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
-	 * Done at intel_ddi_post_disable
-	 */
-
-	/*
-	 * 2. If the frequency will result in a change to the voltage
-	 * requirement, follow the Display Voltage Frequency Switching
-	 * Sequence Before Frequency Change
-	 *
-	 * Note: DVFS is actually handled via the cdclk code paths,
-	 * hence we do nothing here.
-	 */
-
-	/* 3. Disable DPLL through DPLL_ENABLE. */
-	val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
-	val &= ~PLL_ENABLE;
-	intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
-
-	/* 4. Wait for PLL not locked status in DPLL_ENABLE. */
-	if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
-		drm_err(&dev_priv->drm, "PLL %d locked\n", id);
-
-	/*
-	 * 5. If the frequency will result in a change to the voltage
-	 * requirement, follow the Display Voltage Frequency Switching
-	 * Sequence After Frequency Change
-	 *
-	 * Note: DVFS is actually handled via the cdclk code paths,
-	 * hence we do nothing here.
-	 */
-
-	/* 6. Disable DPLL power in DPLL_ENABLE. */
-	val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
-	val &= ~PLL_POWER_ENABLE;
-	intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
-
-	/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
-	if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id),
-				    PLL_POWER_STATE, 5))
-		drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", id);
-}
-
-static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
-				     struct intel_shared_dpll *pll,
-				     struct intel_dpll_hw_state *hw_state)
-{
-	const enum intel_dpll_id id = pll->info->id;
-	intel_wakeref_t wakeref;
-	u32 val;
-	bool ret;
-
-	wakeref = intel_display_power_get_if_enabled(dev_priv,
-						     POWER_DOMAIN_DISPLAY_CORE);
-	if (!wakeref)
-		return false;
-
-	ret = false;
-
-	val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
-	if (!(val & PLL_ENABLE))
-		goto out;
-
-	val = intel_de_read(dev_priv, CNL_DPLL_CFGCR0(id));
-	hw_state->cfgcr0 = val;
-
-	/* avoid reading back stale values if HDMI mode is not enabled */
-	if (val & DPLL_CFGCR0_HDMI_MODE) {
-		hw_state->cfgcr1 = intel_de_read(dev_priv,
-						 CNL_DPLL_CFGCR1(id));
-	}
-	ret = true;
-
-out:
-	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
-
-	return ret;
-}
-
-static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
+static void icl_wrpll_get_multipliers(int bestdiv, int *pdiv,
 				      int *qdiv, int *kdiv)
 {
 	/* even dividers */
@@ -2538,7 +2385,7 @@ static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
 	}
 }
 
-static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
+static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
 				      u32 dco_freq, u32 ref_freq,
 				      int pdiv, int qdiv, int kdiv)
 {
@@ -2586,86 +2433,6 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
 	params->dco_fraction = dco & 0x7fff;
 }
 
-static bool
-__cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
-			  struct skl_wrpll_params *wrpll_params,
-			  int ref_clock)
-{
-	u32 afe_clock = crtc_state->port_clock * 5;
-	u32 dco_min = 7998000;
-	u32 dco_max = 10000000;
-	u32 dco_mid = (dco_min + dco_max) / 2;
-	static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
-					 18, 20, 24, 28, 30, 32,  36,  40,
-					 42, 44, 48, 50, 52, 54,  56,  60,
-					 64, 66, 68, 70, 72, 76,  78,  80,
-					 84, 88, 90, 92, 96, 98, 100, 102,
-					  3,  5,  7,  9, 15, 21 };
-	u32 dco, best_dco = 0, dco_centrality = 0;
-	u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
-	int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
-
-	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
-		dco = afe_clock * dividers[d];
-
-		if ((dco <= dco_max) && (dco >= dco_min)) {
-			dco_centrality = abs(dco - dco_mid);
-
-			if (dco_centrality < best_dco_centrality) {
-				best_dco_centrality = dco_centrality;
-				best_div = dividers[d];
-				best_dco = dco;
-			}
-		}
-	}
-
-	if (best_div == 0)
-		return false;
-
-	cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
-	cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
-				  pdiv, qdiv, kdiv);
-
-	return true;
-}
-
-static bool
-cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
-			struct skl_wrpll_params *wrpll_params)
-{
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-
-	return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
-					 i915->dpll.ref_clks.nssc);
-}
-
-static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
-{
-	u32 cfgcr0, cfgcr1;
-	struct skl_wrpll_params wrpll_params = { 0, };
-
-	cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
-
-	if (!cnl_ddi_calculate_wrpll(crtc_state, &wrpll_params))
-		return false;
-
-	cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
-		wrpll_params.dco_integer;
-
-	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
-		DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
-		DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
-		DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
-		DPLL_CFGCR1_CENTRAL_FREQ;
-
-	memset(&crtc_state->dpll_hw_state, 0,
-	       sizeof(crtc_state->dpll_hw_state));
-
-	crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
-	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
-	return true;
-}
-
 /*
  * Display WA #22010492432: ehl, tgl, adl-p
  * Program half of the nominal DCO divider fraction value.
@@ -2679,256 +2446,6 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
 		 i915->dpll.ref_clks.nssc == 38400;
 }
 
-static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
-				    const struct intel_shared_dpll *pll,
-				    const struct intel_dpll_hw_state *pll_state,
-				    int ref_clock)
-{
-	u32 dco_fraction;
-	u32 p0, p1, p2, dco_freq;
-
-	p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
-	p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
-
-	if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
-		p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
-			DPLL_CFGCR1_QDIV_RATIO_SHIFT;
-	else
-		p1 = 1;
-
-
-	switch (p0) {
-	case DPLL_CFGCR1_PDIV_2:
-		p0 = 2;
-		break;
-	case DPLL_CFGCR1_PDIV_3:
-		p0 = 3;
-		break;
-	case DPLL_CFGCR1_PDIV_5:
-		p0 = 5;
-		break;
-	case DPLL_CFGCR1_PDIV_7:
-		p0 = 7;
-		break;
-	}
-
-	switch (p2) {
-	case DPLL_CFGCR1_KDIV_1:
-		p2 = 1;
-		break;
-	case DPLL_CFGCR1_KDIV_2:
-		p2 = 2;
-		break;
-	case DPLL_CFGCR1_KDIV_3:
-		p2 = 3;
-		break;
-	}
-
-	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
-		   ref_clock;
-
-	dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
-		       DPLL_CFGCR0_DCO_FRACTION_SHIFT;
-
-	if (ehl_combo_pll_div_frac_wa_needed(dev_priv))
-		dco_fraction *= 2;
-
-	dco_freq += (dco_fraction * ref_clock) / 0x8000;
-
-	if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
-		return 0;
-
-	return dco_freq / (p0 * p1 * p2 * 5);
-}
-
-static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
-				  const struct intel_shared_dpll *pll,
-				  const struct intel_dpll_hw_state *pll_state)
-{
-	return __cnl_ddi_wrpll_get_freq(i915, pll, pll_state,
-					i915->dpll.ref_clks.nssc);
-}
-
-static bool
-cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
-{
-	u32 cfgcr0;
-
-	cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
-
-	switch (crtc_state->port_clock / 2) {
-	case 81000:
-		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
-		break;
-	case 135000:
-		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
-		break;
-	case 270000:
-		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
-		break;
-		/* eDP 1.4 rates */
-	case 162000:
-		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
-		break;
-	case 108000:
-		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
-		break;
-	case 216000:
-		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
-		break;
-	case 324000:
-		/* Some SKUs may require elevated I/O voltage to support this */
-		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
-		break;
-	case 405000:
-		/* Some SKUs may require elevated I/O voltage to support this */
-		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
-		break;
-	}
-
-	memset(&crtc_state->dpll_hw_state, 0,
-	       sizeof(crtc_state->dpll_hw_state));
-
-	crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
-
-	return true;
-}
-
-static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
-				  const struct intel_shared_dpll *pll,
-				  const struct intel_dpll_hw_state *pll_state)
-{
-	int link_clock = 0;
-
-	switch (pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
-	case DPLL_CFGCR0_LINK_RATE_810:
-		link_clock = 81000;
-		break;
-	case DPLL_CFGCR0_LINK_RATE_1080:
-		link_clock = 108000;
-		break;
-	case DPLL_CFGCR0_LINK_RATE_1350:
-		link_clock = 135000;
-		break;
-	case DPLL_CFGCR0_LINK_RATE_1620:
-		link_clock = 162000;
-		break;
-	case DPLL_CFGCR0_LINK_RATE_2160:
-		link_clock = 216000;
-		break;
-	case DPLL_CFGCR0_LINK_RATE_2700:
-		link_clock = 270000;
-		break;
-	case DPLL_CFGCR0_LINK_RATE_3240:
-		link_clock = 324000;
-		break;
-	case DPLL_CFGCR0_LINK_RATE_4050:
-		link_clock = 405000;
-		break;
-	default:
-		drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
-		break;
-	}
-
-	return link_clock * 2;
-}
-
-static bool cnl_get_dpll(struct intel_atomic_state *state,
-			 struct intel_crtc *crtc,
-			 struct intel_encoder *encoder)
-{
-	struct intel_crtc_state *crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_shared_dpll *pll;
-	bool bret;
-
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
-		bret = cnl_ddi_hdmi_pll_dividers(crtc_state);
-		if (!bret) {
-			drm_dbg_kms(&i915->drm,
-				    "Could not get HDMI pll dividers.\n");
-			return false;
-		}
-	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
-		bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);
-		if (!bret) {
-			drm_dbg_kms(&i915->drm,
-				    "Could not set DP dpll HW state.\n");
-			return false;
-		}
-	} else {
-		drm_dbg_kms(&i915->drm,
-			    "Skip DPLL setup for output_types 0x%x\n",
-			    crtc_state->output_types);
-		return false;
-	}
-
-	pll = intel_find_shared_dpll(state, crtc,
-				     &crtc_state->dpll_hw_state,
-				     BIT(DPLL_ID_SKL_DPLL2) |
-				     BIT(DPLL_ID_SKL_DPLL1) |
-				     BIT(DPLL_ID_SKL_DPLL0));
-	if (!pll) {
-		drm_dbg_kms(&i915->drm, "No PLL selected\n");
-		return false;
-	}
-
-	intel_reference_shared_dpll(state, crtc,
-				    pll, &crtc_state->dpll_hw_state);
-
-	crtc_state->shared_dpll = pll;
-
-	return true;
-}
-
-static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
-				const struct intel_shared_dpll *pll,
-				const struct intel_dpll_hw_state *pll_state)
-{
-	if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
-		return cnl_ddi_wrpll_get_freq(i915, pll, pll_state);
-	else
-		return cnl_ddi_lcpll_get_freq(i915, pll, pll_state);
-}
-
-static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915)
-{
-	/* No SSC reference */
-	i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
-}
-
-static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
-			      const struct intel_dpll_hw_state *hw_state)
-{
-	drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: "
-		    "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
-		    hw_state->cfgcr0,
-		    hw_state->cfgcr1);
-}
-
-static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
-	.enable = cnl_ddi_pll_enable,
-	.disable = cnl_ddi_pll_disable,
-	.get_hw_state = cnl_ddi_pll_get_hw_state,
-	.get_freq = cnl_ddi_pll_get_freq,
-};
-
-static const struct dpll_info cnl_plls[] = {
-	{ "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
-	{ "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
-	{ "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
-	{ },
-};
-
-static const struct intel_dpll_mgr cnl_pll_mgr = {
-	.dpll_info = cnl_plls,
-	.get_dplls = cnl_get_dpll,
-	.put_dplls = intel_put_dpll,
-	.update_ref_clks = cnl_update_dpll_ref_clks,
-	.dump_hw_state = cnl_dump_hw_state,
-};
-
 struct icl_combo_pll_params {
 	int clock;
 	struct skl_wrpll_params wrpll;
@@ -3105,17 +2622,104 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
 	       struct skl_wrpll_params *wrpll_params)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	int ref_clock = icl_wrpll_ref_clock(i915);
+	u32 afe_clock = crtc_state->port_clock * 5;
+	u32 dco_min = 7998000;
+	u32 dco_max = 10000000;
+	u32 dco_mid = (dco_min + dco_max) / 2;
+	static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
+					 18, 20, 24, 28, 30, 32,  36,  40,
+					 42, 44, 48, 50, 52, 54,  56,  60,
+					 64, 66, 68, 70, 72, 76,  78,  80,
+					 84, 88, 90, 92, 96, 98, 100, 102,
+					  3,  5,  7,  9, 15, 21 };
+	u32 dco, best_dco = 0, dco_centrality = 0;
+	u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
+	int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
+
+	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
+		dco = afe_clock * dividers[d];
+
+		if (dco <= dco_max && dco >= dco_min) {
+			dco_centrality = abs(dco - dco_mid);
 
-	return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
-					 icl_wrpll_ref_clock(i915));
+			if (dco_centrality < best_dco_centrality) {
+				best_dco_centrality = dco_centrality;
+				best_div = dividers[d];
+				best_dco = dco;
+			}
+		}
+	}
+
+	if (best_div == 0)
+		return false;
+
+	icl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
+	icl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
+				  pdiv, qdiv, kdiv);
+
+	return true;
 }
 
 static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
 				      const struct intel_shared_dpll *pll,
 				      const struct intel_dpll_hw_state *pll_state)
 {
-	return __cnl_ddi_wrpll_get_freq(i915, pll, pll_state,
-					icl_wrpll_ref_clock(i915));
+	int ref_clock = icl_wrpll_ref_clock(i915);
+	u32 dco_fraction;
+	u32 p0, p1, p2, dco_freq;
+
+	p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
+	p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
+
+	if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
+		p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
+			DPLL_CFGCR1_QDIV_RATIO_SHIFT;
+	else
+		p1 = 1;
+
+	switch (p0) {
+	case DPLL_CFGCR1_PDIV_2:
+		p0 = 2;
+		break;
+	case DPLL_CFGCR1_PDIV_3:
+		p0 = 3;
+		break;
+	case DPLL_CFGCR1_PDIV_5:
+		p0 = 5;
+		break;
+	case DPLL_CFGCR1_PDIV_7:
+		p0 = 7;
+		break;
+	}
+
+	switch (p2) {
+	case DPLL_CFGCR1_KDIV_1:
+		p2 = 1;
+		break;
+	case DPLL_CFGCR1_KDIV_2:
+		p2 = 2;
+		break;
+	case DPLL_CFGCR1_KDIV_3:
+		p2 = 3;
+		break;
+	}
+
+	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
+		   ref_clock;
+
+	dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+		       DPLL_CFGCR0_DCO_FRACTION_SHIFT;
+
+	if (ehl_combo_pll_div_frac_wa_needed(i915))
+		dco_fraction *= 2;
+
+	dco_freq += (dco_fraction * ref_clock) / 0x8000;
+
+	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
+		return 0;
+
+	return dco_freq / (p0 * p1 * p2 * 5);
 }
 
 static void icl_calc_dpll_state(struct drm_i915_private *i915,
@@ -4479,8 +4083,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
 		dpll_mgr = &ehl_pll_mgr;
 	else if (DISPLAY_VER(dev_priv) >= 11)
 		dpll_mgr = &icl_pll_mgr;
-	else if (IS_CANNONLAKE(dev_priv))
-		dpll_mgr = &cnl_pll_mgr;
 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 		dpll_mgr = &bxt_pll_mgr;
 	else if (DISPLAY_VER(dev_priv) == 9)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6a894ffd91e1..65596987b156 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10566,7 +10566,7 @@ enum skl_power_gate {
 							ADLS_DPCLKA_DDIJ_SEL_MASK, \
 							ADLS_DPCLKA_DDIK_SEL_MASK)
 
-/* CNL PLL */
+/* ICL PLL */
 #define DPLL0_ENABLE		0x46010
 #define DPLL1_ENABLE		0x46014
 #define _ADLS_DPLL2_ENABLE	0x46018
@@ -10575,7 +10575,7 @@ enum skl_power_gate {
 #define  PLL_LOCK		(1 << 30)
 #define  PLL_POWER_ENABLE	(1 << 27)
 #define  PLL_POWER_STATE	(1 << 26)
-#define CNL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
 					   _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
 
 #define TBT_PLL_ENABLE		_MMIO(0x46020)
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 12/30] drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:10:56PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in intel_ddi.c.
> 
> A lot of special code for CNL can be removed. There were some
> __cnl.*() functions that were created to share the implementation
> between ICL and CNL. Those are now embedded in the only caller, in ICL.
> 
> Remove code and rename functions/macros accordingly to use ICL prefix
> for those that are still needed.
> 
> Verified with:
> 
> 	make EXTRA_CFLAGS=-Wunused drivers/gpu/drm/i915/display/intel_dpll_mgr.o

good idea...

> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 586 +++---------------
>  drivers/gpu/drm/i915/i915_reg.h               |   4 +-
>  2 files changed, 96 insertions(+), 494 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 8e2bd8fa090a..0d72917e5670 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -168,7 +168,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
>  	else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
>  		return MG_PLL_ENABLE(0);
>  
> -	return CNL_DPLL_ENABLE(pll->info->id);
> +	return ICL_DPLL_ENABLE(pll->info->id);
>  }
>  
>  static i915_reg_t
> @@ -2346,160 +2346,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
>  	.dump_hw_state = bxt_dump_hw_state,
>  };
>  
> -static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
> -			       struct intel_shared_dpll *pll)
> -{
> -	const enum intel_dpll_id id = pll->info->id;
> -	u32 val;
> -
> -	/* 1. Enable DPLL power in DPLL_ENABLE. */
> -	val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
> -	val |= PLL_POWER_ENABLE;
> -	intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
> -
> -	/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
> -	if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id),
> -				  PLL_POWER_STATE, 5))
> -		drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id);
> -
> -	/*
> -	 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
> -	 * select DP mode, and set DP link rate.
> -	 */
> -	val = pll->state.hw_state.cfgcr0;
> -	intel_de_write(dev_priv, CNL_DPLL_CFGCR0(id), val);
> -
> -	/* 4. Reab back to ensure writes completed */
> -	intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR0(id));
> -
> -	/* 3. Configure DPLL_CFGCR0 */
> -	/* Avoid touch CFGCR1 if HDMI mode is not enabled */
> -	if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
> -		val = pll->state.hw_state.cfgcr1;
> -		intel_de_write(dev_priv, CNL_DPLL_CFGCR1(id), val);
> -		/* 4. Reab back to ensure writes completed */
> -		intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR1(id));
> -	}
> -
> -	/*
> -	 * 5. If the frequency will result in a change to the voltage
> -	 * requirement, follow the Display Voltage Frequency Switching
> -	 * Sequence Before Frequency Change
> -	 *
> -	 * Note: DVFS is actually handled via the cdclk code paths,
> -	 * hence we do nothing here.
> -	 */
> -
> -	/* 6. Enable DPLL in DPLL_ENABLE. */
> -	val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
> -	val |= PLL_ENABLE;
> -	intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
> -
> -	/* 7. Wait for PLL lock status in DPLL_ENABLE. */
> -	if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
> -		drm_err(&dev_priv->drm, "PLL %d not locked\n", id);
> -
> -	/*
> -	 * 8. If the frequency will result in a change to the voltage
> -	 * requirement, follow the Display Voltage Frequency Switching
> -	 * Sequence After Frequency Change
> -	 *
> -	 * Note: DVFS is actually handled via the cdclk code paths,
> -	 * hence we do nothing here.
> -	 */
> -
> -	/*
> -	 * 9. turn on the clock for the DDI and map the DPLL to the DDI
> -	 * Done at intel_ddi_clk_select
> -	 */
> -}
> -
> -static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
> -				struct intel_shared_dpll *pll)
> -{
> -	const enum intel_dpll_id id = pll->info->id;
> -	u32 val;
> -
> -	/*
> -	 * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
> -	 * Done at intel_ddi_post_disable
> -	 */
> -
> -	/*
> -	 * 2. If the frequency will result in a change to the voltage
> -	 * requirement, follow the Display Voltage Frequency Switching
> -	 * Sequence Before Frequency Change
> -	 *
> -	 * Note: DVFS is actually handled via the cdclk code paths,
> -	 * hence we do nothing here.
> -	 */
> -
> -	/* 3. Disable DPLL through DPLL_ENABLE. */
> -	val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
> -	val &= ~PLL_ENABLE;
> -	intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
> -
> -	/* 4. Wait for PLL not locked status in DPLL_ENABLE. */
> -	if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
> -		drm_err(&dev_priv->drm, "PLL %d locked\n", id);
> -
> -	/*
> -	 * 5. If the frequency will result in a change to the voltage
> -	 * requirement, follow the Display Voltage Frequency Switching
> -	 * Sequence After Frequency Change
> -	 *
> -	 * Note: DVFS is actually handled via the cdclk code paths,
> -	 * hence we do nothing here.
> -	 */
> -
> -	/* 6. Disable DPLL power in DPLL_ENABLE. */
> -	val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
> -	val &= ~PLL_POWER_ENABLE;
> -	intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
> -
> -	/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
> -	if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id),
> -				    PLL_POWER_STATE, 5))
> -		drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", id);
> -}
> -
> -static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> -				     struct intel_shared_dpll *pll,
> -				     struct intel_dpll_hw_state *hw_state)
> -{
> -	const enum intel_dpll_id id = pll->info->id;
> -	intel_wakeref_t wakeref;
> -	u32 val;
> -	bool ret;
> -
> -	wakeref = intel_display_power_get_if_enabled(dev_priv,
> -						     POWER_DOMAIN_DISPLAY_CORE);
> -	if (!wakeref)
> -		return false;
> -
> -	ret = false;
> -
> -	val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
> -	if (!(val & PLL_ENABLE))
> -		goto out;
> -
> -	val = intel_de_read(dev_priv, CNL_DPLL_CFGCR0(id));
> -	hw_state->cfgcr0 = val;
> -
> -	/* avoid reading back stale values if HDMI mode is not enabled */
> -	if (val & DPLL_CFGCR0_HDMI_MODE) {
> -		hw_state->cfgcr1 = intel_de_read(dev_priv,
> -						 CNL_DPLL_CFGCR1(id));
> -	}
> -	ret = true;
> -
> -out:
> -	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
> -
> -	return ret;
> -}
> -
> -static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
> +static void icl_wrpll_get_multipliers(int bestdiv, int *pdiv,
>  				      int *qdiv, int *kdiv)
>  {
>  	/* even dividers */
> @@ -2538,7 +2385,7 @@ static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
>  	}
>  }
>  
> -static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> +static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
>  				      u32 dco_freq, u32 ref_freq,
>  				      int pdiv, int qdiv, int kdiv)
>  {
> @@ -2586,86 +2433,6 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
>  	params->dco_fraction = dco & 0x7fff;
>  }
>  
> -static bool
> -__cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
> -			  struct skl_wrpll_params *wrpll_params,
> -			  int ref_clock)
> -{
> -	u32 afe_clock = crtc_state->port_clock * 5;
> -	u32 dco_min = 7998000;
> -	u32 dco_max = 10000000;
> -	u32 dco_mid = (dco_min + dco_max) / 2;
> -	static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
> -					 18, 20, 24, 28, 30, 32,  36,  40,
> -					 42, 44, 48, 50, 52, 54,  56,  60,
> -					 64, 66, 68, 70, 72, 76,  78,  80,
> -					 84, 88, 90, 92, 96, 98, 100, 102,
> -					  3,  5,  7,  9, 15, 21 };
> -	u32 dco, best_dco = 0, dco_centrality = 0;
> -	u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
> -	int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
> -
> -	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> -		dco = afe_clock * dividers[d];
> -
> -		if ((dco <= dco_max) && (dco >= dco_min)) {
> -			dco_centrality = abs(dco - dco_mid);
> -
> -			if (dco_centrality < best_dco_centrality) {
> -				best_dco_centrality = dco_centrality;
> -				best_div = dividers[d];
> -				best_dco = dco;
> -			}
> -		}
> -	}
> -
> -	if (best_div == 0)
> -		return false;
> -
> -	cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
> -	cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
> -				  pdiv, qdiv, kdiv);
> -
> -	return true;
> -}
> -
> -static bool
> -cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
> -			struct skl_wrpll_params *wrpll_params)
> -{
> -	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> -
> -	return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
> -					 i915->dpll.ref_clks.nssc);
> -}
> -
> -static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> -{
> -	u32 cfgcr0, cfgcr1;
> -	struct skl_wrpll_params wrpll_params = { 0, };
> -
> -	cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
> -
> -	if (!cnl_ddi_calculate_wrpll(crtc_state, &wrpll_params))
> -		return false;
> -
> -	cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
> -		wrpll_params.dco_integer;
> -
> -	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
> -		DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
> -		DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
> -		DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
> -		DPLL_CFGCR1_CENTRAL_FREQ;
> -
> -	memset(&crtc_state->dpll_hw_state, 0,
> -	       sizeof(crtc_state->dpll_hw_state));
> -
> -	crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
> -	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
> -	return true;
> -}
> -
>  /*
>   * Display WA #22010492432: ehl, tgl, adl-p
>   * Program half of the nominal DCO divider fraction value.
> @@ -2679,256 +2446,6 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
>  		 i915->dpll.ref_clks.nssc == 38400;
>  }
>  
> -static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> -				    const struct intel_shared_dpll *pll,
> -				    const struct intel_dpll_hw_state *pll_state,
> -				    int ref_clock)
> -{
> -	u32 dco_fraction;
> -	u32 p0, p1, p2, dco_freq;
> -
> -	p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
> -	p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
> -
> -	if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
> -		p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
> -			DPLL_CFGCR1_QDIV_RATIO_SHIFT;
> -	else
> -		p1 = 1;
> -
> -
> -	switch (p0) {
> -	case DPLL_CFGCR1_PDIV_2:
> -		p0 = 2;
> -		break;
> -	case DPLL_CFGCR1_PDIV_3:
> -		p0 = 3;
> -		break;
> -	case DPLL_CFGCR1_PDIV_5:
> -		p0 = 5;
> -		break;
> -	case DPLL_CFGCR1_PDIV_7:
> -		p0 = 7;
> -		break;
> -	}
> -
> -	switch (p2) {
> -	case DPLL_CFGCR1_KDIV_1:
> -		p2 = 1;
> -		break;
> -	case DPLL_CFGCR1_KDIV_2:
> -		p2 = 2;
> -		break;
> -	case DPLL_CFGCR1_KDIV_3:
> -		p2 = 3;
> -		break;
> -	}
> -
> -	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
> -		   ref_clock;
> -
> -	dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> -		       DPLL_CFGCR0_DCO_FRACTION_SHIFT;
> -
> -	if (ehl_combo_pll_div_frac_wa_needed(dev_priv))
> -		dco_fraction *= 2;
> -
> -	dco_freq += (dco_fraction * ref_clock) / 0x8000;
> -
> -	if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
> -		return 0;
> -
> -	return dco_freq / (p0 * p1 * p2 * 5);
> -}
> -
> -static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> -				  const struct intel_shared_dpll *pll,
> -				  const struct intel_dpll_hw_state *pll_state)
> -{
> -	return __cnl_ddi_wrpll_get_freq(i915, pll, pll_state,
> -					i915->dpll.ref_clks.nssc);
> -}
> -
> -static bool
> -cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> -{
> -	u32 cfgcr0;
> -
> -	cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
> -
> -	switch (crtc_state->port_clock / 2) {
> -	case 81000:
> -		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
> -		break;
> -	case 135000:
> -		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
> -		break;
> -	case 270000:
> -		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
> -		break;
> -		/* eDP 1.4 rates */
> -	case 162000:
> -		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
> -		break;
> -	case 108000:
> -		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
> -		break;
> -	case 216000:
> -		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
> -		break;
> -	case 324000:
> -		/* Some SKUs may require elevated I/O voltage to support this */
> -		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
> -		break;
> -	case 405000:
> -		/* Some SKUs may require elevated I/O voltage to support this */
> -		cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
> -		break;
> -	}
> -
> -	memset(&crtc_state->dpll_hw_state, 0,
> -	       sizeof(crtc_state->dpll_hw_state));
> -
> -	crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
> -
> -	return true;
> -}
> -
> -static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
> -				  const struct intel_shared_dpll *pll,
> -				  const struct intel_dpll_hw_state *pll_state)
> -{
> -	int link_clock = 0;
> -
> -	switch (pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
> -	case DPLL_CFGCR0_LINK_RATE_810:
> -		link_clock = 81000;
> -		break;
> -	case DPLL_CFGCR0_LINK_RATE_1080:
> -		link_clock = 108000;
> -		break;
> -	case DPLL_CFGCR0_LINK_RATE_1350:
> -		link_clock = 135000;
> -		break;
> -	case DPLL_CFGCR0_LINK_RATE_1620:
> -		link_clock = 162000;
> -		break;
> -	case DPLL_CFGCR0_LINK_RATE_2160:
> -		link_clock = 216000;
> -		break;
> -	case DPLL_CFGCR0_LINK_RATE_2700:
> -		link_clock = 270000;
> -		break;
> -	case DPLL_CFGCR0_LINK_RATE_3240:
> -		link_clock = 324000;
> -		break;
> -	case DPLL_CFGCR0_LINK_RATE_4050:
> -		link_clock = 405000;
> -		break;
> -	default:
> -		drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
> -		break;
> -	}
> -
> -	return link_clock * 2;
> -}
> -
> -static bool cnl_get_dpll(struct intel_atomic_state *state,
> -			 struct intel_crtc *crtc,
> -			 struct intel_encoder *encoder)
> -{
> -	struct intel_crtc_state *crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> -	struct intel_shared_dpll *pll;
> -	bool bret;
> -
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> -		bret = cnl_ddi_hdmi_pll_dividers(crtc_state);
> -		if (!bret) {
> -			drm_dbg_kms(&i915->drm,
> -				    "Could not get HDMI pll dividers.\n");
> -			return false;
> -		}
> -	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
> -		bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);
> -		if (!bret) {
> -			drm_dbg_kms(&i915->drm,
> -				    "Could not set DP dpll HW state.\n");
> -			return false;
> -		}
> -	} else {
> -		drm_dbg_kms(&i915->drm,
> -			    "Skip DPLL setup for output_types 0x%x\n",
> -			    crtc_state->output_types);
> -		return false;
> -	}
> -
> -	pll = intel_find_shared_dpll(state, crtc,
> -				     &crtc_state->dpll_hw_state,
> -				     BIT(DPLL_ID_SKL_DPLL2) |
> -				     BIT(DPLL_ID_SKL_DPLL1) |
> -				     BIT(DPLL_ID_SKL_DPLL0));
> -	if (!pll) {
> -		drm_dbg_kms(&i915->drm, "No PLL selected\n");
> -		return false;
> -	}
> -
> -	intel_reference_shared_dpll(state, crtc,
> -				    pll, &crtc_state->dpll_hw_state);
> -
> -	crtc_state->shared_dpll = pll;
> -
> -	return true;
> -}
> -
> -static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
> -				const struct intel_shared_dpll *pll,
> -				const struct intel_dpll_hw_state *pll_state)
> -{
> -	if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
> -		return cnl_ddi_wrpll_get_freq(i915, pll, pll_state);
> -	else
> -		return cnl_ddi_lcpll_get_freq(i915, pll, pll_state);
> -}
> -
> -static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915)
> -{
> -	/* No SSC reference */
> -	i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
> -}
> -
> -static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
> -			      const struct intel_dpll_hw_state *hw_state)
> -{
> -	drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: "
> -		    "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
> -		    hw_state->cfgcr0,
> -		    hw_state->cfgcr1);
> -}
> -
> -static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
> -	.enable = cnl_ddi_pll_enable,
> -	.disable = cnl_ddi_pll_disable,
> -	.get_hw_state = cnl_ddi_pll_get_hw_state,
> -	.get_freq = cnl_ddi_pll_get_freq,
> -};
> -
> -static const struct dpll_info cnl_plls[] = {
> -	{ "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
> -	{ "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> -	{ "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> -	{ },
> -};
> -
> -static const struct intel_dpll_mgr cnl_pll_mgr = {
> -	.dpll_info = cnl_plls,
> -	.get_dplls = cnl_get_dpll,
> -	.put_dplls = intel_put_dpll,
> -	.update_ref_clks = cnl_update_dpll_ref_clks,
> -	.dump_hw_state = cnl_dump_hw_state,
> -};
> -
>  struct icl_combo_pll_params {
>  	int clock;
>  	struct skl_wrpll_params wrpll;
> @@ -3105,17 +2622,104 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
>  	       struct skl_wrpll_params *wrpll_params)
>  {
>  	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	int ref_clock = icl_wrpll_ref_clock(i915);
> +	u32 afe_clock = crtc_state->port_clock * 5;
> +	u32 dco_min = 7998000;
> +	u32 dco_max = 10000000;
> +	u32 dco_mid = (dco_min + dco_max) / 2;
> +	static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
> +					 18, 20, 24, 28, 30, 32,  36,  40,
> +					 42, 44, 48, 50, 52, 54,  56,  60,
> +					 64, 66, 68, 70, 72, 76,  78,  80,
> +					 84, 88, 90, 92, 96, 98, 100, 102,
> +					  3,  5,  7,  9, 15, 21 };
> +	u32 dco, best_dco = 0, dco_centrality = 0;
> +	u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
> +	int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
> +
> +	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> +		dco = afe_clock * dividers[d];
> +
> +		if (dco <= dco_max && dco >= dco_min) {
> +			dco_centrality = abs(dco - dco_mid);
>  
> -	return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params,
> -					 icl_wrpll_ref_clock(i915));
> +			if (dco_centrality < best_dco_centrality) {
> +				best_dco_centrality = dco_centrality;
> +				best_div = dividers[d];
> +				best_dco = dco;
> +			}
> +		}
> +	}
> +
> +	if (best_div == 0)
> +		return false;
> +
> +	icl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
> +	icl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
> +				  pdiv, qdiv, kdiv);
> +
> +	return true;
>  }
>  
>  static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
>  				      const struct intel_shared_dpll *pll,
>  				      const struct intel_dpll_hw_state *pll_state)
>  {
> -	return __cnl_ddi_wrpll_get_freq(i915, pll, pll_state,
> -					icl_wrpll_ref_clock(i915));
> +	int ref_clock = icl_wrpll_ref_clock(i915);
> +	u32 dco_fraction;
> +	u32 p0, p1, p2, dco_freq;
> +
> +	p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
> +	p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
> +
> +	if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
> +		p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
> +			DPLL_CFGCR1_QDIV_RATIO_SHIFT;
> +	else
> +		p1 = 1;
> +
> +	switch (p0) {
> +	case DPLL_CFGCR1_PDIV_2:
> +		p0 = 2;
> +		break;
> +	case DPLL_CFGCR1_PDIV_3:
> +		p0 = 3;
> +		break;
> +	case DPLL_CFGCR1_PDIV_5:
> +		p0 = 5;
> +		break;
> +	case DPLL_CFGCR1_PDIV_7:
> +		p0 = 7;
> +		break;
> +	}
> +
> +	switch (p2) {
> +	case DPLL_CFGCR1_KDIV_1:
> +		p2 = 1;
> +		break;
> +	case DPLL_CFGCR1_KDIV_2:
> +		p2 = 2;
> +		break;
> +	case DPLL_CFGCR1_KDIV_3:
> +		p2 = 3;
> +		break;
> +	}
> +
> +	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
> +		   ref_clock;
> +
> +	dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> +		       DPLL_CFGCR0_DCO_FRACTION_SHIFT;
> +
> +	if (ehl_combo_pll_div_frac_wa_needed(i915))
> +		dco_fraction *= 2;
> +
> +	dco_freq += (dco_fraction * ref_clock) / 0x8000;
> +
> +	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
> +		return 0;
> +
> +	return dco_freq / (p0 * p1 * p2 * 5);
>  }
>  
>  static void icl_calc_dpll_state(struct drm_i915_private *i915,
> @@ -4479,8 +4083,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
>  		dpll_mgr = &ehl_pll_mgr;
>  	else if (DISPLAY_VER(dev_priv) >= 11)
>  		dpll_mgr = &icl_pll_mgr;
> -	else if (IS_CANNONLAKE(dev_priv))
> -		dpll_mgr = &cnl_pll_mgr;
>  	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>  		dpll_mgr = &bxt_pll_mgr;
>  	else if (DISPLAY_VER(dev_priv) == 9)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6a894ffd91e1..65596987b156 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10566,7 +10566,7 @@ enum skl_power_gate {
>  							ADLS_DPCLKA_DDIJ_SEL_MASK, \
>  							ADLS_DPCLKA_DDIK_SEL_MASK)
>  
> -/* CNL PLL */
> +/* ICL PLL */
>  #define DPLL0_ENABLE		0x46010
>  #define DPLL1_ENABLE		0x46014
>  #define _ADLS_DPLL2_ENABLE	0x46018
> @@ -10575,7 +10575,7 @@ enum skl_power_gate {
>  #define  PLL_LOCK		(1 << 30)
>  #define  PLL_POWER_ENABLE	(1 << 27)
>  #define  PLL_POWER_STATE	(1 << 26)
> -#define CNL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
> +#define ICL_DPLL_ENABLE(pll)	_MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
>  					   _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
>  
>  #define TBT_PLL_ENABLE		_MMIO(0x46020)
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 13/30] drm/i915/display: remove explicit CNL handling from intel_vdsc.c

[Lucas De Marchi]

Only one reference to CNL that is not needed, but code is the same for
DISPLAY_VER >= 11, so leave the code around and just remove the special
case for CNL.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 85749370508c..df3286aa6999 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -348,7 +348,10 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
 	if (DISPLAY_VER(i915) >= 12)
 		return true;
 
-	if ((DISPLAY_VER(i915) >= 11 || IS_CANNONLAKE(i915)) && (pipe != PIPE_A || (cpu_transcoder == TRANSCODER_EDP || cpu_transcoder == TRANSCODER_DSI_0 || cpu_transcoder == TRANSCODER_DSI_1)))
+	if (DISPLAY_VER(i915) >= 11 &&
+	    (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP ||
+	     cpu_transcoder == TRANSCODER_DSI_0 ||
+	     cpu_transcoder == TRANSCODER_DSI_1))
 		return true;
 
 	return false;
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 13/30] drm/i915/display: remove explicit CNL handling from intel_vdsc.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:10:57PM -0700, Lucas De Marchi wrote:
> Only one reference to CNL that is not needed, but code is the same for
> DISPLAY_VER >= 11, so leave the code around and just remove the special
> case for CNL.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 85749370508c..df3286aa6999 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -348,7 +348,10 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
>  	if (DISPLAY_VER(i915) >= 12)
>  		return true;
>  
> -	if ((DISPLAY_VER(i915) >= 11 || IS_CANNONLAKE(i915)) && (pipe != PIPE_A || (cpu_transcoder == TRANSCODER_EDP || cpu_transcoder == TRANSCODER_DSI_0 || cpu_transcoder == TRANSCODER_DSI_1)))
> +	if (DISPLAY_VER(i915) >= 11 &&
> +	    (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP ||
> +	     cpu_transcoder == TRANSCODER_DSI_0 ||
> +	     cpu_transcoder == TRANSCODER_DSI_1))
>  		return true;
>  
>  	return false;
> -- 
> 2.31.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH 14/30] drm/i915/display: remove explicit CNL handling from skl_universal_plane.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in skl_universal_plane.c.

Remove code and rename functions/macros accordingly to use ICL prefix.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 3ad04bf2a0fd..0f40f8b07724 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -835,7 +835,7 @@ static u32 skl_plane_ctl_rotate(unsigned int rotate)
 	return 0;
 }
 
-static u32 cnl_plane_ctl_flip(unsigned int reflect)
+static u32 icl_plane_ctl_flip(unsigned int reflect)
 {
 	switch (reflect) {
 	case 0:
@@ -917,8 +917,8 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 	plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
 	plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
 
-	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
-		plane_ctl |= cnl_plane_ctl_flip(rotation &
+	if (DISPLAY_VER(dev_priv) >= 11)
+		plane_ctl |= icl_plane_ctl_flip(rotation &
 						DRM_MODE_REFLECT_MASK);
 
 	if (key->flags & I915_SET_COLORKEY_DESTINATION)
@@ -1828,7 +1828,7 @@ static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 	if (plane_id == PLANE_CURSOR)
 		return false;
 
-	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 11)
 		return true;
 
 	if (IS_GEMINILAKE(dev_priv))
@@ -2144,7 +2144,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
 			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
 
-	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 11)
 		supported_rotations |= DRM_MODE_REFLECT_X;
 
 	drm_plane_create_rotation_property(&plane->base,
@@ -2174,7 +2174,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 	if (DISPLAY_VER(dev_priv) >= 12)
 		drm_plane_enable_fb_damage_clips(&plane->base);
 
-	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
+	if (DISPLAY_VER(dev_priv) >= 11)
 		drm_plane_create_scaling_filter_property(&plane->base,
 						BIT(DRM_SCALING_FILTER_DEFAULT) |
 						BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
@@ -2295,7 +2295,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
 		break;
 	}
 
-	if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && val & PLANE_CTL_FLIP_HORIZONTAL)
+	if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
 		plane_config->rotation |= DRM_MODE_REFLECT_X;
 
 	/* 90/270 degree rotation would require extra work */
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 14/30] drm/i915/display: remove explicit CNL handling from skl_universal_plane.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:10:58PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in skl_universal_plane.c.
> 
> Remove code and rename functions/macros accordingly to use ICL prefix.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 3ad04bf2a0fd..0f40f8b07724 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -835,7 +835,7 @@ static u32 skl_plane_ctl_rotate(unsigned int rotate)
>  	return 0;
>  }
>  
> -static u32 cnl_plane_ctl_flip(unsigned int reflect)
> +static u32 icl_plane_ctl_flip(unsigned int reflect)
>  {
>  	switch (reflect) {
>  	case 0:
> @@ -917,8 +917,8 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  	plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
>  	plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
>  
> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> -		plane_ctl |= cnl_plane_ctl_flip(rotation &
> +	if (DISPLAY_VER(dev_priv) >= 11)
> +		plane_ctl |= icl_plane_ctl_flip(rotation &
>  						DRM_MODE_REFLECT_MASK);
>  
>  	if (key->flags & I915_SET_COLORKEY_DESTINATION)
> @@ -1828,7 +1828,7 @@ static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
>  	if (plane_id == PLANE_CURSOR)
>  		return false;
>  
> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> +	if (DISPLAY_VER(dev_priv) >= 11)
>  		return true;
>  
>  	if (IS_GEMINILAKE(dev_priv))
> @@ -2144,7 +2144,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
>  			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
>  
> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> +	if (DISPLAY_VER(dev_priv) >= 11)
>  		supported_rotations |= DRM_MODE_REFLECT_X;
>  
>  	drm_plane_create_rotation_property(&plane->base,
> @@ -2174,7 +2174,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
>  	if (DISPLAY_VER(dev_priv) >= 12)
>  		drm_plane_enable_fb_damage_clips(&plane->base);
>  
> -	if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> +	if (DISPLAY_VER(dev_priv) >= 11)
>  		drm_plane_create_scaling_filter_property(&plane->base,
>  						BIT(DRM_SCALING_FILTER_DEFAULT) |
>  						BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
> @@ -2295,7 +2295,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
>  		break;
>  	}
>  
> -	if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && val & PLANE_CTL_FLIP_HORIZONTAL)
> +	if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
>  		plane_config->rotation |= DRM_MODE_REFLECT_X;
>  
>  	/* 90/270 degree rotation would require extra work */
> -- 
> 2.31.1
> 
> _______________________________________________
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[Intel-gfx] [PATCH 15/30] drm/i915/display: remove explicit CNL handling from intel_display_power.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_display_power.c.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 289 ------------------
 .../drm/i915/display/intel_display_power.h    |   2 -
 drivers/gpu/drm/i915/i915_reg.h               |  13 -
 3 files changed, 304 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 81efc77bada0..44aef0c44ab7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -447,17 +447,6 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 
 	hsw_wait_for_power_well_enable(dev_priv, power_well, false);
 
-	/* Display WA #1178: cnl */
-	if (IS_CANNONLAKE(dev_priv) &&
-	    pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
-	    pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
-		u32 val;
-
-		val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
-		val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
-		intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
-	}
-
 	if (power_well->desc->hsw.has_fuses) {
 		enum skl_power_gate pg;
 
@@ -2743,63 +2732,6 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
 	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
 
-#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |		\
-	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
-	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
-	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
-	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
-	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |		\
-	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |		\
-	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |		\
-	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |		\
-	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |		\
-	BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |		\
-	BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
-	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
-	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
-	BIT_ULL(POWER_DOMAIN_AUX_F) |			\
-	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
-	BIT_ULL(POWER_DOMAIN_VGA) |				\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |		\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |		\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |		\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |		\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_A_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
-	BIT_ULL(POWER_DOMAIN_AUX_IO_A) |		\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_B_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_C_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_D_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_AUX_F_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_AUX_F) |			\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS (		\
-	BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) |		\
-	BIT_ULL(POWER_DOMAIN_INIT))
-#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
-	CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
-	BIT_ULL(POWER_DOMAIN_GT_IRQ) |			\
-	BIT_ULL(POWER_DOMAIN_MODESET) |			\
-	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
-	BIT_ULL(POWER_DOMAIN_INIT))
-
 /*
  * ICL PW_0/PG_0 domains (HW/DMC control):
  * - PCI
@@ -3706,148 +3638,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
 	},
 };
 
-static const struct i915_power_well_desc cnl_power_wells[] = {
-	{
-		.name = "always-on",
-		.always_on = true,
-		.domains = POWER_DOMAIN_MASK,
-		.ops = &i9xx_always_on_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-	},
-	{
-		.name = "power well 1",
-		/* Handled by the DMC firmware */
-		.always_on = true,
-		.domains = 0,
-		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_1,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = SKL_PW_CTL_IDX_PW_1,
-			.hsw.has_fuses = true,
-		},
-	},
-	{
-		.name = "AUX A",
-		.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
-		},
-	},
-	{
-		.name = "AUX B",
-		.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
-		},
-	},
-	{
-		.name = "AUX C",
-		.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
-		},
-	},
-	{
-		.name = "AUX D",
-		.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = CNL_PW_CTL_IDX_AUX_D,
-		},
-	},
-	{
-		.name = "DC off",
-		.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
-		.ops = &gen9_dc_off_power_well_ops,
-		.id = SKL_DISP_DC_OFF,
-	},
-	{
-		.name = "power well 2",
-		.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = SKL_DISP_PW_2,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = SKL_PW_CTL_IDX_PW_2,
-			.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
-			.hsw.has_vga = true,
-			.hsw.has_fuses = true,
-		},
-	},
-	{
-		.name = "DDI A IO power well",
-		.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
-		},
-	},
-	{
-		.name = "DDI B IO power well",
-		.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
-		},
-	},
-	{
-		.name = "DDI C IO power well",
-		.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
-		},
-	},
-	{
-		.name = "DDI D IO power well",
-		.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = SKL_PW_CTL_IDX_DDI_D,
-		},
-	},
-	{
-		.name = "DDI F IO power well",
-		.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = CNL_DISP_PW_DDI_F_IO,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = CNL_PW_CTL_IDX_DDI_F,
-		},
-	},
-	{
-		.name = "AUX F",
-		.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
-		.ops = &hsw_power_well_ops,
-		.id = CNL_DISP_PW_DDI_F_AUX,
-		{
-			.hsw.regs = &hsw_power_well_regs,
-			.hsw.idx = CNL_PW_CTL_IDX_AUX_F,
-		},
-	},
-};
-
 static const struct i915_power_well_ops icl_aux_power_well_ops = {
 	.sync_hw = hsw_power_well_sync_hw,
 	.enable = icl_aux_power_well_enable,
@@ -5147,12 +4937,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 		err = set_power_wells(power_domains, tgl_power_wells);
 	} else if (DISPLAY_VER(dev_priv) == 11) {
 		err = set_power_wells(power_domains, icl_power_wells);
-	} else if (IS_CNL_WITH_PORT_F(dev_priv)) {
-		err = set_power_wells(power_domains, cnl_power_wells);
-	} else if (IS_CANNONLAKE(dev_priv)) {
-		err = set_power_wells_mask(power_domains, cnl_power_wells,
-					   BIT_ULL(CNL_DISP_PW_DDI_F_IO) |
-					   BIT_ULL(CNL_DISP_PW_DDI_F_AUX));
 	} else if (IS_GEMINILAKE(dev_priv)) {
 		err = set_power_wells(power_domains, glk_power_wells);
 	} else if (IS_BROXTON(dev_priv)) {
@@ -5707,75 +5491,6 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 	usleep_range(10, 30);		/* 10 us delay per Bspec */
 }
 
-static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
-{
-	struct i915_power_domains *power_domains = &dev_priv->power_domains;
-	struct i915_power_well *well;
-
-	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
-
-	/* 1. Enable PCH Reset Handshake */
-	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
-
-	if (!HAS_DISPLAY(dev_priv))
-		return;
-
-	/* 2-3. */
-	intel_combo_phy_init(dev_priv);
-
-	/*
-	 * 4. Enable Power Well 1 (PG1).
-	 *    The AUX IO power wells will be enabled on demand.
-	 */
-	mutex_lock(&power_domains->lock);
-	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
-	intel_power_well_enable(dev_priv, well);
-	mutex_unlock(&power_domains->lock);
-
-	/* 5. Enable CD clock */
-	intel_cdclk_init_hw(dev_priv);
-
-	/* 6. Enable DBUF */
-	gen9_dbuf_enable(dev_priv);
-
-	if (resume && intel_dmc_has_payload(dev_priv))
-		intel_dmc_load_program(dev_priv);
-}
-
-static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
-{
-	struct i915_power_domains *power_domains = &dev_priv->power_domains;
-	struct i915_power_well *well;
-
-	if (!HAS_DISPLAY(dev_priv))
-		return;
-
-	gen9_disable_dc_states(dev_priv);
-
-	/* 1. Disable all display engine functions -> aready done */
-
-	/* 2. Disable DBUF */
-	gen9_dbuf_disable(dev_priv);
-
-	/* 3. Disable CD clock */
-	intel_cdclk_uninit_hw(dev_priv);
-
-	/*
-	 * 4. Disable Power Well 1 (PG1).
-	 *    The AUX IO power wells are toggled on demand, so they are already
-	 *    disabled at this point.
-	 */
-	mutex_lock(&power_domains->lock);
-	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
-	intel_power_well_disable(dev_priv, well);
-	mutex_unlock(&power_domains->lock);
-
-	usleep_range(10, 30);		/* 10 us delay per Bspec */
-
-	/* 5. */
-	intel_combo_phy_uninit(dev_priv);
-}
-
 struct buddy_page_mask {
 	u32 page_mask;
 	u8 type;
@@ -6120,8 +5835,6 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
 
 	if (DISPLAY_VER(i915) >= 11) {
 		icl_display_core_init(i915, resume);
-	} else if (IS_CANNONLAKE(i915)) {
-		cnl_display_core_init(i915, resume);
 	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
 		bxt_display_core_init(i915, resume);
 	} else if (DISPLAY_VER(i915) == 9) {
@@ -6281,8 +5994,6 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
 
 	if (DISPLAY_VER(i915) >= 11)
 		icl_display_core_uninit(i915);
-	else if (IS_CANNONLAKE(i915))
-		cnl_display_core_uninit(i915);
 	else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
 		bxt_display_core_uninit(i915);
 	else if (DISPLAY_VER(i915) == 9)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index ad788bbd727d..c79f7ca739d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -142,8 +142,6 @@ enum i915_power_well_id {
 	SKL_DISP_PW_MISC_IO,
 	SKL_DISP_PW_1,
 	SKL_DISP_PW_2,
-	CNL_DISP_PW_DDI_F_IO,
-	CNL_DISP_PW_DDI_F_AUX,
 	ICL_DISP_PW_3,
 	SKL_DISP_DC_OFF,
 	TGL_DISP_PW_TC_COLD_OFF,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65596987b156..91e93f3e9649 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9828,19 +9828,6 @@ enum skl_power_gate {
 	((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
 #define  SKL_FUSE_PG_DIST_STATUS(pg)		(1 << (27 - (pg)))
 
-#define _CNL_AUX_REG_IDX(pw_idx)	((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
-#define _CNL_AUX_ANAOVRD1_B		0x162250
-#define _CNL_AUX_ANAOVRD1_C		0x162210
-#define _CNL_AUX_ANAOVRD1_D		0x1622D0
-#define _CNL_AUX_ANAOVRD1_F		0x162A90
-#define CNL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
-						    _CNL_AUX_ANAOVRD1_B, \
-						    _CNL_AUX_ANAOVRD1_C, \
-						    _CNL_AUX_ANAOVRD1_D, \
-						    _CNL_AUX_ANAOVRD1_F))
-#define   CNL_AUX_ANAOVRD1_ENABLE	(1 << 16)
-#define   CNL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 23)
-
 #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
 #define _ICL_AUX_ANAOVRD1_A		0x162398
 #define _ICL_AUX_ANAOVRD1_B		0x6C398
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 15/30] drm/i915/display: remove explicit CNL handling from intel_display_power.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:10:59PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in intel_display_power.c.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  .../drm/i915/display/intel_display_power.c    | 289 ------------------
>  .../drm/i915/display/intel_display_power.h    |   2 -
>  drivers/gpu/drm/i915/i915_reg.h               |  13 -
>  3 files changed, 304 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 81efc77bada0..44aef0c44ab7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -447,17 +447,6 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
>  
>  	hsw_wait_for_power_well_enable(dev_priv, power_well, false);
>  
> -	/* Display WA #1178: cnl */
> -	if (IS_CANNONLAKE(dev_priv) &&
> -	    pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
> -	    pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
> -		u32 val;
> -
> -		val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
> -		val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
> -		intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
> -	}
> -
>  	if (power_well->desc->hsw.has_fuses) {
>  		enum skl_power_gate pg;
>  
> @@ -2743,63 +2732,6 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
>  	BIT_ULL(POWER_DOMAIN_GMBUS) |			\
>  	BIT_ULL(POWER_DOMAIN_INIT))
>  
> -#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |		\
> -	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> -	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> -	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> -	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> -	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |		\
> -	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |		\
> -	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |		\
> -	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |		\
> -	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |		\
> -	BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |		\
> -	BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
> -	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
> -	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
> -	BIT_ULL(POWER_DOMAIN_AUX_F) |			\
> -	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
> -	BIT_ULL(POWER_DOMAIN_VGA) |				\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) |		\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |		\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |		\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |		\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_A_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> -	BIT_ULL(POWER_DOMAIN_AUX_IO_A) |		\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_B_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_C_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_AUX_C) |			\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_D_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_AUX_D) |			\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_F_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_AUX_F) |			\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS (		\
> -	BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) |		\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> -	CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
> -	BIT_ULL(POWER_DOMAIN_GT_IRQ) |			\
> -	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> -	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> -	BIT_ULL(POWER_DOMAIN_INIT))
> -
>  /*
>   * ICL PW_0/PG_0 domains (HW/DMC control):
>   * - PCI
> @@ -3706,148 +3638,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
>  	},
>  };
>  
> -static const struct i915_power_well_desc cnl_power_wells[] = {
> -	{
> -		.name = "always-on",
> -		.always_on = true,
> -		.domains = POWER_DOMAIN_MASK,
> -		.ops = &i9xx_always_on_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -	},
> -	{
> -		.name = "power well 1",
> -		/* Handled by the DMC firmware */
> -		.always_on = true,
> -		.domains = 0,
> -		.ops = &hsw_power_well_ops,
> -		.id = SKL_DISP_PW_1,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = SKL_PW_CTL_IDX_PW_1,
> -			.hsw.has_fuses = true,
> -		},
> -	},
> -	{
> -		.name = "AUX A",
> -		.domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
> -		},
> -	},
> -	{
> -		.name = "AUX B",
> -		.domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
> -		},
> -	},
> -	{
> -		.name = "AUX C",
> -		.domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
> -		},
> -	},
> -	{
> -		.name = "AUX D",
> -		.domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = CNL_PW_CTL_IDX_AUX_D,
> -		},
> -	},
> -	{
> -		.name = "DC off",
> -		.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
> -		.ops = &gen9_dc_off_power_well_ops,
> -		.id = SKL_DISP_DC_OFF,
> -	},
> -	{
> -		.name = "power well 2",
> -		.domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = SKL_DISP_PW_2,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = SKL_PW_CTL_IDX_PW_2,
> -			.hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> -			.hsw.has_vga = true,
> -			.hsw.has_fuses = true,
> -		},
> -	},
> -	{
> -		.name = "DDI A IO power well",
> -		.domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
> -		},
> -	},
> -	{
> -		.name = "DDI B IO power well",
> -		.domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
> -		},
> -	},
> -	{
> -		.name = "DDI C IO power well",
> -		.domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
> -		},
> -	},
> -	{
> -		.name = "DDI D IO power well",
> -		.domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = DISP_PW_ID_NONE,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = SKL_PW_CTL_IDX_DDI_D,
> -		},
> -	},
> -	{
> -		.name = "DDI F IO power well",
> -		.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = CNL_DISP_PW_DDI_F_IO,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = CNL_PW_CTL_IDX_DDI_F,
> -		},
> -	},
> -	{
> -		.name = "AUX F",
> -		.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
> -		.ops = &hsw_power_well_ops,
> -		.id = CNL_DISP_PW_DDI_F_AUX,
> -		{
> -			.hsw.regs = &hsw_power_well_regs,
> -			.hsw.idx = CNL_PW_CTL_IDX_AUX_F,
> -		},
> -	},
> -};
> -
>  static const struct i915_power_well_ops icl_aux_power_well_ops = {
>  	.sync_hw = hsw_power_well_sync_hw,
>  	.enable = icl_aux_power_well_enable,
> @@ -5147,12 +4937,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
>  		err = set_power_wells(power_domains, tgl_power_wells);
>  	} else if (DISPLAY_VER(dev_priv) == 11) {
>  		err = set_power_wells(power_domains, icl_power_wells);
> -	} else if (IS_CNL_WITH_PORT_F(dev_priv)) {
> -		err = set_power_wells(power_domains, cnl_power_wells);
> -	} else if (IS_CANNONLAKE(dev_priv)) {
> -		err = set_power_wells_mask(power_domains, cnl_power_wells,
> -					   BIT_ULL(CNL_DISP_PW_DDI_F_IO) |
> -					   BIT_ULL(CNL_DISP_PW_DDI_F_AUX));
>  	} else if (IS_GEMINILAKE(dev_priv)) {
>  		err = set_power_wells(power_domains, glk_power_wells);
>  	} else if (IS_BROXTON(dev_priv)) {
> @@ -5707,75 +5491,6 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
>  	usleep_range(10, 30);		/* 10 us delay per Bspec */
>  }
>  
> -static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
> -{
> -	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> -	struct i915_power_well *well;
> -
> -	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> -
> -	/* 1. Enable PCH Reset Handshake */
> -	intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
> -
> -	if (!HAS_DISPLAY(dev_priv))
> -		return;
> -
> -	/* 2-3. */
> -	intel_combo_phy_init(dev_priv);
> -
> -	/*
> -	 * 4. Enable Power Well 1 (PG1).
> -	 *    The AUX IO power wells will be enabled on demand.
> -	 */
> -	mutex_lock(&power_domains->lock);
> -	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> -	intel_power_well_enable(dev_priv, well);
> -	mutex_unlock(&power_domains->lock);
> -
> -	/* 5. Enable CD clock */
> -	intel_cdclk_init_hw(dev_priv);
> -
> -	/* 6. Enable DBUF */
> -	gen9_dbuf_enable(dev_priv);
> -
> -	if (resume && intel_dmc_has_payload(dev_priv))
> -		intel_dmc_load_program(dev_priv);
> -}
> -
> -static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> -{
> -	struct i915_power_domains *power_domains = &dev_priv->power_domains;
> -	struct i915_power_well *well;
> -
> -	if (!HAS_DISPLAY(dev_priv))
> -		return;
> -
> -	gen9_disable_dc_states(dev_priv);
> -
> -	/* 1. Disable all display engine functions -> aready done */
> -
> -	/* 2. Disable DBUF */
> -	gen9_dbuf_disable(dev_priv);
> -
> -	/* 3. Disable CD clock */
> -	intel_cdclk_uninit_hw(dev_priv);
> -
> -	/*
> -	 * 4. Disable Power Well 1 (PG1).
> -	 *    The AUX IO power wells are toggled on demand, so they are already
> -	 *    disabled at this point.
> -	 */
> -	mutex_lock(&power_domains->lock);
> -	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
> -	intel_power_well_disable(dev_priv, well);
> -	mutex_unlock(&power_domains->lock);
> -
> -	usleep_range(10, 30);		/* 10 us delay per Bspec */
> -
> -	/* 5. */
> -	intel_combo_phy_uninit(dev_priv);
> -}
> -
>  struct buddy_page_mask {
>  	u32 page_mask;
>  	u8 type;
> @@ -6120,8 +5835,6 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
>  
>  	if (DISPLAY_VER(i915) >= 11) {
>  		icl_display_core_init(i915, resume);
> -	} else if (IS_CANNONLAKE(i915)) {
> -		cnl_display_core_init(i915, resume);
>  	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
>  		bxt_display_core_init(i915, resume);
>  	} else if (DISPLAY_VER(i915) == 9) {
> @@ -6281,8 +5994,6 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
>  
>  	if (DISPLAY_VER(i915) >= 11)
>  		icl_display_core_uninit(i915);
> -	else if (IS_CANNONLAKE(i915))
> -		cnl_display_core_uninit(i915);
>  	else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
>  		bxt_display_core_uninit(i915);
>  	else if (DISPLAY_VER(i915) == 9)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index ad788bbd727d..c79f7ca739d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -142,8 +142,6 @@ enum i915_power_well_id {
>  	SKL_DISP_PW_MISC_IO,
>  	SKL_DISP_PW_1,
>  	SKL_DISP_PW_2,
> -	CNL_DISP_PW_DDI_F_IO,
> -	CNL_DISP_PW_DDI_F_AUX,
>  	ICL_DISP_PW_3,
>  	SKL_DISP_DC_OFF,
>  	TGL_DISP_PW_TC_COLD_OFF,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 65596987b156..91e93f3e9649 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9828,19 +9828,6 @@ enum skl_power_gate {
>  	((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
>  #define  SKL_FUSE_PG_DIST_STATUS(pg)		(1 << (27 - (pg)))
>  
> -#define _CNL_AUX_REG_IDX(pw_idx)	((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
> -#define _CNL_AUX_ANAOVRD1_B		0x162250
> -#define _CNL_AUX_ANAOVRD1_C		0x162210
> -#define _CNL_AUX_ANAOVRD1_D		0x1622D0
> -#define _CNL_AUX_ANAOVRD1_F		0x162A90
> -#define CNL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \
> -						    _CNL_AUX_ANAOVRD1_B, \
> -						    _CNL_AUX_ANAOVRD1_C, \
> -						    _CNL_AUX_ANAOVRD1_D, \
> -						    _CNL_AUX_ANAOVRD1_F))
> -#define   CNL_AUX_ANAOVRD1_ENABLE	(1 << 16)
> -#define   CNL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 23)
> -
>  #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
>  #define _ICL_AUX_ANAOVRD1_A		0x162398
>  #define _ICL_AUX_ANAOVRD1_B		0x6C398
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 16/30] drm/i915/display: remove CNL ddi buf translation tables

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  12 +-
 .../drm/i915/display/intel_ddi_buf_trans.c    | 616 +++++-------------
 .../drm/i915/display/intel_ddi_buf_trans.h    |   4 +-
 3 files changed, 184 insertions(+), 448 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8367462842fa..e5cfb606dd30 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1055,8 +1055,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
 	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 		 RCOMP_SCALAR_MASK);
-	val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
-	val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
+	val |= SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel);
+	val |= SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel);
 	/* Program Rcomp scalar for every table entry */
 	val |= RCOMP_SCALAR(0x98);
 	intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
@@ -1067,16 +1067,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
 		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 			 CURSOR_COEFF_MASK);
-		val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
-		val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
-		val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
+		val |= POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1);
+		val |= POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2);
+		val |= CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff);
 		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
 	}
 
 	/* Program PORT_TX_DW7 */
 	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
 	val &= ~N_SCALAR_MASK;
-	val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
+	val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar);
 	intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 63b1ae830d9a..9ab95bcd0c86 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -417,199 +417,19 @@ static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = {
 	.hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1,
 };
 
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_85V[] = {
-							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } },	/* 350   500      3.1   */
-	{ .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
-	{ .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } },	/* 650   725      0.9   */
-	{ .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_85V = {
-	.entries = _cnl_ddi_translations_dp_0_85V,
-	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_85V),
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for HDMI */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_85V[] = {
-							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
-	{ .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } },	/* 450   650      3.2   */
-	{ .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 450   850      5.5   */
-	{ .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } },	/* 650   650      0.0   */
-	{ .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 650   850      2.3   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 850   850      0.0   */
-	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V = {
-	.entries = _cnl_ddi_translations_hdmi_0_85V,
-	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V),
-	.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V) - 1,
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_0_85V[] = {
-							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x66, 0x3A, 0x00, 0x05 } },	/* 384   500      2.3   */
-	{ .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } },	/* 153   200      2.3   */
-	{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 192   250      2.3   */
-	{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 230   300      2.3   */
-	{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 269   350      2.3   */
-	{ .cnl = { 0xA, 0x66, 0x3C, 0x00, 0x03 } },	/* 446   500      1.0   */
-	{ .cnl = { 0xB, 0x70, 0x3C, 0x00, 0x03 } },	/* 460   600      2.3   */
-	{ .cnl = { 0xC, 0x75, 0x3C, 0x00, 0x03 } },	/* 537   700      2.3   */
-	{ .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_0_85V = {
-	.entries = _cnl_ddi_translations_edp_0_85V,
-	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_0_85V),
-};
-
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_95V[] = {
-							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } },	/* 350   500      3.1   */
-	{ .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
-	{ .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } },	/* 650   725      0.9   */
-	{ .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_95V = {
-	.entries = _cnl_ddi_translations_dp_0_95V,
-	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_95V),
-};
-
-/* Voltage Swing Programming for VccIO 0.95V for HDMI */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_95V[] = {
-							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
-	{ .cnl = { 0xB, 0x69, 0x37, 0x00, 0x08 } },	/* 400   600      3.5   */
-	{ .cnl = { 0x5, 0x76, 0x31, 0x00, 0x0E } },	/* 400   800      6.0   */
-	{ .cnl = { 0xA, 0x5E, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
-	{ .cnl = { 0xB, 0x69, 0x3F, 0x00, 0x00 } },	/* 600   600      0.0   */
-	{ .cnl = { 0xB, 0x79, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
-	{ .cnl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } },	/* 600   1000     4.4   */
-	{ .cnl = { 0x5, 0x76, 0x3F, 0x00, 0x00 } },	/* 800   800      0.0   */
-	{ .cnl = { 0x6, 0x7D, 0x39, 0x00, 0x06 } },	/* 800   1000     1.9   */
-	{ .cnl = { 0x6, 0x7F, 0x39, 0x00, 0x06 } },	/* 850   1050     1.8   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1050  1050     0.0   */
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V = {
-	.entries = _cnl_ddi_translations_hdmi_0_95V,
-	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V),
-	.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V) - 1,
-};
-
-/* Voltage Swing Programming for VccIO 0.95V for eDP */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_0_95V[] = {
-							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x61, 0x3A, 0x00, 0x05 } },	/* 384   500      2.3   */
-	{ .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } },	/* 153   200      2.3   */
-	{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 192   250      2.3   */
-	{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 230   300      2.3   */
-	{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 269   350      2.3   */
-	{ .cnl = { 0xA, 0x61, 0x3C, 0x00, 0x03 } },	/* 446   500      1.0   */
-	{ .cnl = { 0xB, 0x68, 0x39, 0x00, 0x06 } },	/* 460   600      2.3   */
-	{ .cnl = { 0xC, 0x6E, 0x39, 0x00, 0x06 } },	/* 537   700      2.3   */
-	{ .cnl = { 0x4, 0x7F, 0x3A, 0x00, 0x05 } },	/* 460   600      2.3   */
-	{ .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_0_95V = {
-	.entries = _cnl_ddi_translations_edp_0_95V,
-	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_0_95V),
-};
-
-/* Voltage Swing Programming for VccIO 1.05V for DP */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_1_05V[] = {
-							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
-	{ .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } },	/* 400   600      3.5   */
-	{ .cnl = { 0x5, 0x70, 0x31, 0x00, 0x0E } },	/* 400   800      6.0   */
-	{ .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 400   1050     8.4   */
-	{ .cnl = { 0xB, 0x64, 0x3F, 0x00, 0x00 } },	/* 600   600      0.0   */
-	{ .cnl = { 0x5, 0x73, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
-	{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 550   1050     5.6   */
-	{ .cnl = { 0x5, 0x76, 0x3E, 0x00, 0x01 } },	/* 850   900      0.5   */
-	{ .cnl = { 0x6, 0x7F, 0x36, 0x00, 0x09 } },	/* 750   1050     2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1050  1050     0.0   */
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_1_05V = {
-	.entries = _cnl_ddi_translations_dp_1_05V,
-	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_1_05V),
-};
-
-/* Voltage Swing Programming for VccIO 1.05V for HDMI */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_1_05V[] = {
-							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
-	{ .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } },	/* 400   600      3.5   */
-	{ .cnl = { 0x5, 0x70, 0x31, 0x00, 0x0E } },	/* 400   800      6.0   */
-	{ .cnl = { 0xA, 0x5B, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
-	{ .cnl = { 0xB, 0x64, 0x3F, 0x00, 0x00 } },	/* 600   600      0.0   */
-	{ .cnl = { 0x5, 0x73, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
-	{ .cnl = { 0x6, 0x7C, 0x32, 0x00, 0x0D } },	/* 600   1000     4.4   */
-	{ .cnl = { 0x5, 0x70, 0x3F, 0x00, 0x00 } },	/* 800   800      0.0   */
-	{ .cnl = { 0x6, 0x7C, 0x39, 0x00, 0x06 } },	/* 800   1000     1.9   */
-	{ .cnl = { 0x6, 0x7F, 0x39, 0x00, 0x06 } },	/* 850   1050     1.8   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1050  1050     0.0   */
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V = {
-	.entries = _cnl_ddi_translations_hdmi_1_05V,
-	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V),
-	.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V) - 1,
-};
-
-/* Voltage Swing Programming for VccIO 1.05V for eDP */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_1_05V[] = {
-							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x5E, 0x3A, 0x00, 0x05 } },	/* 384   500      2.3   */
-	{ .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } },	/* 153   200      2.3   */
-	{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 192   250      2.3   */
-	{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 230   300      2.3   */
-	{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 269   350      2.3   */
-	{ .cnl = { 0xA, 0x5E, 0x3C, 0x00, 0x03 } },	/* 446   500      1.0   */
-	{ .cnl = { 0xB, 0x64, 0x39, 0x00, 0x06 } },	/* 460   600      2.3   */
-	{ .cnl = { 0xE, 0x6A, 0x39, 0x00, 0x06 } },	/* 537   700      2.3   */
-	{ .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_1_05V = {
-	.entries = _cnl_ddi_translations_edp_1_05V,
-	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_1_05V),
-};
-
 /* icl_combo_phy_ddi_translations */
 static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
-	{ .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
+	{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
+	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3 = {
@@ -619,16 +439,16 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_e
 
 static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
-	{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 200   250      1.9   */
-	{ .cnl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },	/* 200   300      3.5   */
-	{ .cnl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } },	/* 200   350      4.9   */
-	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
-	{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
-	{ .cnl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } },	/* 250   350      2.9   */
-	{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
-	{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
-	{ .cnl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
+	{ .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 200   250      1.9   */
+	{ .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },	/* 200   300      3.5   */
+	{ .icl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } },	/* 200   350      4.9   */
+	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
+	{ .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
+	{ .icl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } },	/* 250   350      2.9   */
+	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
+	{ .icl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
+	{ .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
 };
 
 static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2 = {
@@ -638,13 +458,13 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2
 
 static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
-	{ .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } },	/* 450   650      3.2   */
-	{ .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 450   850      5.5   */
-	{ .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } },	/* 650   650      0.0   ALS */
-	{ .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 650   850      2.3   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 850   850      0.0   */
-	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
+	{ .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
+	{ .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } },	/* 450   650      3.2   */
+	{ .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 450   850      5.5   */
+	{ .icl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } },	/* 650   650      0.0   ALS */
+	{ .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 650   850      2.3   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 850   850      0.0   */
+	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
 };
 
 static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = {
@@ -655,16 +475,16 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = {
 
 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x47, 0x36, 0x00, 0x09 } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x64, 0x34, 0x00, 0x0B } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x64, 0x38, 0x00, 0x07 } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
-	{ .cnl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x47, 0x36, 0x00, 0x09 } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x64, 0x34, 0x00, 0x0B } },	/* 350   700      6.0   */
+	{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 350   900      8.2   */
+	{ .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x64, 0x38, 0x00, 0x07 } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = {
@@ -674,16 +494,16 @@ static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = {
 
 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp_hbr2[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
-	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   250      1.9   */
-	{ .cnl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },	/* 200   300      3.5   */
-	{ .cnl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },	/* 200   350      4.9   */
-	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
-	{ .cnl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } },	/* 250   300      1.6   */
-	{ .cnl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },	/* 250   350      2.9   */
-	{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
-	{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
-	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
+	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   250      1.9   */
+	{ .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },	/* 200   300      3.5   */
+	{ .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },	/* 200   350      4.9   */
+	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
+	{ .icl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } },	/* 250   300      1.6   */
+	{ .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },	/* 250   350      2.9   */
+	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
+	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
+	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
 };
 
 static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2 = {
@@ -693,16 +513,16 @@ static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2
 
 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
-	{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 200   250      1.9   */
-	{ .cnl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },	/* 200   300      3.5   */
-	{ .cnl = { 0xA, 0x35, 0x36, 0x00, 0x09 } },	/* 200   350      4.9   */
-	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
-	{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
-	{ .cnl = { 0xA, 0x35, 0x35, 0x00, 0x0A } },	/* 250   350      2.9   */
-	{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
-	{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
-	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
+	{ .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 200   250      1.9   */
+	{ .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },	/* 200   300      3.5   */
+	{ .icl = { 0xA, 0x35, 0x36, 0x00, 0x09 } },	/* 200   350      4.9   */
+	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
+	{ .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
+	{ .icl = { 0xA, 0x35, 0x35, 0x00, 0x0A } },	/* 250   350      2.9   */
+	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
+	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
+	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
 };
 
 static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr = {
@@ -712,16 +532,16 @@ static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr =
 
 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr2[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
-	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   250      1.9   */
-	{ .cnl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },	/* 200   300      3.5   */
-	{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 200   350      4.9   */
-	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
-	{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   300      1.6   */
-	{ .cnl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } },	/* 250   350      2.9   */
-	{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
-	{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
-	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
+	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   250      1.9   */
+	{ .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },	/* 200   300      3.5   */
+	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 200   350      4.9   */
+	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
+	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   300      1.6   */
+	{ .icl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } },	/* 250   350      2.9   */
+	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
+	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
+	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
 };
 
 static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2 = {
@@ -731,16 +551,16 @@ static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2
 
 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
-	{ .cnl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
+	{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
+	{ .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr = {
@@ -750,16 +570,16 @@ static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hb
 
 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
-	{ .cnl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
+	{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
+	{ .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
@@ -885,16 +705,16 @@ static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = {
 
 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
-	{ .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
+	{ .icl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
+	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr = {
@@ -904,16 +724,16 @@ static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr =
 
 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr2[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x63, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
-	{ .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
+	{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
+	{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x63, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 = {
@@ -923,16 +743,16 @@ static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 =
 
 static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x60, 0x32, 0x00, 0x0D } },	/* 350   700      6.0   */
-	{ .cnl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
-	{ .cnl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x60, 0x32, 0x00, 0x0D } },	/* 350   700      6.0   */
+	{ .icl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } },	/* 350   900      8.2   */
+	{ .icl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
+	{ .icl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2 = {
@@ -946,15 +766,15 @@ static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr
  */
 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
 							/* VS	pre-emp	*/
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	0	*/
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	1	*/
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	2	*/
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	3	*/
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	0	*/
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	1	*/
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	2	*/
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 2	0	*/
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 2	1	*/
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	0	*/
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	1	*/
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	2	*/
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	3	*/
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	0	*/
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	1	*/
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	2	*/
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 2	0	*/
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 2	1	*/
 };
 
 static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl = {
@@ -964,16 +784,16 @@ static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_
 
 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
-	{ .cnl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
+	{ .icl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } },	/* 350   900      8.2   */
+	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr = {
@@ -983,16 +803,16 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr =
 
 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x50, 0x38, 0x00, 0x07 } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x61, 0x33, 0x00, 0x0C } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
-	{ .cnl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x61, 0x33, 0x00, 0x0C } },	/* 350   700      6.0   */
+	{ .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },	/* 350   900      8.2   */
+	{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
@@ -1002,16 +822,16 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_h
 
 static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x63, 0x30, 0x00, 0x0F } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 500   900      5.1   */
-	{ .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x63, 0x30, 0x00, 0x0F } },	/* 350   700      6.0   */
+	{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
+	{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
@@ -1021,16 +841,16 @@ static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_
 
 static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } },	/* 200   200      0.0   */
-	{ .cnl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } },	/* 200   250      1.9   */
-	{ .cnl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } },	/* 200   300      3.5   */
-	{ .cnl = { 0x4, 0x59, 0x32, 0x00, 0x0D } },	/* 200   350      4.9   */
-	{ .cnl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } },	/* 250   250      0.0   */
-	{ .cnl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
-	{ .cnl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } },	/* 250   350      2.9   */
-	{ .cnl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } },	/* 300   300      0.0   */
-	{ .cnl = { 0x4, 0x65, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
-	{ .cnl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } },	/* 350   350      0.0   */
+	{ .icl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } },	/* 200   200      0.0   */
+	{ .icl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } },	/* 200   250      1.9   */
+	{ .icl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } },	/* 200   300      3.5   */
+	{ .icl = { 0x4, 0x59, 0x32, 0x00, 0x0D } },	/* 200   350      4.9   */
+	{ .icl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } },	/* 250   250      0.0   */
+	{ .icl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
+	{ .icl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } },	/* 250   350      2.9   */
+	{ .icl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } },	/* 300   300      0.0   */
+	{ .icl = { 0x4, 0x65, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
+	{ .icl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } },	/* 350   350      0.0   */
 };
 
 static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = {
@@ -1040,16 +860,16 @@ static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2
 
 static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = {
 							/* NT mV Trans mV db    */
-	{ .cnl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } },	/* 350   350      0.0   */
-	{ .cnl = { 0xA, 0x69, 0x32, 0x00, 0x0D } },	/* 350   500      3.1   */
-	{ .cnl = { 0xC, 0x74, 0x31, 0x00, 0x0E } },	/* 350   700      6.0   */
-	{ .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },	/* 350   900      8.2   */
-	{ .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
-	{ .cnl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
-	{ .cnl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } },	/* 500   900      5.1   */
-	{ .cnl = { 0xC, 0x7F, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
-	{ .cnl = { 0x6, 0x7F, 0x3C, 0x00, 0x03 } },	/* 600   900      3.5   */
-	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
+	{ .icl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } },	/* 350   350      0.0   */
+	{ .icl = { 0xA, 0x69, 0x32, 0x00, 0x0D } },	/* 350   500      3.1   */
+	{ .icl = { 0xC, 0x74, 0x31, 0x00, 0x0E } },	/* 350   700      6.0   */
+	{ .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },	/* 350   900      8.2   */
+	{ .icl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
+	{ .icl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
+	{ .icl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } },	/* 500   900      5.1   */
+	{ .icl = { 0xC, 0x7F, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
+	{ .icl = { 0x6, 0x7F, 0x3C, 0x00, 0x03 } },	/* 600   900      3.5   */
+	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
 };
 
 static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = {
@@ -1269,88 +1089,6 @@ bxt_get_buf_trans(struct intel_encoder *encoder,
 		return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries);
 }
 
-static const struct intel_ddi_buf_trans *
-cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-
-	if (voltage == VOLTAGE_INFO_0_85V) {
-		return intel_get_buf_trans(&cnl_ddi_translations_hdmi_0_85V,
-					   n_entries);
-	} else if (voltage == VOLTAGE_INFO_0_95V) {
-		return intel_get_buf_trans(&cnl_ddi_translations_hdmi_0_95V,
-					   n_entries);
-	} else if (voltage == VOLTAGE_INFO_1_05V) {
-		return intel_get_buf_trans(&cnl_ddi_translations_hdmi_1_05V,
-					   n_entries);
-	} else {
-		*n_entries = 1; /* shut up gcc */
-		MISSING_CASE(voltage);
-	}
-	return NULL;
-}
-
-static const struct intel_ddi_buf_trans *
-cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-
-	if (voltage == VOLTAGE_INFO_0_85V) {
-		return intel_get_buf_trans(&cnl_ddi_translations_dp_0_85V,
-					   n_entries);
-	} else if (voltage == VOLTAGE_INFO_0_95V) {
-		return intel_get_buf_trans(&cnl_ddi_translations_dp_0_95V,
-					   n_entries);
-	} else if (voltage == VOLTAGE_INFO_1_05V) {
-		return intel_get_buf_trans(&cnl_ddi_translations_dp_1_05V,
-					   n_entries);
-	} else {
-		*n_entries = 1; /* shut up gcc */
-		MISSING_CASE(voltage);
-	}
-	return NULL;
-}
-
-static const struct intel_ddi_buf_trans *
-cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
-
-	if (dev_priv->vbt.edp.low_vswing) {
-		if (voltage == VOLTAGE_INFO_0_85V) {
-			return intel_get_buf_trans(&cnl_ddi_translations_edp_0_85V,
-						   n_entries);
-		} else if (voltage == VOLTAGE_INFO_0_95V) {
-			return intel_get_buf_trans(&cnl_ddi_translations_edp_0_95V,
-						   n_entries);
-		} else if (voltage == VOLTAGE_INFO_1_05V) {
-			return intel_get_buf_trans(&cnl_ddi_translations_edp_1_05V,
-						   n_entries);
-		} else {
-			*n_entries = 1; /* shut up gcc */
-			MISSING_CASE(voltage);
-		}
-		return NULL;
-	} else {
-		return cnl_get_buf_trans_dp(encoder, n_entries);
-	}
-}
-
-static const struct intel_ddi_buf_trans *
-cnl_get_buf_trans(struct intel_encoder *encoder,
-		  const struct intel_crtc_state *crtc_state,
-		  int *n_entries)
-{
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-		return cnl_get_buf_trans_hdmi(encoder, n_entries);
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
-		return cnl_get_buf_trans_edp(encoder, n_entries);
-	return cnl_get_buf_trans_dp(encoder, n_entries);
-}
-
 static const struct intel_ddi_buf_trans *
 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
 			   const struct intel_crtc_state *crtc_state,
@@ -1761,8 +1499,6 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
 			encoder->get_buf_trans = icl_get_combo_buf_trans;
 		else
 			encoder->get_buf_trans = icl_get_mg_buf_trans;
-	} else if (IS_CANNONLAKE(i915)) {
-		encoder->get_buf_trans = cnl_get_buf_trans;
 	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
 		encoder->get_buf_trans = bxt_get_buf_trans;
 	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index 05226eb46cd6..2acd720f9d4f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -25,7 +25,7 @@ struct bxt_ddi_buf_trans {
 	u8 deemphasis;
 };
 
-struct cnl_ddi_buf_trans {
+struct icl_ddi_buf_trans {
 	u8 dw2_swing_sel;
 	u8 dw7_n_scalar;
 	u8 dw4_cursor_coeff;
@@ -48,7 +48,7 @@ struct tgl_dkl_phy_ddi_buf_trans {
 union intel_ddi_buf_trans_entry {
 	struct hsw_ddi_buf_trans hsw;
 	struct bxt_ddi_buf_trans bxt;
-	struct cnl_ddi_buf_trans cnl;
+	struct icl_ddi_buf_trans icl;
 	struct icl_mg_phy_ddi_buf_trans mg;
 	struct tgl_dkl_phy_ddi_buf_trans dkl;
 };
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 16/30] drm/i915/display: remove CNL ddi buf translation tables

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:00PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  12 +-
>  .../drm/i915/display/intel_ddi_buf_trans.c    | 616 +++++-------------
>  .../drm/i915/display/intel_ddi_buf_trans.h    |   4 +-
>  3 files changed, 184 insertions(+), 448 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8367462842fa..e5cfb606dd30 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1055,8 +1055,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
>  	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>  		 RCOMP_SCALAR_MASK);
> -	val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
> -	val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
> +	val |= SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel);
> +	val |= SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel);
>  	/* Program Rcomp scalar for every table entry */
>  	val |= RCOMP_SCALAR(0x98);
>  	intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
> @@ -1067,16 +1067,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
>  		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
>  			 CURSOR_COEFF_MASK);
> -		val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
> -		val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
> -		val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
> +		val |= POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1);
> +		val |= POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2);
> +		val |= CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff);
>  		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
>  	}
>  
>  	/* Program PORT_TX_DW7 */
>  	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
>  	val &= ~N_SCALAR_MASK;
> -	val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
> +	val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar);
>  	intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 63b1ae830d9a..9ab95bcd0c86 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -417,199 +417,19 @@ static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = {
>  	.hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1,
>  };
>  
> -/* Voltage Swing Programming for VccIO 0.85V for DP */
> -static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_85V[] = {
> -							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } },	/* 650   725      0.9   */
> -	{ .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> -};
> -
> -static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_85V = {
> -	.entries = _cnl_ddi_translations_dp_0_85V,
> -	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_85V),
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.85V for HDMI */
> -static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_85V[] = {
> -							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
> -	{ .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } },	/* 450   650      3.2   */
> -	{ .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 450   850      5.5   */
> -	{ .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } },	/* 650   650      0.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 650   850      2.3   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 850   850      0.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
> -};
> -
> -static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V = {
> -	.entries = _cnl_ddi_translations_hdmi_0_85V,
> -	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V),
> -	.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V) - 1,
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.85V for eDP */
> -static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_0_85V[] = {
> -							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x66, 0x3A, 0x00, 0x05 } },	/* 384   500      2.3   */
> -	{ .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } },	/* 153   200      2.3   */
> -	{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 192   250      2.3   */
> -	{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 230   300      2.3   */
> -	{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 269   350      2.3   */
> -	{ .cnl = { 0xA, 0x66, 0x3C, 0x00, 0x03 } },	/* 446   500      1.0   */
> -	{ .cnl = { 0xB, 0x70, 0x3C, 0x00, 0x03 } },	/* 460   600      2.3   */
> -	{ .cnl = { 0xC, 0x75, 0x3C, 0x00, 0x03 } },	/* 537   700      2.3   */
> -	{ .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
> -};
> -
> -static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_0_85V = {
> -	.entries = _cnl_ddi_translations_edp_0_85V,
> -	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_0_85V),
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.95V for DP */
> -static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_95V[] = {
> -							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } },	/* 650   725      0.9   */
> -	{ .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> -};
> -
> -static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_95V = {
> -	.entries = _cnl_ddi_translations_dp_0_95V,
> -	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_95V),
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.95V for HDMI */
> -static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_95V[] = {
> -							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
> -	{ .cnl = { 0xB, 0x69, 0x37, 0x00, 0x08 } },	/* 400   600      3.5   */
> -	{ .cnl = { 0x5, 0x76, 0x31, 0x00, 0x0E } },	/* 400   800      6.0   */
> -	{ .cnl = { 0xA, 0x5E, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
> -	{ .cnl = { 0xB, 0x69, 0x3F, 0x00, 0x00 } },	/* 600   600      0.0   */
> -	{ .cnl = { 0xB, 0x79, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
> -	{ .cnl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } },	/* 600   1000     4.4   */
> -	{ .cnl = { 0x5, 0x76, 0x3F, 0x00, 0x00 } },	/* 800   800      0.0   */
> -	{ .cnl = { 0x6, 0x7D, 0x39, 0x00, 0x06 } },	/* 800   1000     1.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x39, 0x00, 0x06 } },	/* 850   1050     1.8   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1050  1050     0.0   */
> -};
> -
> -static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V = {
> -	.entries = _cnl_ddi_translations_hdmi_0_95V,
> -	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V),
> -	.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V) - 1,
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.95V for eDP */
> -static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_0_95V[] = {
> -							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x61, 0x3A, 0x00, 0x05 } },	/* 384   500      2.3   */
> -	{ .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } },	/* 153   200      2.3   */
> -	{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 192   250      2.3   */
> -	{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 230   300      2.3   */
> -	{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 269   350      2.3   */
> -	{ .cnl = { 0xA, 0x61, 0x3C, 0x00, 0x03 } },	/* 446   500      1.0   */
> -	{ .cnl = { 0xB, 0x68, 0x39, 0x00, 0x06 } },	/* 460   600      2.3   */
> -	{ .cnl = { 0xC, 0x6E, 0x39, 0x00, 0x06 } },	/* 537   700      2.3   */
> -	{ .cnl = { 0x4, 0x7F, 0x3A, 0x00, 0x05 } },	/* 460   600      2.3   */
> -	{ .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
> -};
> -
> -static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_0_95V = {
> -	.entries = _cnl_ddi_translations_edp_0_95V,
> -	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_0_95V),
> -};
> -
> -/* Voltage Swing Programming for VccIO 1.05V for DP */
> -static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_1_05V[] = {
> -							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
> -	{ .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } },	/* 400   600      3.5   */
> -	{ .cnl = { 0x5, 0x70, 0x31, 0x00, 0x0E } },	/* 400   800      6.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 400   1050     8.4   */
> -	{ .cnl = { 0xB, 0x64, 0x3F, 0x00, 0x00 } },	/* 600   600      0.0   */
> -	{ .cnl = { 0x5, 0x73, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 550   1050     5.6   */
> -	{ .cnl = { 0x5, 0x76, 0x3E, 0x00, 0x01 } },	/* 850   900      0.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x36, 0x00, 0x09 } },	/* 750   1050     2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1050  1050     0.0   */
> -};
> -
> -static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_1_05V = {
> -	.entries = _cnl_ddi_translations_dp_1_05V,
> -	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_1_05V),
> -};
> -
> -/* Voltage Swing Programming for VccIO 1.05V for HDMI */
> -static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_1_05V[] = {
> -							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
> -	{ .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } },	/* 400   600      3.5   */
> -	{ .cnl = { 0x5, 0x70, 0x31, 0x00, 0x0E } },	/* 400   800      6.0   */
> -	{ .cnl = { 0xA, 0x5B, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
> -	{ .cnl = { 0xB, 0x64, 0x3F, 0x00, 0x00 } },	/* 600   600      0.0   */
> -	{ .cnl = { 0x5, 0x73, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
> -	{ .cnl = { 0x6, 0x7C, 0x32, 0x00, 0x0D } },	/* 600   1000     4.4   */
> -	{ .cnl = { 0x5, 0x70, 0x3F, 0x00, 0x00 } },	/* 800   800      0.0   */
> -	{ .cnl = { 0x6, 0x7C, 0x39, 0x00, 0x06 } },	/* 800   1000     1.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x39, 0x00, 0x06 } },	/* 850   1050     1.8   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1050  1050     0.0   */
> -};
> -
> -static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V = {
> -	.entries = _cnl_ddi_translations_hdmi_1_05V,
> -	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V),
> -	.hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V) - 1,
> -};
> -
> -/* Voltage Swing Programming for VccIO 1.05V for eDP */
> -static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_1_05V[] = {
> -							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x5E, 0x3A, 0x00, 0x05 } },	/* 384   500      2.3   */
> -	{ .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } },	/* 153   200      2.3   */
> -	{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 192   250      2.3   */
> -	{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 230   300      2.3   */
> -	{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 269   350      2.3   */
> -	{ .cnl = { 0xA, 0x5E, 0x3C, 0x00, 0x03 } },	/* 446   500      1.0   */
> -	{ .cnl = { 0xB, 0x64, 0x39, 0x00, 0x06 } },	/* 460   600      2.3   */
> -	{ .cnl = { 0xE, 0x6A, 0x39, 0x00, 0x06 } },	/* 537   700      2.3   */
> -	{ .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } },	/* 400   400      0.0   */
> -};
> -
> -static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_1_05V = {
> -	.entries = _cnl_ddi_translations_edp_1_05V,
> -	.num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_1_05V),
> -};
> -
>  /* icl_combo_phy_ddi_translations */
>  static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> +	{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
> +	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
> +	{ .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3 = {
> @@ -619,16 +439,16 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_e
>  
>  static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
> -	{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 200   250      1.9   */
> -	{ .cnl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },	/* 200   300      3.5   */
> -	{ .cnl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } },	/* 200   350      4.9   */
> -	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
> -	{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
> -	{ .cnl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } },	/* 250   350      2.9   */
> -	{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
> -	{ .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
> -	{ .cnl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
> +	{ .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 200   250      1.9   */
> +	{ .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },	/* 200   300      3.5   */
> +	{ .icl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } },	/* 200   350      4.9   */
> +	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
> +	{ .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
> +	{ .icl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } },	/* 250   350      2.9   */
> +	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
> +	{ .icl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
> +	{ .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2 = {
> @@ -638,13 +458,13 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2
>  
>  static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
> -	{ .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } },	/* 450   650      3.2   */
> -	{ .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 450   850      5.5   */
> -	{ .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } },	/* 650   650      0.0   ALS */
> -	{ .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 650   850      2.3   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 850   850      0.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
> +	{ .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
> +	{ .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } },	/* 450   650      3.2   */
> +	{ .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 450   850      5.5   */
> +	{ .icl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } },	/* 650   650      0.0   ALS */
> +	{ .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 650   850      2.3   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 850   850      0.0   */
> +	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = {
> @@ -655,16 +475,16 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = {
>  
>  static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x47, 0x36, 0x00, 0x09 } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x64, 0x34, 0x00, 0x0B } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x64, 0x38, 0x00, 0x07 } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x47, 0x36, 0x00, 0x09 } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x64, 0x34, 0x00, 0x0B } },	/* 350   700      6.0   */
> +	{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 350   900      8.2   */
> +	{ .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x64, 0x38, 0x00, 0x07 } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
> +	{ .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = {
> @@ -674,16 +494,16 @@ static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = {
>  
>  static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp_hbr2[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
> -	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   250      1.9   */
> -	{ .cnl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },	/* 200   300      3.5   */
> -	{ .cnl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },	/* 200   350      4.9   */
> -	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
> -	{ .cnl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } },	/* 250   300      1.6   */
> -	{ .cnl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },	/* 250   350      2.9   */
> -	{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
> -	{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
> -	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
> +	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   250      1.9   */
> +	{ .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },	/* 200   300      3.5   */
> +	{ .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },	/* 200   350      4.9   */
> +	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
> +	{ .icl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } },	/* 250   300      1.6   */
> +	{ .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },	/* 250   350      2.9   */
> +	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
> +	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
> +	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2 = {
> @@ -693,16 +513,16 @@ static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2
>  
>  static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
> -	{ .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 200   250      1.9   */
> -	{ .cnl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },	/* 200   300      3.5   */
> -	{ .cnl = { 0xA, 0x35, 0x36, 0x00, 0x09 } },	/* 200   350      4.9   */
> -	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
> -	{ .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
> -	{ .cnl = { 0xA, 0x35, 0x35, 0x00, 0x0A } },	/* 250   350      2.9   */
> -	{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
> -	{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
> -	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
> +	{ .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 200   250      1.9   */
> +	{ .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },	/* 200   300      3.5   */
> +	{ .icl = { 0xA, 0x35, 0x36, 0x00, 0x09 } },	/* 200   350      4.9   */
> +	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
> +	{ .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
> +	{ .icl = { 0xA, 0x35, 0x35, 0x00, 0x0A } },	/* 250   350      2.9   */
> +	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
> +	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
> +	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr = {
> @@ -712,16 +532,16 @@ static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr =
>  
>  static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr2[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
> -	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   250      1.9   */
> -	{ .cnl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },	/* 200   300      3.5   */
> -	{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 200   350      4.9   */
> -	{ .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
> -	{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   300      1.6   */
> -	{ .cnl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } },	/* 250   350      2.9   */
> -	{ .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
> -	{ .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
> -	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
> +	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   250      1.9   */
> +	{ .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },	/* 200   300      3.5   */
> +	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 200   350      4.9   */
> +	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
> +	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   300      1.6   */
> +	{ .icl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } },	/* 250   350      2.9   */
> +	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
> +	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
> +	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2 = {
> @@ -731,16 +551,16 @@ static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2
>  
>  static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> +	{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
> +	{ .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
> +	{ .icl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr = {
> @@ -750,16 +570,16 @@ static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hb
>  
>  static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> +	{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
> +	{ .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
> +	{ .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
> @@ -885,16 +705,16 @@ static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = {
>  
>  static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> +	{ .icl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
> +	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
> +	{ .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr = {
> @@ -904,16 +724,16 @@ static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr =
>  
>  static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr2[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x63, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> +	{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
> +	{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x63, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
> +	{ .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 = {
> @@ -923,16 +743,16 @@ static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 =
>  
>  static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x60, 0x32, 0x00, 0x0D } },	/* 350   700      6.0   */
> -	{ .cnl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
> -	{ .cnl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x60, 0x32, 0x00, 0x0D } },	/* 350   700      6.0   */
> +	{ .icl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } },	/* 350   900      8.2   */
> +	{ .icl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
> +	{ .icl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2 = {
> @@ -946,15 +766,15 @@ static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr
>   */
>  static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
>  							/* VS	pre-emp	*/
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	0	*/
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	1	*/
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	2	*/
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	3	*/
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	0	*/
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	1	*/
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	2	*/
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 2	0	*/
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 2	1	*/
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	0	*/
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	1	*/
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	2	*/
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	3	*/
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	0	*/
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	1	*/
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	2	*/
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 2	0	*/
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 2	1	*/
>  };
>  
>  static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl = {
> @@ -964,16 +784,16 @@ static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_
>  
>  static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
> +	{ .icl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } },	/* 350   900      8.2   */
> +	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
> +	{ .icl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr = {
> @@ -983,16 +803,16 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr =
>  
>  static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x50, 0x38, 0x00, 0x07 } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x61, 0x33, 0x00, 0x0C } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x61, 0x33, 0x00, 0x0C } },	/* 350   700      6.0   */
> +	{ .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },	/* 350   900      8.2   */
> +	{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
> +	{ .icl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
> @@ -1002,16 +822,16 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_h
>  
>  static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x63, 0x30, 0x00, 0x0F } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x63, 0x30, 0x00, 0x0F } },	/* 350   700      6.0   */
> +	{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
> +	{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 500   900      5.1   */
> +	{ .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
> @@ -1021,16 +841,16 @@ static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_
>  
>  static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } },	/* 200   200      0.0   */
> -	{ .cnl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } },	/* 200   250      1.9   */
> -	{ .cnl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } },	/* 200   300      3.5   */
> -	{ .cnl = { 0x4, 0x59, 0x32, 0x00, 0x0D } },	/* 200   350      4.9   */
> -	{ .cnl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } },	/* 250   250      0.0   */
> -	{ .cnl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
> -	{ .cnl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } },	/* 250   350      2.9   */
> -	{ .cnl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } },	/* 300   300      0.0   */
> -	{ .cnl = { 0x4, 0x65, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
> -	{ .cnl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } },	/* 350   350      0.0   */
> +	{ .icl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } },	/* 200   200      0.0   */
> +	{ .icl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } },	/* 200   250      1.9   */
> +	{ .icl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } },	/* 200   300      3.5   */
> +	{ .icl = { 0x4, 0x59, 0x32, 0x00, 0x0D } },	/* 200   350      4.9   */
> +	{ .icl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } },	/* 250   250      0.0   */
> +	{ .icl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
> +	{ .icl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } },	/* 250   350      2.9   */
> +	{ .icl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } },	/* 300   300      0.0   */
> +	{ .icl = { 0x4, 0x65, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
> +	{ .icl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } },	/* 350   350      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = {
> @@ -1040,16 +860,16 @@ static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2
>  
>  static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = {
>  							/* NT mV Trans mV db    */
> -	{ .cnl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } },	/* 350   350      0.0   */
> -	{ .cnl = { 0xA, 0x69, 0x32, 0x00, 0x0D } },	/* 350   500      3.1   */
> -	{ .cnl = { 0xC, 0x74, 0x31, 0x00, 0x0E } },	/* 350   700      6.0   */
> -	{ .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },	/* 350   900      8.2   */
> -	{ .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> -	{ .cnl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
> -	{ .cnl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } },	/* 500   900      5.1   */
> -	{ .cnl = { 0xC, 0x7F, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
> -	{ .cnl = { 0x6, 0x7F, 0x3C, 0x00, 0x03 } },	/* 600   900      3.5   */
> -	{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
> +	{ .icl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } },	/* 350   350      0.0   */
> +	{ .icl = { 0xA, 0x69, 0x32, 0x00, 0x0D } },	/* 350   500      3.1   */
> +	{ .icl = { 0xC, 0x74, 0x31, 0x00, 0x0E } },	/* 350   700      6.0   */
> +	{ .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },	/* 350   900      8.2   */
> +	{ .icl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
> +	{ .icl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
> +	{ .icl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } },	/* 500   900      5.1   */
> +	{ .icl = { 0xC, 0x7F, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
> +	{ .icl = { 0x6, 0x7F, 0x3C, 0x00, 0x03 } },	/* 600   900      3.5   */
> +	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
>  };
>  
>  static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = {
> @@ -1269,88 +1089,6 @@ bxt_get_buf_trans(struct intel_encoder *encoder,
>  		return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries);
>  }
>  
> -static const struct intel_ddi_buf_trans *
> -cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -
> -	if (voltage == VOLTAGE_INFO_0_85V) {
> -		return intel_get_buf_trans(&cnl_ddi_translations_hdmi_0_85V,
> -					   n_entries);
> -	} else if (voltage == VOLTAGE_INFO_0_95V) {
> -		return intel_get_buf_trans(&cnl_ddi_translations_hdmi_0_95V,
> -					   n_entries);
> -	} else if (voltage == VOLTAGE_INFO_1_05V) {
> -		return intel_get_buf_trans(&cnl_ddi_translations_hdmi_1_05V,
> -					   n_entries);
> -	} else {
> -		*n_entries = 1; /* shut up gcc */
> -		MISSING_CASE(voltage);
> -	}
> -	return NULL;
> -}
> -
> -static const struct intel_ddi_buf_trans *
> -cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -
> -	if (voltage == VOLTAGE_INFO_0_85V) {
> -		return intel_get_buf_trans(&cnl_ddi_translations_dp_0_85V,
> -					   n_entries);
> -	} else if (voltage == VOLTAGE_INFO_0_95V) {
> -		return intel_get_buf_trans(&cnl_ddi_translations_dp_0_95V,
> -					   n_entries);
> -	} else if (voltage == VOLTAGE_INFO_1_05V) {
> -		return intel_get_buf_trans(&cnl_ddi_translations_dp_1_05V,
> -					   n_entries);
> -	} else {
> -		*n_entries = 1; /* shut up gcc */
> -		MISSING_CASE(voltage);
> -	}
> -	return NULL;
> -}
> -
> -static const struct intel_ddi_buf_trans *
> -cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -
> -	if (dev_priv->vbt.edp.low_vswing) {
> -		if (voltage == VOLTAGE_INFO_0_85V) {
> -			return intel_get_buf_trans(&cnl_ddi_translations_edp_0_85V,
> -						   n_entries);
> -		} else if (voltage == VOLTAGE_INFO_0_95V) {
> -			return intel_get_buf_trans(&cnl_ddi_translations_edp_0_95V,
> -						   n_entries);
> -		} else if (voltage == VOLTAGE_INFO_1_05V) {
> -			return intel_get_buf_trans(&cnl_ddi_translations_edp_1_05V,
> -						   n_entries);
> -		} else {
> -			*n_entries = 1; /* shut up gcc */
> -			MISSING_CASE(voltage);
> -		}
> -		return NULL;
> -	} else {
> -		return cnl_get_buf_trans_dp(encoder, n_entries);
> -	}
> -}
> -
> -static const struct intel_ddi_buf_trans *
> -cnl_get_buf_trans(struct intel_encoder *encoder,
> -		  const struct intel_crtc_state *crtc_state,
> -		  int *n_entries)
> -{
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> -		return cnl_get_buf_trans_hdmi(encoder, n_entries);
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> -		return cnl_get_buf_trans_edp(encoder, n_entries);
> -	return cnl_get_buf_trans_dp(encoder, n_entries);
> -}
> -
>  static const struct intel_ddi_buf_trans *
>  icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
>  			   const struct intel_crtc_state *crtc_state,
> @@ -1761,8 +1499,6 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
>  			encoder->get_buf_trans = icl_get_combo_buf_trans;
>  		else
>  			encoder->get_buf_trans = icl_get_mg_buf_trans;
> -	} else if (IS_CANNONLAKE(i915)) {
> -		encoder->get_buf_trans = cnl_get_buf_trans;
>  	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
>  		encoder->get_buf_trans = bxt_get_buf_trans;
>  	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> index 05226eb46cd6..2acd720f9d4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> @@ -25,7 +25,7 @@ struct bxt_ddi_buf_trans {
>  	u8 deemphasis;
>  };
>  
> -struct cnl_ddi_buf_trans {
> +struct icl_ddi_buf_trans {
>  	u8 dw2_swing_sel;
>  	u8 dw7_n_scalar;
>  	u8 dw4_cursor_coeff;
> @@ -48,7 +48,7 @@ struct tgl_dkl_phy_ddi_buf_trans {
>  union intel_ddi_buf_trans_entry {
>  	struct hsw_ddi_buf_trans hsw;
>  	struct bxt_ddi_buf_trans bxt;
> -	struct cnl_ddi_buf_trans cnl;
> +	struct icl_ddi_buf_trans icl;
>  	struct icl_mg_phy_ddi_buf_trans mg;
>  	struct tgl_dkl_phy_ddi_buf_trans dkl;
>  };
> -- 
> 2.31.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH 17/30] drm/i915/display: rename CNL references in skl_scaler.c

[Lucas De Marchi]

With the removal of CNL, let's consider GLK as the first platform using
those constants since GLK has DISPLAY_VER == 10.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/skl_scaler.c | 10 +++++-----
 drivers/gpu/drm/i915/i915_reg.h           |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 911a113ee006..ebdd3115de16 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -341,12 +341,12 @@ static u16 cnl_nearest_filter_coef(int t)
  *
  */
 
-static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
+static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
 					     enum pipe pipe, int id, int set)
 {
 	int i;
 
-	intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
+	intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
 			  PS_COEE_INDEX_AUTO_INC);
 
 	for (i = 0; i < 17 * 7; i += 2) {
@@ -359,11 +359,11 @@ static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
 		t = cnl_coef_tap(i + 1);
 		tmp |= cnl_nearest_filter_coef(t) << 16;
 
-		intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
+		intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
 				  tmp);
 	}
 
-	intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
+	intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
 }
 
 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
@@ -386,7 +386,7 @@ static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe
 	case DRM_SCALING_FILTER_DEFAULT:
 		break;
 	case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
-		cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
+		glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
 		break;
 	default:
 		MISSING_CASE(filter);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 91e93f3e9649..d198b1a2d4b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7726,11 +7726,11 @@ enum {
 #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
 			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
 			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
-#define CNL_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,    \
+#define GLK_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,    \
 			_ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
 			_ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
 
-#define CNL_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe,     \
+#define GLK_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe,     \
 			_ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
 			_ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
 /* legacy palette */
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 17/30] drm/i915/display: rename CNL references in skl_scaler.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:01PM -0700, Lucas De Marchi wrote:
> With the removal of CNL, let's consider GLK as the first platform using
> those constants since GLK has DISPLAY_VER == 10.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_scaler.c | 10 +++++-----
>  drivers/gpu/drm/i915/i915_reg.h           |  4 ++--
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 911a113ee006..ebdd3115de16 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -341,12 +341,12 @@ static u16 cnl_nearest_filter_coef(int t)
>   *
>   */
>  
> -static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
> +static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
>  					     enum pipe pipe, int id, int set)
>  {
>  	int i;
>  
> -	intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
> +	intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
>  			  PS_COEE_INDEX_AUTO_INC);
>  
>  	for (i = 0; i < 17 * 7; i += 2) {
> @@ -359,11 +359,11 @@ static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
>  		t = cnl_coef_tap(i + 1);
>  		tmp |= cnl_nearest_filter_coef(t) << 16;
>  
> -		intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
> +		intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
>  				  tmp);
>  	}
>  
> -	intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
> +	intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
>  }
>  
>  static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
> @@ -386,7 +386,7 @@ static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe
>  	case DRM_SCALING_FILTER_DEFAULT:
>  		break;
>  	case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
> -		cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
> +		glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
>  		break;
>  	default:
>  		MISSING_CASE(filter);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 91e93f3e9649..d198b1a2d4b5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7726,11 +7726,11 @@ enum {
>  #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
>  			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
>  			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> -#define CNL_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,    \
> +#define GLK_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,    \
>  			_ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
>  			_ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
>  
> -#define CNL_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe,     \
> +#define GLK_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe,     \
>  			_ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
>  			_ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
>  /* legacy palette */
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 18/30] drm/i915: remove explicit CNL handling from i915_irq.c

[Lucas De Marchi]

Remove special handling of PORT_F in i915_irq.c and only do it for
DISPLAY_VER == 11.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 7 +++----
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2171bd2820e..17d336218b67 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2297,11 +2297,10 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 			GEN9_AUX_CHANNEL_C |
 			GEN9_AUX_CHANNEL_D;
 
-	if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
-		mask |= CNL_AUX_CHANNEL_F;
-
-	if (DISPLAY_VER(dev_priv) == 11)
+	if (DISPLAY_VER(dev_priv) == 11) {
+		mask |= ICL_AUX_CHANNEL_F;
 		mask |= ICL_AUX_CHANNEL_E;
+	}
 
 	return mask;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d198b1a2d4b5..fdc8fd424d36 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7945,7 +7945,7 @@ enum {
 #define  DSI1_NON_TE			(1 << 31)
 #define  DSI0_NON_TE			(1 << 30)
 #define  ICL_AUX_CHANNEL_E		(1 << 29)
-#define  CNL_AUX_CHANNEL_F		(1 << 28)
+#define  ICL_AUX_CHANNEL_F		(1 << 28)
 #define  GEN9_AUX_CHANNEL_D		(1 << 27)
 #define  GEN9_AUX_CHANNEL_C		(1 << 26)
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 18/30] drm/i915: remove explicit CNL handling from i915_irq.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:02PM -0700, Lucas De Marchi wrote:
> Remove special handling of PORT_F in i915_irq.c and only do it for
> DISPLAY_VER == 11.

oh! ignore my previous thought about removing the port F...

> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_irq.c | 7 +++----
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  2 files changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e2171bd2820e..17d336218b67 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2297,11 +2297,10 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
>  			GEN9_AUX_CHANNEL_C |
>  			GEN9_AUX_CHANNEL_D;
>  
> -	if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
> -		mask |= CNL_AUX_CHANNEL_F;
> -
> -	if (DISPLAY_VER(dev_priv) == 11)
> +	if (DISPLAY_VER(dev_priv) == 11) {
> +		mask |= ICL_AUX_CHANNEL_F;
>  		mask |= ICL_AUX_CHANNEL_E;
> +	}
>  
>  	return mask;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d198b1a2d4b5..fdc8fd424d36 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7945,7 +7945,7 @@ enum {
>  #define  DSI1_NON_TE			(1 << 31)
>  #define  DSI0_NON_TE			(1 << 30)
>  #define  ICL_AUX_CHANNEL_E		(1 << 29)
> -#define  CNL_AUX_CHANNEL_F		(1 << 28)
> +#define  ICL_AUX_CHANNEL_F		(1 << 28)
>  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
>  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
> -- 
> 2.31.1
> 
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Re: [Intel-gfx] [PATCH 18/30] drm/i915: remove explicit CNL handling from i915_irq.c

[Lucas De Marchi]

On Mon, Jul 26, 2021 at 06:59:35AM -0400, Rodrigo Vivi wrote:
>On Fri, Jul 23, 2021 at 05:11:02PM -0700, Lucas De Marchi wrote:
>> Remove special handling of PORT_F in i915_irq.c and only do it for
>> DISPLAY_VER == 11.
>
>oh! ignore my previous thought about removing the port F...

of course I only saw this after replying to your comment :)

thanks
Lucas De Marchi

>
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>
>Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>
>> ---
>>  drivers/gpu/drm/i915/i915_irq.c | 7 +++----
>>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>>  2 files changed, 4 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index e2171bd2820e..17d336218b67 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -2297,11 +2297,10 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
>>  			GEN9_AUX_CHANNEL_C |
>>  			GEN9_AUX_CHANNEL_D;
>>
>> -	if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
>> -		mask |= CNL_AUX_CHANNEL_F;
>> -
>> -	if (DISPLAY_VER(dev_priv) == 11)
>> +	if (DISPLAY_VER(dev_priv) == 11) {
>> +		mask |= ICL_AUX_CHANNEL_F;
>>  		mask |= ICL_AUX_CHANNEL_E;
>> +	}
>>
>>  	return mask;
>>  }
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d198b1a2d4b5..fdc8fd424d36 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7945,7 +7945,7 @@ enum {
>>  #define  DSI1_NON_TE			(1 << 31)
>>  #define  DSI0_NON_TE			(1 << 30)
>>  #define  ICL_AUX_CHANNEL_E		(1 << 29)
>> -#define  CNL_AUX_CHANNEL_F		(1 << 28)
>> +#define  ICL_AUX_CHANNEL_F		(1 << 28)
>>  #define  GEN9_AUX_CHANNEL_D		(1 << 27)
>>  #define  GEN9_AUX_CHANNEL_C		(1 << 26)
>>  #define  GEN9_AUX_CHANNEL_B		(1 << 25)
>> --
>> 2.31.1
>>
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[Intel-gfx] [PATCH 19/30] drm/i915: remove explicit CNL handling from intel_pm.c

[Lucas De Marchi]

Remove support for CNL as it's highly untested, probably broken, and
there is no real platform that requires this code. This is part of CNL
removal from i915.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c | 41 +--------------------------------
 2 files changed, 2 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fdc8fd424d36..f032a4c8b26d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8239,7 +8239,7 @@ enum {
 
 #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
 #define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)
-#define   CNL_DELAY_PMRSP		(1 << 22)
+#define   ICL_DELAY_PMRSP		(1 << 22)
 #define   MASK_WAKEMEM			(1 << 13)
 #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aa64b2ef2efb..65bc3709f54c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7465,7 +7465,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 
 	/*Wa_14010594013:icl, ehl */
 	intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
-			 0, CNL_DELAY_PMRSP);
+			 0, ICL_DELAY_PMRSP);
 }
 
 static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7515,43 +7515,6 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 		   CNP_PWM_CGE_GATING_DISABLE);
 }
 
-static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-{
-	u32 val;
-	cnp_init_clock_gating(dev_priv);
-
-	/* This is not an Wa. Enable for better image quality */
-	intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,
-		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
-
-	/* WaEnableChickenDCPR:cnl */
-	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
-		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
-
-	/*
-	 * WaFbcWakeMemOn:cnl
-	 * Display WA #0859: cnl
-	 */
-	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
-		   DISP_FBC_MEMORY_WAKE);
-
-	val = intel_uncore_read(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE);
-	/* ReadHitWriteOnlyDisable:cnl */
-	val |= RCCUNIT_CLKGATE_DIS;
-	intel_uncore_write(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE, val);
-
-	/* Wa_2201832410:cnl */
-	val = intel_uncore_read(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE);
-	val |= GWUNIT_CLKGATE_DIS;
-	intel_uncore_write(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE, val);
-
-	/* WaDisableVFclkgate:cnl */
-	/* WaVFUnitClockGatingDisable:cnl */
-	val = intel_uncore_read(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE);
-	val |= VFUNIT_CLKGATE_DIS;
-	intel_uncore_write(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, val);
-}
-
 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	cnp_init_clock_gating(dev_priv);
@@ -7980,8 +7943,6 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
 	else if (GRAPHICS_VER(dev_priv) == 11)
 		dev_priv->display.init_clock_gating = icl_init_clock_gating;
-	else if (IS_CANNONLAKE(dev_priv))
-		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
 	else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
 	else if (IS_SKYLAKE(dev_priv))
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 19/30] drm/i915: remove explicit CNL handling from intel_pm.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:03PM -0700, Lucas De Marchi wrote:
> Remove support for CNL as it's highly untested, probably broken, and
> there is no real platform that requires this code. This is part of CNL
> removal from i915.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c | 41 +--------------------------------
>  2 files changed, 2 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fdc8fd424d36..f032a4c8b26d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8239,7 +8239,7 @@ enum {
>  
>  #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
>  #define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)
> -#define   CNL_DELAY_PMRSP		(1 << 22)
> +#define   ICL_DELAY_PMRSP		(1 << 22)
>  #define   MASK_WAKEMEM			(1 << 13)
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index aa64b2ef2efb..65bc3709f54c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7465,7 +7465,7 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  	/*Wa_14010594013:icl, ehl */
>  	intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> -			 0, CNL_DELAY_PMRSP);
> +			 0, ICL_DELAY_PMRSP);
>  }
>  
>  static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -7515,43 +7515,6 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>  		   CNP_PWM_CGE_GATING_DISABLE);
>  }
>  
> -static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> -{
> -	u32 val;
> -	cnp_init_clock_gating(dev_priv);
> -
> -	/* This is not an Wa. Enable for better image quality */
> -	intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,
> -		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> -
> -	/* WaEnableChickenDCPR:cnl */
> -	intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> -		   intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
> -
> -	/*
> -	 * WaFbcWakeMemOn:cnl
> -	 * Display WA #0859: cnl
> -	 */
> -	intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
> -		   DISP_FBC_MEMORY_WAKE);
> -
> -	val = intel_uncore_read(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE);
> -	/* ReadHitWriteOnlyDisable:cnl */
> -	val |= RCCUNIT_CLKGATE_DIS;
> -	intel_uncore_write(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE, val);
> -
> -	/* Wa_2201832410:cnl */
> -	val = intel_uncore_read(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE);
> -	val |= GWUNIT_CLKGATE_DIS;
> -	intel_uncore_write(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE, val);
> -
> -	/* WaDisableVFclkgate:cnl */
> -	/* WaVFUnitClockGatingDisable:cnl */
> -	val = intel_uncore_read(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE);
> -	val |= VFUNIT_CLKGATE_DIS;
> -	intel_uncore_write(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, val);
> -}
> -
>  static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	cnp_init_clock_gating(dev_priv);
> @@ -7980,8 +7943,6 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
>  	else if (GRAPHICS_VER(dev_priv) == 11)
>  		dev_priv->display.init_clock_gating = icl_init_clock_gating;
> -	else if (IS_CANNONLAKE(dev_priv))
> -		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>  	else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
>  	else if (IS_SKYLAKE(dev_priv))
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 20/30] drm/i915: remove explicit CNL handling from intel_mocs.c

[Lucas De Marchi]

Only one reference to CNL that is not needed, but code is the same for
GEN9_BC, so leave the code around and just remove the special
case for CNL.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 17848807f111..582c4423b95d 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -352,7 +352,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 		table->size  = ARRAY_SIZE(icl_mocs_table);
 		table->table = icl_mocs_table;
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
-	} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
+	} else if (IS_GEN9_BC(i915)) {
 		table->size  = ARRAY_SIZE(skl_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = skl_mocs_table;
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 20/30] drm/i915: remove explicit CNL handling from intel_mocs.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:04PM -0700, Lucas De Marchi wrote:
> Only one reference to CNL that is not needed, but code is the same for
> GEN9_BC, so leave the code around and just remove the special
> case for CNL.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 17848807f111..582c4423b95d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -352,7 +352,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  		table->size  = ARRAY_SIZE(icl_mocs_table);
>  		table->table = icl_mocs_table;
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> -	} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
> +	} else if (IS_GEN9_BC(i915)) {
>  		table->size  = ARRAY_SIZE(skl_mocs_table);
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>  		table->table = skl_mocs_table;
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 21/30] drm/i915: remove explicit CNL handling from intel_pch.c

[Lucas De Marchi]

Remove references for CNL from pch detection.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_pch.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index cc44164e242b..d1d4b97b86f5 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -81,7 +81,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 	case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n");
 		drm_WARN_ON(&dev_priv->drm,
-			    !IS_CANNONLAKE(dev_priv) &&
 			    !IS_COFFEELAKE(dev_priv) &&
 			    !IS_COMETLAKE(dev_priv));
 		return PCH_CNP;
@@ -89,7 +88,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		drm_dbg_kms(&dev_priv->drm,
 			    "Found Cannon Lake LP PCH (CNP-LP)\n");
 		drm_WARN_ON(&dev_priv->drm,
-			    !IS_CANNONLAKE(dev_priv) &&
 			    !IS_COFFEELAKE(dev_priv) &&
 			    !IS_COMETLAKE(dev_priv));
 		return PCH_CNP;
@@ -171,8 +169,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
 		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
 	else if (IS_ICELAKE(dev_priv))
 		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
-	else if (IS_CANNONLAKE(dev_priv) ||
-		 IS_COFFEELAKE(dev_priv) ||
+	else if (IS_COFFEELAKE(dev_priv) ||
 		 IS_COMETLAKE(dev_priv))
 		id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 	else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 21/30] drm/i915: remove explicit CNL handling from intel_pch.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:05PM -0700, Lucas De Marchi wrote:
> Remove references for CNL from pch detection.

for a moment I almost thought you were removing the CNP support...

> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pch.c | 5 +----
>  1 file changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
> index cc44164e242b..d1d4b97b86f5 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -81,7 +81,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
>  	case INTEL_PCH_CNP_DEVICE_ID_TYPE:
>  		drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n");
>  		drm_WARN_ON(&dev_priv->drm,
> -			    !IS_CANNONLAKE(dev_priv) &&
>  			    !IS_COFFEELAKE(dev_priv) &&
>  			    !IS_COMETLAKE(dev_priv));
>  		return PCH_CNP;
> @@ -89,7 +88,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "Found Cannon Lake LP PCH (CNP-LP)\n");
>  		drm_WARN_ON(&dev_priv->drm,
> -			    !IS_CANNONLAKE(dev_priv) &&
>  			    !IS_COFFEELAKE(dev_priv) &&
>  			    !IS_COMETLAKE(dev_priv));
>  		return PCH_CNP;
> @@ -171,8 +169,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
>  		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
>  	else if (IS_ICELAKE(dev_priv))
>  		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
> -	else if (IS_CANNONLAKE(dev_priv) ||
> -		 IS_COFFEELAKE(dev_priv) ||
> +	else if (IS_COFFEELAKE(dev_priv) ||
>  		 IS_COMETLAKE(dev_priv))
>  		id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
>  	else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 22/30] drm/i915: remove explicit CNL handling from intel_wopcm.c

[Lucas De Marchi]

Consider the new WOPCM size as starting in ICL rather than CNL since the
latter is being removed from the driver.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_wopcm.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index 8309455f13ea..5e511bb891f9 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -56,8 +56,8 @@
 
 /* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
 #define BXT_WOPCM_RC6_CTX_RESERVED	(SZ_16K + SZ_8K)
-/* 36KB WOPCM reserved at the end of WOPCM on CNL. */
-#define CNL_WOPCM_HW_CTX_RESERVED	(SZ_32K + SZ_4K)
+/* 36KB WOPCM reserved at the end of WOPCM on ICL. */
+#define ICL_WOPCM_HW_CTX_RESERVED	(SZ_32K + SZ_4K)
 
 /* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
 #define GEN9_GUC_FW_RESERVED	SZ_128K
@@ -93,8 +93,8 @@ static u32 context_reserved_size(struct drm_i915_private *i915)
 {
 	if (IS_GEN9_LP(i915))
 		return BXT_WOPCM_RC6_CTX_RESERVED;
-	else if (GRAPHICS_VER(i915) >= 10)
-		return CNL_WOPCM_HW_CTX_RESERVED;
+	else if (GRAPHICS_VER(i915) >= 11)
+		return ICL_WOPCM_HW_CTX_RESERVED;
 	else
 		return 0;
 }
@@ -126,7 +126,7 @@ static bool gen9_check_huc_fw_fits(struct drm_i915_private *i915,
 				   u32 guc_wopcm_size, u32 huc_fw_size)
 {
 	/*
-	 * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
+	 * On Gen9, hardware requires the total available GuC WOPCM
 	 * size to be larger than or equal to HuC firmware size. Otherwise,
 	 * firmware uploading would fail.
 	 */
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 22/30] drm/i915: remove explicit CNL handling from intel_wopcm.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:06PM -0700, Lucas De Marchi wrote:
> Consider the new WOPCM size as starting in ICL rather than CNL since the
> latter is being removed from the driver.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_wopcm.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
> index 8309455f13ea..5e511bb891f9 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -56,8 +56,8 @@
>  
>  /* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
>  #define BXT_WOPCM_RC6_CTX_RESERVED	(SZ_16K + SZ_8K)
> -/* 36KB WOPCM reserved at the end of WOPCM on CNL. */
> -#define CNL_WOPCM_HW_CTX_RESERVED	(SZ_32K + SZ_4K)
> +/* 36KB WOPCM reserved at the end of WOPCM on ICL. */
> +#define ICL_WOPCM_HW_CTX_RESERVED	(SZ_32K + SZ_4K)
>  
>  /* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
>  #define GEN9_GUC_FW_RESERVED	SZ_128K
> @@ -93,8 +93,8 @@ static u32 context_reserved_size(struct drm_i915_private *i915)
>  {
>  	if (IS_GEN9_LP(i915))
>  		return BXT_WOPCM_RC6_CTX_RESERVED;
> -	else if (GRAPHICS_VER(i915) >= 10)
> -		return CNL_WOPCM_HW_CTX_RESERVED;
> +	else if (GRAPHICS_VER(i915) >= 11)
> +		return ICL_WOPCM_HW_CTX_RESERVED;
>  	else
>  		return 0;
>  }
> @@ -126,7 +126,7 @@ static bool gen9_check_huc_fw_fits(struct drm_i915_private *i915,
>  				   u32 guc_wopcm_size, u32 huc_fw_size)
>  {
>  	/*
> -	 * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
> +	 * On Gen9, hardware requires the total available GuC WOPCM
>  	 * size to be larger than or equal to HuC firmware size. Otherwise,
>  	 * firmware uploading would fail.
>  	 */
> -- 
> 2.31.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH 23/30] drm/i915/gt: remove explicit CNL handling from intel_sseu.c

[Lucas De Marchi]

CNL is the only platform with GRAPHICS_VER == 10. With its removal we
don't need to handle that version anymore.

Also we can now reduce the max number of slices: the call to
intel_sseu_set_info() with the highest number of slices comes from SKL
and BDW with 3 slices. Recent platforms actually increase the
number of subslices so the number of slices remain 1.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 79 ----------------------------
 drivers/gpu/drm/i915/gt/intel_sseu.h |  2 +-
 2 files changed, 1 insertion(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 367fd44b81c8..9542c3f3822a 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -188,83 +188,6 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
 	sseu->has_eu_pg = 1;
 }
 
-static void gen10_sseu_info_init(struct intel_gt *gt)
-{
-	struct intel_uncore *uncore = gt->uncore;
-	struct sseu_dev_info *sseu = &gt->info.sseu;
-	const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
-	const int eu_mask = 0xff;
-	u32 subslice_mask, eu_en;
-	int s, ss;
-
-	intel_sseu_set_info(sseu, 6, 4, 8);
-
-	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
-		GEN10_F2_S_ENA_SHIFT;
-
-	/* Slice0 */
-	eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
-	for (ss = 0; ss < sseu->max_subslices; ss++)
-		sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
-	/* Slice1 */
-	sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
-	eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
-	sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
-	/* Slice2 */
-	sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
-	sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
-	/* Slice3 */
-	sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
-	eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
-	sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
-	/* Slice4 */
-	sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
-	sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
-	/* Slice5 */
-	sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
-	eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
-	sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
-
-	subslice_mask = (1 << 4) - 1;
-	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
-			   GEN10_F2_SS_DIS_SHIFT);
-
-	for (s = 0; s < sseu->max_slices; s++) {
-		u32 subslice_mask_with_eus = subslice_mask;
-
-		for (ss = 0; ss < sseu->max_subslices; ss++) {
-			if (sseu_get_eus(sseu, s, ss) == 0)
-				subslice_mask_with_eus &= ~BIT(ss);
-		}
-
-		/*
-		 * Slice0 can have up to 3 subslices, but there are only 2 in
-		 * slice1/2.
-		 */
-		intel_sseu_set_subslices(sseu, s, s == 0 ?
-					 subslice_mask_with_eus :
-					 subslice_mask_with_eus & 0x3);
-	}
-
-	sseu->eu_total = compute_eu_total(sseu);
-
-	/*
-	 * CNL is expected to always have a uniform distribution
-	 * of EU across subslices with the exception that any one
-	 * EU in any one subslice may be fused off for die
-	 * recovery.
-	 */
-	sseu->eu_per_subslice =
-		intel_sseu_subslice_total(sseu) ?
-		DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :
-		0;
-
-	/* No restrictions on Power Gating */
-	sseu->has_slice_pg = 1;
-	sseu->has_subslice_pg = 1;
-	sseu->has_eu_pg = 1;
-}
-
 static void cherryview_sseu_info_init(struct intel_gt *gt)
 {
 	struct sseu_dev_info *sseu = &gt->info.sseu;
@@ -592,8 +515,6 @@ void intel_sseu_info_init(struct intel_gt *gt)
 		bdw_sseu_info_init(gt);
 	else if (GRAPHICS_VER(i915) == 9)
 		gen9_sseu_info_init(gt);
-	else if (GRAPHICS_VER(i915) == 10)
-		gen10_sseu_info_init(gt);
 	else if (GRAPHICS_VER(i915) == 11)
 		gen11_sseu_info_init(gt);
 	else if (GRAPHICS_VER(i915) >= 12)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4cd1a8a7298a..8d85ec05f610 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -15,7 +15,7 @@ struct drm_i915_private;
 struct intel_gt;
 struct drm_printer;
 
-#define GEN_MAX_SLICES		(6) /* CNL upper bound */
+#define GEN_MAX_SLICES		(3) /* SKL upper bound */
 #define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */
 #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
 #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 23/30] drm/i915/gt: remove explicit CNL handling from intel_sseu.c

[Matt Roper]

On Fri, Jul 23, 2021 at 05:11:07PM -0700, Lucas De Marchi wrote:
> CNL is the only platform with GRAPHICS_VER == 10. With its removal we
> don't need to handle that version anymore.
> 
> Also we can now reduce the max number of slices: the call to
> intel_sseu_set_info() with the highest number of slices comes from SKL
> and BDW with 3 slices. Recent platforms actually increase the
> number of subslices so the number of slices remain 1.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_sseu.c | 79 ----------------------------
>  drivers/gpu/drm/i915/gt/intel_sseu.h |  2 +-
>  2 files changed, 1 insertion(+), 80 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 367fd44b81c8..9542c3f3822a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -188,83 +188,6 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
>  	sseu->has_eu_pg = 1;
>  }
>  
> -static void gen10_sseu_info_init(struct intel_gt *gt)
> -{
> -	struct intel_uncore *uncore = gt->uncore;
> -	struct sseu_dev_info *sseu = &gt->info.sseu;
> -	const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
> -	const int eu_mask = 0xff;
> -	u32 subslice_mask, eu_en;
> -	int s, ss;
> -
> -	intel_sseu_set_info(sseu, 6, 4, 8);
> -
> -	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
> -		GEN10_F2_S_ENA_SHIFT;
> -
> -	/* Slice0 */
> -	eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0);
> -	for (ss = 0; ss < sseu->max_subslices; ss++)
> -		sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
> -	/* Slice1 */
> -	sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
> -	eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1);
> -	sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
> -	/* Slice2 */
> -	sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
> -	sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
> -	/* Slice3 */
> -	sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
> -	eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2);
> -	sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
> -	/* Slice4 */
> -	sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
> -	sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
> -	/* Slice5 */
> -	sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
> -	eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3);
> -	sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
> -
> -	subslice_mask = (1 << 4) - 1;
> -	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> -			   GEN10_F2_SS_DIS_SHIFT);
> -
> -	for (s = 0; s < sseu->max_slices; s++) {
> -		u32 subslice_mask_with_eus = subslice_mask;
> -
> -		for (ss = 0; ss < sseu->max_subslices; ss++) {
> -			if (sseu_get_eus(sseu, s, ss) == 0)
> -				subslice_mask_with_eus &= ~BIT(ss);
> -		}
> -
> -		/*
> -		 * Slice0 can have up to 3 subslices, but there are only 2 in
> -		 * slice1/2.
> -		 */
> -		intel_sseu_set_subslices(sseu, s, s == 0 ?
> -					 subslice_mask_with_eus :
> -					 subslice_mask_with_eus & 0x3);
> -	}
> -
> -	sseu->eu_total = compute_eu_total(sseu);
> -
> -	/*
> -	 * CNL is expected to always have a uniform distribution
> -	 * of EU across subslices with the exception that any one
> -	 * EU in any one subslice may be fused off for die
> -	 * recovery.
> -	 */
> -	sseu->eu_per_subslice =
> -		intel_sseu_subslice_total(sseu) ?
> -		DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) :
> -		0;
> -
> -	/* No restrictions on Power Gating */
> -	sseu->has_slice_pg = 1;
> -	sseu->has_subslice_pg = 1;
> -	sseu->has_eu_pg = 1;
> -}
> -
>  static void cherryview_sseu_info_init(struct intel_gt *gt)
>  {
>  	struct sseu_dev_info *sseu = &gt->info.sseu;
> @@ -592,8 +515,6 @@ void intel_sseu_info_init(struct intel_gt *gt)
>  		bdw_sseu_info_init(gt);
>  	else if (GRAPHICS_VER(i915) == 9)
>  		gen9_sseu_info_init(gt);
> -	else if (GRAPHICS_VER(i915) == 10)
> -		gen10_sseu_info_init(gt);
>  	else if (GRAPHICS_VER(i915) == 11)
>  		gen11_sseu_info_init(gt);
>  	else if (GRAPHICS_VER(i915) >= 12)
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index 4cd1a8a7298a..8d85ec05f610 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -15,7 +15,7 @@ struct drm_i915_private;
>  struct intel_gt;
>  struct drm_printer;
>  
> -#define GEN_MAX_SLICES		(6) /* CNL upper bound */
> +#define GEN_MAX_SLICES		(3) /* SKL upper bound */
>  #define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */
>  #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
>  #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
> -- 
> 2.31.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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[Intel-gfx] [PATCH 24/30] drm/i915: rename CNL references in intel_dram.c

[Lucas De Marchi]

With the removal of CNL, let's consider ICL as the first platform using
those constants.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 24 +++++++++++------------
 drivers/gpu/drm/i915/intel_dram.c | 32 +++++++++++++++----------------
 2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f032a4c8b26d..8782d1723254 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11082,18 +11082,18 @@ enum skl_power_gate {
 #define  SKL_DRAM_RANK_1			(0x0 << 10)
 #define  SKL_DRAM_RANK_2			(0x1 << 10)
 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
-#define  CNL_DRAM_SIZE_MASK			0x7F
-#define  CNL_DRAM_WIDTH_MASK			(0x3 << 7)
-#define  CNL_DRAM_WIDTH_SHIFT			7
-#define  CNL_DRAM_WIDTH_X8			(0x0 << 7)
-#define  CNL_DRAM_WIDTH_X16			(0x1 << 7)
-#define  CNL_DRAM_WIDTH_X32			(0x2 << 7)
-#define  CNL_DRAM_RANK_MASK			(0x3 << 9)
-#define  CNL_DRAM_RANK_SHIFT			9
-#define  CNL_DRAM_RANK_1			(0x0 << 9)
-#define  CNL_DRAM_RANK_2			(0x1 << 9)
-#define  CNL_DRAM_RANK_3			(0x2 << 9)
-#define  CNL_DRAM_RANK_4			(0x3 << 9)
+#define  ICL_DRAM_SIZE_MASK			0x7F
+#define  ICL_DRAM_WIDTH_MASK			(0x3 << 7)
+#define  ICL_DRAM_WIDTH_SHIFT			7
+#define  ICL_DRAM_WIDTH_X8			(0x0 << 7)
+#define  ICL_DRAM_WIDTH_X16			(0x1 << 7)
+#define  ICL_DRAM_WIDTH_X32			(0x2 << 7)
+#define  ICL_DRAM_RANK_MASK			(0x3 << 9)
+#define  ICL_DRAM_RANK_SHIFT			9
+#define  ICL_DRAM_RANK_1			(0x0 << 9)
+#define  ICL_DRAM_RANK_2			(0x1 << 9)
+#define  ICL_DRAM_RANK_3			(0x2 << 9)
+#define  ICL_DRAM_RANK_4			(0x3 << 9)
 
 #define SA_PERF_STATUS_0_0_0_MCHBAR_PC		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
 #define  DG1_QCLK_RATIO_MASK			REG_GENMASK(9, 2)
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 9675bb94b70b..34d6cf440352 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -77,21 +77,21 @@ static int skl_get_dimm_ranks(u16 val)
 }
 
 /* Returns total Gb for the whole DIMM */
-static int cnl_get_dimm_size(u16 val)
+static int icl_get_dimm_size(u16 val)
 {
-	return (val & CNL_DRAM_SIZE_MASK) * 8 / 2;
+	return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
 }
 
-static int cnl_get_dimm_width(u16 val)
+static int icl_get_dimm_width(u16 val)
 {
-	if (cnl_get_dimm_size(val) == 0)
+	if (icl_get_dimm_size(val) == 0)
 		return 0;
 
-	switch (val & CNL_DRAM_WIDTH_MASK) {
-	case CNL_DRAM_WIDTH_X8:
-	case CNL_DRAM_WIDTH_X16:
-	case CNL_DRAM_WIDTH_X32:
-		val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
+	switch (val & ICL_DRAM_WIDTH_MASK) {
+	case ICL_DRAM_WIDTH_X8:
+	case ICL_DRAM_WIDTH_X16:
+	case ICL_DRAM_WIDTH_X32:
+		val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
 		return 8 << val;
 	default:
 		MISSING_CASE(val);
@@ -99,12 +99,12 @@ static int cnl_get_dimm_width(u16 val)
 	}
 }
 
-static int cnl_get_dimm_ranks(u16 val)
+static int icl_get_dimm_ranks(u16 val)
 {
-	if (cnl_get_dimm_size(val) == 0)
+	if (icl_get_dimm_size(val) == 0)
 		return 0;
 
-	val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
+	val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
 
 	return val + 1;
 }
@@ -121,10 +121,10 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
 		       struct dram_dimm_info *dimm,
 		       int channel, char dimm_name, u16 val)
 {
-	if (GRAPHICS_VER(i915) >= 10) {
-		dimm->size = cnl_get_dimm_size(val);
-		dimm->width = cnl_get_dimm_width(val);
-		dimm->ranks = cnl_get_dimm_ranks(val);
+	if (GRAPHICS_VER(i915) >= 11) {
+		dimm->size = icl_get_dimm_size(val);
+		dimm->width = icl_get_dimm_width(val);
+		dimm->ranks = icl_get_dimm_ranks(val);
 	} else {
 		dimm->size = skl_get_dimm_size(val);
 		dimm->width = skl_get_dimm_width(val);
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 24/30] drm/i915: rename CNL references in intel_dram.c

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:08PM -0700, Lucas De Marchi wrote:
> With the removal of CNL, let's consider ICL as the first platform using
> those constants.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h   | 24 +++++++++++------------
>  drivers/gpu/drm/i915/intel_dram.c | 32 +++++++++++++++----------------
>  2 files changed, 28 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f032a4c8b26d..8782d1723254 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11082,18 +11082,18 @@ enum skl_power_gate {
>  #define  SKL_DRAM_RANK_1			(0x0 << 10)
>  #define  SKL_DRAM_RANK_2			(0x1 << 10)
>  #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
> -#define  CNL_DRAM_SIZE_MASK			0x7F
> -#define  CNL_DRAM_WIDTH_MASK			(0x3 << 7)
> -#define  CNL_DRAM_WIDTH_SHIFT			7
> -#define  CNL_DRAM_WIDTH_X8			(0x0 << 7)
> -#define  CNL_DRAM_WIDTH_X16			(0x1 << 7)
> -#define  CNL_DRAM_WIDTH_X32			(0x2 << 7)
> -#define  CNL_DRAM_RANK_MASK			(0x3 << 9)
> -#define  CNL_DRAM_RANK_SHIFT			9
> -#define  CNL_DRAM_RANK_1			(0x0 << 9)
> -#define  CNL_DRAM_RANK_2			(0x1 << 9)
> -#define  CNL_DRAM_RANK_3			(0x2 << 9)
> -#define  CNL_DRAM_RANK_4			(0x3 << 9)
> +#define  ICL_DRAM_SIZE_MASK			0x7F
> +#define  ICL_DRAM_WIDTH_MASK			(0x3 << 7)
> +#define  ICL_DRAM_WIDTH_SHIFT			7
> +#define  ICL_DRAM_WIDTH_X8			(0x0 << 7)
> +#define  ICL_DRAM_WIDTH_X16			(0x1 << 7)
> +#define  ICL_DRAM_WIDTH_X32			(0x2 << 7)
> +#define  ICL_DRAM_RANK_MASK			(0x3 << 9)
> +#define  ICL_DRAM_RANK_SHIFT			9
> +#define  ICL_DRAM_RANK_1			(0x0 << 9)
> +#define  ICL_DRAM_RANK_2			(0x1 << 9)
> +#define  ICL_DRAM_RANK_3			(0x2 << 9)
> +#define  ICL_DRAM_RANK_4			(0x3 << 9)
>  
>  #define SA_PERF_STATUS_0_0_0_MCHBAR_PC		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
>  #define  DG1_QCLK_RATIO_MASK			REG_GENMASK(9, 2)
> diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
> index 9675bb94b70b..34d6cf440352 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -77,21 +77,21 @@ static int skl_get_dimm_ranks(u16 val)
>  }
>  
>  /* Returns total Gb for the whole DIMM */
> -static int cnl_get_dimm_size(u16 val)
> +static int icl_get_dimm_size(u16 val)
>  {
> -	return (val & CNL_DRAM_SIZE_MASK) * 8 / 2;
> +	return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
>  }
>  
> -static int cnl_get_dimm_width(u16 val)
> +static int icl_get_dimm_width(u16 val)
>  {
> -	if (cnl_get_dimm_size(val) == 0)
> +	if (icl_get_dimm_size(val) == 0)
>  		return 0;
>  
> -	switch (val & CNL_DRAM_WIDTH_MASK) {
> -	case CNL_DRAM_WIDTH_X8:
> -	case CNL_DRAM_WIDTH_X16:
> -	case CNL_DRAM_WIDTH_X32:
> -		val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
> +	switch (val & ICL_DRAM_WIDTH_MASK) {
> +	case ICL_DRAM_WIDTH_X8:
> +	case ICL_DRAM_WIDTH_X16:
> +	case ICL_DRAM_WIDTH_X32:
> +		val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
>  		return 8 << val;
>  	default:
>  		MISSING_CASE(val);
> @@ -99,12 +99,12 @@ static int cnl_get_dimm_width(u16 val)
>  	}
>  }
>  
> -static int cnl_get_dimm_ranks(u16 val)
> +static int icl_get_dimm_ranks(u16 val)
>  {
> -	if (cnl_get_dimm_size(val) == 0)
> +	if (icl_get_dimm_size(val) == 0)
>  		return 0;
>  
> -	val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
> +	val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
>  
>  	return val + 1;
>  }
> @@ -121,10 +121,10 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
>  		       struct dram_dimm_info *dimm,
>  		       int channel, char dimm_name, u16 val)
>  {
> -	if (GRAPHICS_VER(i915) >= 10) {
> -		dimm->size = cnl_get_dimm_size(val);
> -		dimm->width = cnl_get_dimm_width(val);
> -		dimm->ranks = cnl_get_dimm_ranks(val);
> +	if (GRAPHICS_VER(i915) >= 11) {
> +		dimm->size = icl_get_dimm_size(val);
> +		dimm->width = icl_get_dimm_width(val);
> +		dimm->ranks = icl_get_dimm_ranks(val);
>  	} else {
>  		dimm->size = skl_get_dimm_size(val);
>  		dimm->width = skl_get_dimm_width(val);
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 25/30] drm/i915/gt: rename CNL references in intel_engine.h

[Lucas De Marchi]

With the removal of CNL, let's consider ICL as the first platform using
that index.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine.h | 2 +-
 drivers/gpu/drm/i915/i915_drv.h        | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index f911c1224ab2..dfb400766db5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -179,7 +179,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 
 #define I915_HWS_CSB_BUF0_INDEX		0x10
 #define I915_HWS_CSB_WRITE_INDEX	0x1f
-#define CNL_HWS_CSB_WRITE_INDEX		0x2f
+#define ICL_HWS_CSB_WRITE_INDEX		0x2f
 
 void intel_engine_stop(struct intel_engine_cs *engine);
 void intel_engine_cleanup(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d118834a4ed9..dd2d196050d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1959,8 +1959,8 @@ int remap_io_sg(struct vm_area_struct *vma,
 
 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
 {
-	if (GRAPHICS_VER(i915) >= 10)
-		return CNL_HWS_CSB_WRITE_INDEX;
+	if (GRAPHICS_VER(i915) >= 11)
+		return ICL_HWS_CSB_WRITE_INDEX;
 	else
 		return I915_HWS_CSB_WRITE_INDEX;
 }
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 25/30] drm/i915/gt: rename CNL references in intel_engine.h

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:09PM -0700, Lucas De Marchi wrote:
> With the removal of CNL, let's consider ICL as the first platform using
> that index.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


(
I got myself thinking that some patches like this could be squashed into others,
and a few of them made with coccinele, but in the end I like the approach you
took. It's been very easy to review this series...
)


> ---
>  drivers/gpu/drm/i915/gt/intel_engine.h | 2 +-
>  drivers/gpu/drm/i915/i915_drv.h        | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index f911c1224ab2..dfb400766db5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -179,7 +179,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
>  
>  #define I915_HWS_CSB_BUF0_INDEX		0x10
>  #define I915_HWS_CSB_WRITE_INDEX	0x1f
> -#define CNL_HWS_CSB_WRITE_INDEX		0x2f
> +#define ICL_HWS_CSB_WRITE_INDEX		0x2f
>  
>  void intel_engine_stop(struct intel_engine_cs *engine);
>  void intel_engine_cleanup(struct intel_engine_cs *engine);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d118834a4ed9..dd2d196050d4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1959,8 +1959,8 @@ int remap_io_sg(struct vm_area_struct *vma,
>  
>  static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
>  {
> -	if (GRAPHICS_VER(i915) >= 10)
> -		return CNL_HWS_CSB_WRITE_INDEX;
> +	if (GRAPHICS_VER(i915) >= 11)
> +		return ICL_HWS_CSB_WRITE_INDEX;
>  	else
>  		return I915_HWS_CSB_WRITE_INDEX;
>  }
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 26/30] drm/i915: finish removal of CNL

[Lucas De Marchi]

With all the users removed, finish removing the CNL platform definitions.
We will leave the PCI IDs around as those are exposed to userspace.
Even if mesa doesn't support CNL anymore, let's avoid build breakages
due to changing the headers.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  7 +------
 drivers/gpu/drm/i915/i915_pci.c          | 23 +++++------------------
 drivers/gpu/drm/i915/i915_perf.c         |  1 -
 drivers/gpu/drm/i915/intel_device_info.c |  2 --
 drivers/gpu/drm/i915/intel_device_info.h |  2 --
 5 files changed, 6 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dd2d196050d4..e3c8283d770c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1437,7 +1437,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 #define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
-#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 #define IS_JSL_EHL(dev_priv)	(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
 				IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
@@ -1503,8 +1502,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_CML_GT2(dev_priv)	(IS_COMETLAKE(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 2)
 
-#define IS_CNL_WITH_PORT_F(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
 #define IS_ICL_WITH_PORT_F(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
@@ -1649,9 +1646,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)			\
-	(IS_CANNONLAKE(dev_priv) ||					\
-	 IS_SKL_GT3(dev_priv) ||					\
-	 IS_SKL_GT4(dev_priv))
+	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 
 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
 #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 48ea23dd3b5b..aea2c2d82fbf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -787,27 +787,13 @@ static const struct intel_device_info cml_gt2_info = {
 	.gt = 2,
 };
 
-#define GEN10_FEATURES \
-	GEN9_FEATURES, \
-	GEN(10), \
-	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
-	.display.has_dsc = 1, \
-	.has_coherent_ggtt = false, \
-	GLK_COLORS
-
-static const struct intel_device_info cnl_info = {
-	GEN10_FEATURES,
-	PLATFORM(INTEL_CANNONLAKE),
-	.gt = 2,
-};
-
 #define GEN11_DEFAULT_PAGE_SIZES \
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_64K | \
 		      I915_GTT_PAGE_SIZE_2M
 
 #define GEN11_FEATURES \
-	GEN10_FEATURES, \
+	GEN9_FEATURES, \
 	GEN11_DEFAULT_PAGE_SIZES, \
 	.abox_mask = BIT(0), \
 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
@@ -830,10 +816,12 @@ static const struct intel_device_info cnl_info = {
 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
 	}, \
 	GEN(11), \
+	.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
 	.dbuf.size = 2048, \
 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
-	.has_logical_ring_elsq = 1, \
-	.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
+	.display.has_dsc = 1, \
+	.has_coherent_ggtt = false, \
+	.has_logical_ring_elsq = 1
 
 static const struct intel_device_info icl_info = {
 	GEN11_FEATURES,
@@ -1123,7 +1111,6 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_CML_GT2_IDS(&cml_gt2_info),
 	INTEL_CML_U_GT1_IDS(&cml_gt1_info),
 	INTEL_CML_U_GT2_IDS(&cml_gt2_info),
-	INTEL_CNL_IDS(&cnl_info),
 	INTEL_ICL_11_IDS(&icl_info),
 	INTEL_EHL_IDS(&ehl_info),
 	INTEL_JSL_IDS(&jsl_info),
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 838cc14c2f24..108774d651d9 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4319,7 +4319,6 @@ static void oa_init_supported_formats(struct i915_perf *perf)
 	case INTEL_GEMINILAKE:
 	case INTEL_COFFEELAKE:
 	case INTEL_COMETLAKE:
-	case INTEL_CANNONLAKE:
 	case INTEL_ICELAKE:
 	case INTEL_ELKHARTLAKE:
 	case INTEL_JASPERLAKE:
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 99b51c292942..2893a8659a8b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -59,7 +59,6 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(GEMINILAKE),
 	PLATFORM_NAME(COFFEELAKE),
 	PLATFORM_NAME(COMETLAKE),
-	PLATFORM_NAME(CANNONLAKE),
 	PLATFORM_NAME(ICELAKE),
 	PLATFORM_NAME(ELKHARTLAKE),
 	PLATFORM_NAME(JASPERLAKE),
@@ -175,7 +174,6 @@ static const u16 subplatform_ulx_ids[] = {
 };
 
 static const u16 subplatform_portf_ids[] = {
-	INTEL_CNL_PORT_F_IDS(0),
 	INTEL_ICL_PORT_F_IDS(0),
 };
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 616ccec41d76..057c9aa6f9c6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -76,8 +76,6 @@ enum intel_platform {
 	INTEL_GEMINILAKE,
 	INTEL_COFFEELAKE,
 	INTEL_COMETLAKE,
-	/* gen10 */
-	INTEL_CANNONLAKE,
 	/* gen11 */
 	INTEL_ICELAKE,
 	INTEL_ELKHARTLAKE,
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 26/30] drm/i915: finish removal of CNL

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:10PM -0700, Lucas De Marchi wrote:
> With all the users removed, finish removing the CNL platform definitions.
> We will leave the PCI IDs around as those are exposed to userspace.
> Even if mesa doesn't support CNL anymore, let's avoid build breakages
> due to changing the headers.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h          |  7 +------
>  drivers/gpu/drm/i915/i915_pci.c          | 23 +++++------------------
>  drivers/gpu/drm/i915/i915_perf.c         |  1 -
>  drivers/gpu/drm/i915/intel_device_info.c |  2 --
>  drivers/gpu/drm/i915/intel_device_info.h |  2 --
>  5 files changed, 6 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dd2d196050d4..e3c8283d770c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1437,7 +1437,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
>  #define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
>  #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
> -#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
>  #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
>  #define IS_JSL_EHL(dev_priv)	(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
>  				IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
> @@ -1503,8 +1502,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_CML_GT2(dev_priv)	(IS_COMETLAKE(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 2)
>  
> -#define IS_CNL_WITH_PORT_F(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
>  #define IS_ICL_WITH_PORT_F(dev_priv) \
>  	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
>  
> @@ -1649,9 +1646,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  /* WaRsDisableCoarsePowerGating:skl,cnl */
>  #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)			\
> -	(IS_CANNONLAKE(dev_priv) ||					\
> -	 IS_SKL_GT3(dev_priv) ||					\
> -	 IS_SKL_GT4(dev_priv))
> +	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
>  
>  #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
>  #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 48ea23dd3b5b..aea2c2d82fbf 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -787,27 +787,13 @@ static const struct intel_device_info cml_gt2_info = {
>  	.gt = 2,
>  };
>  
> -#define GEN10_FEATURES \
> -	GEN9_FEATURES, \
> -	GEN(10), \
> -	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
> -	.display.has_dsc = 1, \
> -	.has_coherent_ggtt = false, \
> -	GLK_COLORS
> -
> -static const struct intel_device_info cnl_info = {
> -	GEN10_FEATURES,
> -	PLATFORM(INTEL_CANNONLAKE),
> -	.gt = 2,
> -};
> -
>  #define GEN11_DEFAULT_PAGE_SIZES \
>  	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
>  		      I915_GTT_PAGE_SIZE_64K | \
>  		      I915_GTT_PAGE_SIZE_2M
>  
>  #define GEN11_FEATURES \
> -	GEN10_FEATURES, \
> +	GEN9_FEATURES, \
>  	GEN11_DEFAULT_PAGE_SIZES, \
>  	.abox_mask = BIT(0), \
>  	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> @@ -830,10 +816,12 @@ static const struct intel_device_info cnl_info = {
>  		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
>  	}, \
>  	GEN(11), \
> +	.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
>  	.dbuf.size = 2048, \
>  	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> -	.has_logical_ring_elsq = 1, \
> -	.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
> +	.display.has_dsc = 1, \
> +	.has_coherent_ggtt = false, \
> +	.has_logical_ring_elsq = 1
>  
>  static const struct intel_device_info icl_info = {
>  	GEN11_FEATURES,
> @@ -1123,7 +1111,6 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_CML_GT2_IDS(&cml_gt2_info),
>  	INTEL_CML_U_GT1_IDS(&cml_gt1_info),
>  	INTEL_CML_U_GT2_IDS(&cml_gt2_info),
> -	INTEL_CNL_IDS(&cnl_info),
>  	INTEL_ICL_11_IDS(&icl_info),
>  	INTEL_EHL_IDS(&ehl_info),
>  	INTEL_JSL_IDS(&jsl_info),
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 838cc14c2f24..108774d651d9 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4319,7 +4319,6 @@ static void oa_init_supported_formats(struct i915_perf *perf)
>  	case INTEL_GEMINILAKE:
>  	case INTEL_COFFEELAKE:
>  	case INTEL_COMETLAKE:
> -	case INTEL_CANNONLAKE:
>  	case INTEL_ICELAKE:
>  	case INTEL_ELKHARTLAKE:
>  	case INTEL_JASPERLAKE:
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 99b51c292942..2893a8659a8b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -59,7 +59,6 @@ static const char * const platform_names[] = {
>  	PLATFORM_NAME(GEMINILAKE),
>  	PLATFORM_NAME(COFFEELAKE),
>  	PLATFORM_NAME(COMETLAKE),
> -	PLATFORM_NAME(CANNONLAKE),
>  	PLATFORM_NAME(ICELAKE),
>  	PLATFORM_NAME(ELKHARTLAKE),
>  	PLATFORM_NAME(JASPERLAKE),
> @@ -175,7 +174,6 @@ static const u16 subplatform_ulx_ids[] = {
>  };
>  
>  static const u16 subplatform_portf_ids[] = {
> -	INTEL_CNL_PORT_F_IDS(0),
>  	INTEL_ICL_PORT_F_IDS(0),
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 616ccec41d76..057c9aa6f9c6 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -76,8 +76,6 @@ enum intel_platform {
>  	INTEL_GEMINILAKE,
>  	INTEL_COFFEELAKE,
>  	INTEL_COMETLAKE,
> -	/* gen10 */
> -	INTEL_CANNONLAKE,
>  	/* gen11 */
>  	INTEL_ICELAKE,
>  	INTEL_ELKHARTLAKE,
> -- 
> 2.31.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 27/30] drm/i915: remove GRAPHICS_VER == 10

[Lucas De Marchi]

Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with
{==,>=} 11. With the removal of CNL, there is no platform with graphics
version equals 10.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c    |  1 -
 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c       | 10 ++---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  3 --
 drivers/gpu/drm/i915/gt/intel_ggtt.c          |  4 +-
 .../gpu/drm/i915/gt/intel_gt_clock_utils.c    | 10 ++---
 drivers/gpu/drm/i915/gt/intel_gtt.c           |  6 +--
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 42 +------------------
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_rps.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c  |  6 +--
 drivers/gpu/drm/i915/gvt/gtt.c                |  2 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |  6 +--
 drivers/gpu/drm/i915/i915_drv.h               |  2 +-
 drivers/gpu/drm/i915/i915_perf.c              | 21 ++++------
 drivers/gpu/drm/i915/intel_device_info.c      |  4 +-
 15 files changed, 37 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 90708de27684..ddd37ccb1362 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -447,7 +447,6 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
 		break;
 	case 8:
 	case 9:
-	case 10:
 		if (IS_LP(i915))
 			chv_get_stolen_reserved(i915, uncore,
 						&reserved_base, &reserved_size);
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 4270b5a34a83..d6f5836396f8 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused)
 		max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
 			    rp_state_cap >> 16) & 0xff;
 		max_freq *= (IS_GEN9_BC(i915) ||
-			     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
+			     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 			   intel_gpu_freq(rps, max_freq));
 
 		max_freq = (rp_state_cap & 0xff00) >> 8;
 		max_freq *= (IS_GEN9_BC(i915) ||
-			     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
+			     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 			   intel_gpu_freq(rps, max_freq));
 
 		max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
 			    rp_state_cap >> 0) & 0xff;
 		max_freq *= (IS_GEN9_BC(i915) ||
-			     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
+			     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 			   intel_gpu_freq(rps, max_freq));
 		seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
 
 	min_gpu_freq = rps->min_freq;
 	max_gpu_freq = rps->max_freq;
-	if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
+	if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
 		/* Convert GT frequency to 50 HZ units */
 		min_gpu_freq /= GEN9_FREQ_SCALER;
 		max_gpu_freq /= GEN9_FREQ_SCALER;
@@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
 			   intel_gpu_freq(rps,
 					  (gpu_freq *
 					   (IS_GEN9_BC(i915) ||
-					    GRAPHICS_VER(i915) >= 10 ?
+					    GRAPHICS_VER(i915) >= 11 ?
 					    GEN9_FREQ_SCALER : 1))),
 			   ((ia_freq >> 0) & 0xff) * 100,
 			   ((ia_freq >> 8) & 0xff) * 100);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 4168b9fc59e1..152b5493a455 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -35,7 +35,6 @@
 #define DEFAULT_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
 #define GEN8_LR_CONTEXT_RENDER_SIZE	(20 * PAGE_SIZE)
 #define GEN9_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
-#define GEN10_LR_CONTEXT_RENDER_SIZE	(18 * PAGE_SIZE)
 #define GEN11_LR_CONTEXT_RENDER_SIZE	(14 * PAGE_SIZE)
 
 #define GEN8_LR_CONTEXT_OTHER_SIZE	( 2 * PAGE_SIZE)
@@ -149,8 +148,6 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
 		case 12:
 		case 11:
 			return GEN11_LR_CONTEXT_RENDER_SIZE;
-		case 10:
-			return GEN10_LR_CONTEXT_RENDER_SIZE;
 		case 9:
 			return GEN9_LR_CONTEXT_RENDER_SIZE;
 		case 8:
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 9d445ad9a342..de3ac58fceec 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -826,13 +826,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 	phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
 
 	/*
-	 * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
+	 * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
 	 * will be dropped. For WC mappings in general we have 64 byte burst
 	 * writes when the WC buffer is flushed, so we can't use it, but have to
 	 * resort to an uncached mapping. The WC issue is easily caught by the
 	 * readback check when writing GTT PTE entries.
 	 */
-	if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)
+	if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11)
 		ggtt->gsm = ioremap(phys_addr, size);
 	else
 		ggtt->gsm = ioremap_wc(phys_addr, size);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 9f0e729d2d15..3513d6f90747 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -24,8 +24,8 @@ static u32 read_reference_ts_freq(struct intel_uncore *uncore)
 	return base_freq + frac_freq;
 }
 
-static u32 gen10_get_crystal_clock_freq(struct intel_uncore *uncore,
-					u32 rpm_config_reg)
+static u32 gen9_get_crystal_clock_freq(struct intel_uncore *uncore,
+				       u32 rpm_config_reg)
 {
 	u32 f19_2_mhz = 19200000;
 	u32 f24_mhz = 24000000;
@@ -128,10 +128,10 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
 		} else {
 			u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
 
-			if (GRAPHICS_VER(uncore->i915) <= 10)
-				freq = gen10_get_crystal_clock_freq(uncore, c0);
-			else
+			if (GRAPHICS_VER(uncore->i915) >= 11)
 				freq = gen11_get_crystal_clock_freq(uncore, c0);
+			else
+				freq = gen9_get_crystal_clock_freq(uncore, c0);
 
 			/*
 			 * Now figure out how the command stream's timestamp
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index f7e0352edb62..e137dd32b5b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -426,7 +426,7 @@ static void tgl_setup_private_ppat(struct intel_uncore *uncore)
 	intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
 }
 
-static void cnl_setup_private_ppat(struct intel_uncore *uncore)
+static void icl_setup_private_ppat(struct intel_uncore *uncore)
 {
 	intel_uncore_write(uncore,
 			   GEN10_PAT_INDEX(0),
@@ -526,8 +526,8 @@ void setup_private_pat(struct intel_uncore *uncore)
 
 	if (GRAPHICS_VER(i915) >= 12)
 		tgl_setup_private_ppat(uncore);
-	else if (GRAPHICS_VER(i915) >= 10)
-		cnl_setup_private_ppat(uncore);
+	else if (GRAPHICS_VER(i915) >= 11)
+		icl_setup_private_ppat(uncore);
 	else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
 		chv_setup_private_ppat(uncore);
 	else
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index c3f5bec8ae15..bb4af4977920 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -70,7 +70,7 @@ static void set_offsets(u32 *regs,
 	if (close) {
 		/* Close the batch; used mainly by live_lrc_layout() */
 		*regs = MI_BATCH_BUFFER_END;
-		if (GRAPHICS_VER(engine->i915) >= 10)
+		if (GRAPHICS_VER(engine->i915) >= 11)
 			*regs |= BIT(0);
 	}
 }
@@ -653,8 +653,6 @@ lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
 		return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
 	case 11:
 		return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
-	case 10:
-		return GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
 	case 9:
 		return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
 	case 8:
@@ -1448,40 +1446,6 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
 	return batch;
 }
 
-static u32 *
-gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
-{
-	int i;
-
-	/*
-	 * WaPipeControlBefore3DStateSamplePattern: cnl
-	 *
-	 * Ensure the engine is idle prior to programming a
-	 * 3DSTATE_SAMPLE_PATTERN during a context restore.
-	 */
-	batch = gen8_emit_pipe_control(batch,
-				       PIPE_CONTROL_CS_STALL,
-				       0);
-	/*
-	 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
-	 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
-	 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
-	 * confusing. Since gen8_emit_pipe_control() already advances the
-	 * batch by 6 dwords, we advance the other 10 here, completing a
-	 * cacheline. It's not clear if the workaround requires this padding
-	 * before other commands, or if it's just the regular padding we would
-	 * already have for the workaround bb, so leave it here for now.
-	 */
-	for (i = 0; i < 10; i++)
-		*batch++ = MI_NOOP;
-
-	/* Pad to end of cacheline */
-	while ((unsigned long)batch % CACHELINE_BYTES)
-		*batch++ = MI_NOOP;
-
-	return batch;
-}
-
 #define CTX_WA_BB_SIZE (PAGE_SIZE)
 
 static int lrc_create_wa_ctx(struct intel_engine_cs *engine)
@@ -1534,10 +1498,6 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
 	case 12:
 	case 11:
 		return;
-	case 10:
-		wa_bb_fn[0] = gen10_init_indirectctx_bb;
-		wa_bb_fn[1] = NULL;
-		break;
 	case 9:
 		wa_bb_fn[0] = gen9_init_indirectctx_bb;
 		wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 259d7eb4e165..a7d13fe35b2e 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
 	enum intel_engine_id id;
 
 	/* 2b: Program RC6 thresholds.*/
-	if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {
+	if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
 		set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
 		set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
 	} else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 06e9a8ed4e03..2e03ad80f3cf 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps)
 
 	rps->efficient_freq = rps->rp1_freq;
 	if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
-	    IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
+	    IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
 		u32 ddcc_status = 0;
 
 		if (sandybridge_pcode_read(i915,
@@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps)
 					rps->max_freq);
 	}
 
-	if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
+	if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
 		/* Store the frequency values in 16.66 MHZ units, which is
 		 * the natural hardware unit for SKL
 		 */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 714fe8495775..5e7b09c5e36f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -50,7 +50,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
 #undef SS_MAX
 }
 
-static void gen10_sseu_device_status(struct intel_gt *gt,
+static void gen11_sseu_device_status(struct intel_gt *gt,
 				     struct sseu_dev_info *sseu)
 {
 #define SS_MAX 6
@@ -267,8 +267,8 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt *gt)
 			bdw_sseu_device_status(gt, &sseu);
 		else if (GRAPHICS_VER(i915) == 9)
 			gen9_sseu_device_status(gt, &sseu);
-		else if (GRAPHICS_VER(i915) >= 10)
-			gen10_sseu_device_status(gt, &sseu);
+		else if (GRAPHICS_VER(i915) >= 11)
+			gen11_sseu_device_status(gt, &sseu);
 	}
 
 	i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), &sseu);
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index cc2c05e18206..e5c2fdfc20e3 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1055,7 +1055,7 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
 {
 	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 
-	if (GRAPHICS_VER(dev_priv) == 9 || GRAPHICS_VER(dev_priv) == 10) {
+	if (GRAPHICS_VER(dev_priv) == 9) {
 		u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
 			GAMW_ECO_ENABLE_64K_IPS_FIELD;
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0529576f069c..44969f5dde50 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -538,20 +538,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
 			    rp_state_cap >> 16) & 0xff;
 		max_freq *= (IS_GEN9_BC(dev_priv) ||
-			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
+			     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 			   intel_gpu_freq(rps, max_freq));
 
 		max_freq = (rp_state_cap & 0xff00) >> 8;
 		max_freq *= (IS_GEN9_BC(dev_priv) ||
-			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
+			     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 			   intel_gpu_freq(rps, max_freq));
 
 		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
 			    rp_state_cap >> 0) & 0xff;
 		max_freq *= (IS_GEN9_BC(dev_priv) ||
-			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
+			     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 			   intel_gpu_freq(rps, max_freq));
 		seq_printf(m, "Max overclocked frequency: %dMHz\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e3c8283d770c..f9671686bf62 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1649,7 +1649,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 
 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
-#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
+#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
 					IS_GEMINILAKE(dev_priv) || \
 					IS_KABYLAKE(dev_priv))
 
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 108774d651d9..2f01b8c0284c 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1256,7 +1256,6 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
 
 	case 8:
 	case 9:
-	case 10:
 		if (intel_engine_uses_guc(ce->engine)) {
 			/*
 			 * When using GuC, the context descriptor we write in
@@ -2589,7 +2588,7 @@ static void gen8_disable_metric_set(struct i915_perf_stream *stream)
 	intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
 }
 
-static void gen10_disable_metric_set(struct i915_perf_stream *stream)
+static void gen11_disable_metric_set(struct i915_perf_stream *stream)
 {
 	struct intel_uncore *uncore = stream->uncore;
 
@@ -3896,7 +3895,7 @@ static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
 	       REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));
 }
 
-static bool gen10_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
+static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
 {
 	return gen8_is_valid_mux_addr(perf, addr) ||
 	       REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
@@ -4403,27 +4402,23 @@ void i915_perf_init(struct drm_i915_private *i915)
 
 				perf->gen8_valid_ctx_bit = BIT(16);
 			}
-		} else if (IS_GRAPHICS_VER(i915, 10, 11)) {
+		} else if (GRAPHICS_VER(i915) == 11) {
 			perf->ops.is_valid_b_counter_reg =
 				gen7_is_valid_b_counter_addr;
 			perf->ops.is_valid_mux_reg =
-				gen10_is_valid_mux_addr;
+				gen11_is_valid_mux_addr;
 			perf->ops.is_valid_flex_reg =
 				gen8_is_valid_flex_addr;
 
 			perf->ops.oa_enable = gen8_oa_enable;
 			perf->ops.oa_disable = gen8_oa_disable;
 			perf->ops.enable_metric_set = gen8_enable_metric_set;
-			perf->ops.disable_metric_set = gen10_disable_metric_set;
+			perf->ops.disable_metric_set = gen11_disable_metric_set;
 			perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
 
-			if (GRAPHICS_VER(i915) == 10) {
-				perf->ctx_oactxctrl_offset = 0x128;
-				perf->ctx_flexeu0_offset = 0x3de;
-			} else {
-				perf->ctx_oactxctrl_offset = 0x124;
-				perf->ctx_flexeu0_offset = 0x78e;
-			}
+			perf->ctx_oactxctrl_offset = 0x124;
+			perf->ctx_flexeu0_offset = 0x78e;
+
 			perf->gen8_valid_ctx_bit = BIT(16);
 		} else if (GRAPHICS_VER(i915) == 12) {
 			perf->ops.is_valid_b_counter_reg =
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 2893a8659a8b..4319ae020c86 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -265,7 +265,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_scalers[pipe] = 0;
-	else if (GRAPHICS_VER(dev_priv) >= 10) {
+	else if (GRAPHICS_VER(dev_priv) >= 11) {
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_scalers[pipe] = 2;
 	} else if (GRAPHICS_VER(dev_priv) == 9) {
@@ -282,7 +282,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	else if (GRAPHICS_VER(dev_priv) >= 11)
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 6;
-	else if (GRAPHICS_VER(dev_priv) == 10 || IS_GEMINILAKE(dev_priv))
+	else if (IS_GEMINILAKE(dev_priv))
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 3;
 	else if (IS_BROXTON(dev_priv)) {
-- 
2.31.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 27/30] drm/i915: remove GRAPHICS_VER == 10

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:11PM -0700, Lucas De Marchi wrote:
> Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with
> {==,>=} 11. With the removal of CNL, there is no platform with graphics
> version equals 10.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/gem/i915_gem_stolen.c    |  1 -
>  drivers/gpu/drm/i915/gt/debugfs_gt_pm.c       | 10 ++---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  3 --
>  drivers/gpu/drm/i915/gt/intel_ggtt.c          |  4 +-
>  .../gpu/drm/i915/gt/intel_gt_clock_utils.c    | 10 ++---
>  drivers/gpu/drm/i915/gt/intel_gtt.c           |  6 +--
>  drivers/gpu/drm/i915/gt/intel_lrc.c           | 42 +------------------
>  drivers/gpu/drm/i915/gt/intel_rc6.c           |  2 +-
>  drivers/gpu/drm/i915/gt/intel_rps.c           |  4 +-
>  drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c  |  6 +--
>  drivers/gpu/drm/i915/gvt/gtt.c                |  2 +-
>  drivers/gpu/drm/i915/i915_debugfs.c           |  6 +--
>  drivers/gpu/drm/i915/i915_drv.h               |  2 +-
>  drivers/gpu/drm/i915/i915_perf.c              | 21 ++++------
>  drivers/gpu/drm/i915/intel_device_info.c      |  4 +-
>  15 files changed, 37 insertions(+), 86 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 90708de27684..ddd37ccb1362 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -447,7 +447,6 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
>  		break;
>  	case 8:
>  	case 9:
> -	case 10:
>  		if (IS_LP(i915))
>  			chv_get_stolen_reserved(i915, uncore,
>  						&reserved_base, &reserved_size);
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index 4270b5a34a83..d6f5836396f8 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused)
>  		max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
>  			    rp_state_cap >> 16) & 0xff;
>  		max_freq *= (IS_GEN9_BC(i915) ||
> -			     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> +			     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
>  		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
>  			   intel_gpu_freq(rps, max_freq));
>  
>  		max_freq = (rp_state_cap & 0xff00) >> 8;
>  		max_freq *= (IS_GEN9_BC(i915) ||
> -			     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> +			     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
>  		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
>  			   intel_gpu_freq(rps, max_freq));
>  
>  		max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
>  			    rp_state_cap >> 0) & 0xff;
>  		max_freq *= (IS_GEN9_BC(i915) ||
> -			     GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> +			     GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
>  		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
>  			   intel_gpu_freq(rps, max_freq));
>  		seq_printf(m, "Max overclocked frequency: %dMHz\n",
> @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
>  
>  	min_gpu_freq = rps->min_freq;
>  	max_gpu_freq = rps->max_freq;
> -	if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> +	if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
>  		/* Convert GT frequency to 50 HZ units */
>  		min_gpu_freq /= GEN9_FREQ_SCALER;
>  		max_gpu_freq /= GEN9_FREQ_SCALER;
> @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
>  			   intel_gpu_freq(rps,
>  					  (gpu_freq *
>  					   (IS_GEN9_BC(i915) ||
> -					    GRAPHICS_VER(i915) >= 10 ?
> +					    GRAPHICS_VER(i915) >= 11 ?
>  					    GEN9_FREQ_SCALER : 1))),
>  			   ((ia_freq >> 0) & 0xff) * 100,
>  			   ((ia_freq >> 8) & 0xff) * 100);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 4168b9fc59e1..152b5493a455 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -35,7 +35,6 @@
>  #define DEFAULT_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
>  #define GEN8_LR_CONTEXT_RENDER_SIZE	(20 * PAGE_SIZE)
>  #define GEN9_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
> -#define GEN10_LR_CONTEXT_RENDER_SIZE	(18 * PAGE_SIZE)
>  #define GEN11_LR_CONTEXT_RENDER_SIZE	(14 * PAGE_SIZE)
>  
>  #define GEN8_LR_CONTEXT_OTHER_SIZE	( 2 * PAGE_SIZE)
> @@ -149,8 +148,6 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
>  		case 12:
>  		case 11:
>  			return GEN11_LR_CONTEXT_RENDER_SIZE;
> -		case 10:
> -			return GEN10_LR_CONTEXT_RENDER_SIZE;
>  		case 9:
>  			return GEN9_LR_CONTEXT_RENDER_SIZE;
>  		case 8:
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 9d445ad9a342..de3ac58fceec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -826,13 +826,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
>  	phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
>  
>  	/*
> -	 * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
> +	 * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
>  	 * will be dropped. For WC mappings in general we have 64 byte burst
>  	 * writes when the WC buffer is flushed, so we can't use it, but have to
>  	 * resort to an uncached mapping. The WC issue is easily caught by the
>  	 * readback check when writing GTT PTE entries.
>  	 */
> -	if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)
> +	if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11)
>  		ggtt->gsm = ioremap(phys_addr, size);
>  	else
>  		ggtt->gsm = ioremap_wc(phys_addr, size);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> index 9f0e729d2d15..3513d6f90747 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> @@ -24,8 +24,8 @@ static u32 read_reference_ts_freq(struct intel_uncore *uncore)
>  	return base_freq + frac_freq;
>  }
>  
> -static u32 gen10_get_crystal_clock_freq(struct intel_uncore *uncore,
> -					u32 rpm_config_reg)
> +static u32 gen9_get_crystal_clock_freq(struct intel_uncore *uncore,
> +				       u32 rpm_config_reg)
>  {
>  	u32 f19_2_mhz = 19200000;
>  	u32 f24_mhz = 24000000;
> @@ -128,10 +128,10 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>  		} else {
>  			u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
>  
> -			if (GRAPHICS_VER(uncore->i915) <= 10)
> -				freq = gen10_get_crystal_clock_freq(uncore, c0);
> -			else
> +			if (GRAPHICS_VER(uncore->i915) >= 11)
>  				freq = gen11_get_crystal_clock_freq(uncore, c0);
> +			else
> +				freq = gen9_get_crystal_clock_freq(uncore, c0);
>  
>  			/*
>  			 * Now figure out how the command stream's timestamp
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index f7e0352edb62..e137dd32b5b8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -426,7 +426,7 @@ static void tgl_setup_private_ppat(struct intel_uncore *uncore)
>  	intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
>  }
>  
> -static void cnl_setup_private_ppat(struct intel_uncore *uncore)
> +static void icl_setup_private_ppat(struct intel_uncore *uncore)
>  {
>  	intel_uncore_write(uncore,
>  			   GEN10_PAT_INDEX(0),
> @@ -526,8 +526,8 @@ void setup_private_pat(struct intel_uncore *uncore)
>  
>  	if (GRAPHICS_VER(i915) >= 12)
>  		tgl_setup_private_ppat(uncore);
> -	else if (GRAPHICS_VER(i915) >= 10)
> -		cnl_setup_private_ppat(uncore);
> +	else if (GRAPHICS_VER(i915) >= 11)
> +		icl_setup_private_ppat(uncore);
>  	else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
>  		chv_setup_private_ppat(uncore);
>  	else
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index c3f5bec8ae15..bb4af4977920 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -70,7 +70,7 @@ static void set_offsets(u32 *regs,
>  	if (close) {
>  		/* Close the batch; used mainly by live_lrc_layout() */
>  		*regs = MI_BATCH_BUFFER_END;
> -		if (GRAPHICS_VER(engine->i915) >= 10)
> +		if (GRAPHICS_VER(engine->i915) >= 11)
>  			*regs |= BIT(0);
>  	}
>  }
> @@ -653,8 +653,6 @@ lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
>  		return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
>  	case 11:
>  		return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> -	case 10:
> -		return GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
>  	case 9:
>  		return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
>  	case 8:
> @@ -1448,40 +1446,6 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
>  	return batch;
>  }
>  
> -static u32 *
> -gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
> -{
> -	int i;
> -
> -	/*
> -	 * WaPipeControlBefore3DStateSamplePattern: cnl
> -	 *
> -	 * Ensure the engine is idle prior to programming a
> -	 * 3DSTATE_SAMPLE_PATTERN during a context restore.
> -	 */
> -	batch = gen8_emit_pipe_control(batch,
> -				       PIPE_CONTROL_CS_STALL,
> -				       0);
> -	/*
> -	 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
> -	 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
> -	 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
> -	 * confusing. Since gen8_emit_pipe_control() already advances the
> -	 * batch by 6 dwords, we advance the other 10 here, completing a
> -	 * cacheline. It's not clear if the workaround requires this padding
> -	 * before other commands, or if it's just the regular padding we would
> -	 * already have for the workaround bb, so leave it here for now.
> -	 */
> -	for (i = 0; i < 10; i++)
> -		*batch++ = MI_NOOP;
> -
> -	/* Pad to end of cacheline */
> -	while ((unsigned long)batch % CACHELINE_BYTES)
> -		*batch++ = MI_NOOP;
> -
> -	return batch;
> -}
> -
>  #define CTX_WA_BB_SIZE (PAGE_SIZE)
>  
>  static int lrc_create_wa_ctx(struct intel_engine_cs *engine)
> @@ -1534,10 +1498,6 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
>  	case 12:
>  	case 11:
>  		return;
> -	case 10:
> -		wa_bb_fn[0] = gen10_init_indirectctx_bb;
> -		wa_bb_fn[1] = NULL;
> -		break;
>  	case 9:
>  		wa_bb_fn[0] = gen9_init_indirectctx_bb;
>  		wa_bb_fn[1] = NULL;
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 259d7eb4e165..a7d13fe35b2e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>  	enum intel_engine_id id;
>  
>  	/* 2b: Program RC6 thresholds.*/
> -	if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {
> +	if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
>  		set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
>  		set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>  	} else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 06e9a8ed4e03..2e03ad80f3cf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps)
>  
>  	rps->efficient_freq = rps->rp1_freq;
>  	if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
> -	    IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> +	    IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
>  		u32 ddcc_status = 0;
>  
>  		if (sandybridge_pcode_read(i915,
> @@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps)
>  					rps->max_freq);
>  	}
>  
> -	if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> +	if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
>  		/* Store the frequency values in 16.66 MHZ units, which is
>  		 * the natural hardware unit for SKL
>  		 */
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> index 714fe8495775..5e7b09c5e36f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> @@ -50,7 +50,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
>  #undef SS_MAX
>  }
>  
> -static void gen10_sseu_device_status(struct intel_gt *gt,
> +static void gen11_sseu_device_status(struct intel_gt *gt,
>  				     struct sseu_dev_info *sseu)
>  {
>  #define SS_MAX 6
> @@ -267,8 +267,8 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt *gt)
>  			bdw_sseu_device_status(gt, &sseu);
>  		else if (GRAPHICS_VER(i915) == 9)
>  			gen9_sseu_device_status(gt, &sseu);
> -		else if (GRAPHICS_VER(i915) >= 10)
> -			gen10_sseu_device_status(gt, &sseu);
> +		else if (GRAPHICS_VER(i915) >= 11)
> +			gen11_sseu_device_status(gt, &sseu);
>  	}
>  
>  	i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), &sseu);
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index cc2c05e18206..e5c2fdfc20e3 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -1055,7 +1055,7 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
>  {
>  	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
>  
> -	if (GRAPHICS_VER(dev_priv) == 9 || GRAPHICS_VER(dev_priv) == 10) {
> +	if (GRAPHICS_VER(dev_priv) == 9) {
>  		u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
>  			GAMW_ECO_ENABLE_64K_IPS_FIELD;
>  
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 0529576f069c..44969f5dde50 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -538,20 +538,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
>  			    rp_state_cap >> 16) & 0xff;
>  		max_freq *= (IS_GEN9_BC(dev_priv) ||
> -			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
> +			     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
>  		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
>  			   intel_gpu_freq(rps, max_freq));
>  
>  		max_freq = (rp_state_cap & 0xff00) >> 8;
>  		max_freq *= (IS_GEN9_BC(dev_priv) ||
> -			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
> +			     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
>  		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
>  			   intel_gpu_freq(rps, max_freq));
>  
>  		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
>  			    rp_state_cap >> 0) & 0xff;
>  		max_freq *= (IS_GEN9_BC(dev_priv) ||
> -			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
> +			     GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
>  		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
>  			   intel_gpu_freq(rps, max_freq));
>  		seq_printf(m, "Max overclocked frequency: %dMHz\n",
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e3c8283d770c..f9671686bf62 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1649,7 +1649,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
>  
>  #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
> -#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
> +#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
>  					IS_GEMINILAKE(dev_priv) || \
>  					IS_KABYLAKE(dev_priv))
>  
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 108774d651d9..2f01b8c0284c 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1256,7 +1256,6 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
>  
>  	case 8:
>  	case 9:
> -	case 10:
>  		if (intel_engine_uses_guc(ce->engine)) {
>  			/*
>  			 * When using GuC, the context descriptor we write in
> @@ -2589,7 +2588,7 @@ static void gen8_disable_metric_set(struct i915_perf_stream *stream)
>  	intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
>  }
>  
> -static void gen10_disable_metric_set(struct i915_perf_stream *stream)
> +static void gen11_disable_metric_set(struct i915_perf_stream *stream)
>  {
>  	struct intel_uncore *uncore = stream->uncore;
>  
> @@ -3896,7 +3895,7 @@ static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
>  	       REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));
>  }
>  
> -static bool gen10_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
> +static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
>  {
>  	return gen8_is_valid_mux_addr(perf, addr) ||
>  	       REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
> @@ -4403,27 +4402,23 @@ void i915_perf_init(struct drm_i915_private *i915)
>  
>  				perf->gen8_valid_ctx_bit = BIT(16);
>  			}
> -		} else if (IS_GRAPHICS_VER(i915, 10, 11)) {
> +		} else if (GRAPHICS_VER(i915) == 11) {
>  			perf->ops.is_valid_b_counter_reg =
>  				gen7_is_valid_b_counter_addr;
>  			perf->ops.is_valid_mux_reg =
> -				gen10_is_valid_mux_addr;
> +				gen11_is_valid_mux_addr;
>  			perf->ops.is_valid_flex_reg =
>  				gen8_is_valid_flex_addr;
>  
>  			perf->ops.oa_enable = gen8_oa_enable;
>  			perf->ops.oa_disable = gen8_oa_disable;
>  			perf->ops.enable_metric_set = gen8_enable_metric_set;
> -			perf->ops.disable_metric_set = gen10_disable_metric_set;
> +			perf->ops.disable_metric_set = gen11_disable_metric_set;
>  			perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
>  
> -			if (GRAPHICS_VER(i915) == 10) {
> -				perf->ctx_oactxctrl_offset = 0x128;
> -				perf->ctx_flexeu0_offset = 0x3de;
> -			} else {
> -				perf->ctx_oactxctrl_offset = 0x124;
> -				perf->ctx_flexeu0_offset = 0x78e;
> -			}
> +			perf->ctx_oactxctrl_offset = 0x124;
> +			perf->ctx_flexeu0_offset = 0x78e;
> +
>  			perf->gen8_valid_ctx_bit = BIT(16);
>  		} else if (GRAPHICS_VER(i915) == 12) {
>  			perf->ops.is_valid_b_counter_reg =
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 2893a8659a8b..4319ae020c86 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -265,7 +265,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_scalers[pipe] = 0;
> -	else if (GRAPHICS_VER(dev_priv) >= 10) {
> +	else if (GRAPHICS_VER(dev_priv) >= 11) {
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_scalers[pipe] = 2;
>  	} else if (GRAPHICS_VER(dev_priv) == 9) {
> @@ -282,7 +282,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  	else if (GRAPHICS_VER(dev_priv) >= 11)
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_sprites[pipe] = 6;
> -	else if (GRAPHICS_VER(dev_priv) == 10 || IS_GEMINILAKE(dev_priv))
> +	else if (IS_GEMINILAKE(dev_priv))
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_sprites[pipe] = 3;
>  	else if (IS_BROXTON(dev_priv)) {
> -- 
> 2.31.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [PATCH 28/30] drm/i915: rename/remove CNL registers

[Lucas De Marchi]

Remove registers that are not used anymore due to CNL removal and rename
those that are.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 192 ++++++-----------------
 drivers/gpu/drm/i915/intel_device_info.c |   2 +-
 2 files changed, 48 insertions(+), 146 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8782d1723254..925cbdb53712 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1877,7 +1877,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
 
 /*
- * CNL/ICL Port/COMBO-PHY Registers
+ * ICL Port/COMBO-PHY Registers
  */
 #define _ICL_COMBOPHY_A			0x162000
 #define _ICL_COMBOPHY_B			0x6C000
@@ -1891,11 +1891,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 					      _RKL_COMBOPHY_D, \
 					      _ADL_COMBOPHY_E)
 
-/* CNL/ICL Port CL_DW registers */
+/* ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
 					 4 * (dw))
 
-#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
 #define ICL_PORT_CL_DW5(phy)		_MMIO(_ICL_PORT_CL_DW(5, phy))
 #define   CL_POWER_DOWN_ENABLE		(1 << 4)
 #define   SUS_CLOCK_CONFIG		(3 << 0)
@@ -1920,19 +1919,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define ICL_PORT_CL_DW12(phy)		_MMIO(_ICL_PORT_CL_DW(12, phy))
 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
 
-/* CNL/ICL Port COMP_DW registers */
+/* ICL Port COMP_DW registers */
 #define _ICL_PORT_COMP			0x100
 #define _ICL_PORT_COMP_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
 					 _ICL_PORT_COMP + 4 * (dw))
 
-#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
 #define ICL_PORT_COMP_DW0(phy)		_MMIO(_ICL_PORT_COMP_DW(0, phy))
 #define   COMP_INIT			(1 << 31)
 
-#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
 #define ICL_PORT_COMP_DW1(phy)		_MMIO(_ICL_PORT_COMP_DW(1, phy))
 
-#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
 #define ICL_PORT_COMP_DW3(phy)		_MMIO(_ICL_PORT_COMP_DW(3, phy))
 #define   PROCESS_INFO_DOT_0		(0 << 26)
 #define   PROCESS_INFO_DOT_1		(1 << 26)
@@ -1948,38 +1944,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define ICL_PORT_COMP_DW8(phy)		_MMIO(_ICL_PORT_COMP_DW(8, phy))
 #define   IREFGEN			(1 << 24)
 
-#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
 #define ICL_PORT_COMP_DW9(phy)		_MMIO(_ICL_PORT_COMP_DW(9, phy))
 
-#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
 #define ICL_PORT_COMP_DW10(phy)		_MMIO(_ICL_PORT_COMP_DW(10, phy))
 
-/* CNL/ICL Port PCS registers */
-#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
-#define _CNL_PORT_PCS_DW1_GRP_B		0x162384
-#define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
-#define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
-#define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
-#define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
-#define _CNL_PORT_PCS_DW1_LN0_B		0x162604
-#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
-#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
-#define _CNL_PORT_PCS_DW1_LN0_F		0x162804
-#define CNL_PORT_PCS_DW1_GRP(phy)	_MMIO(_PICK(phy, \
-						    _CNL_PORT_PCS_DW1_GRP_AE, \
-						    _CNL_PORT_PCS_DW1_GRP_B, \
-						    _CNL_PORT_PCS_DW1_GRP_C, \
-						    _CNL_PORT_PCS_DW1_GRP_D, \
-						    _CNL_PORT_PCS_DW1_GRP_AE, \
-						    _CNL_PORT_PCS_DW1_GRP_F))
-#define CNL_PORT_PCS_DW1_LN0(phy)	_MMIO(_PICK(phy, \
-						    _CNL_PORT_PCS_DW1_LN0_AE, \
-						    _CNL_PORT_PCS_DW1_LN0_B, \
-						    _CNL_PORT_PCS_DW1_LN0_C, \
-						    _CNL_PORT_PCS_DW1_LN0_D, \
-						    _CNL_PORT_PCS_DW1_LN0_AE, \
-						    _CNL_PORT_PCS_DW1_LN0_F))
-
+/* ICL Port PCS registers */
 #define _ICL_PORT_PCS_AUX		0x300
 #define _ICL_PORT_PCS_GRP		0x600
 #define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
@@ -1998,34 +1967,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   LATENCY_OPTIM_MASK		(0x3 << 2)
 #define   LATENCY_OPTIM_VAL(x)		((x) << 2)
 
-/* CNL/ICL Port TX registers */
-#define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
-#define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
-#define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
-#define _CNL_PORT_TX_D_GRP_OFFSET		0x162BC0
-#define _CNL_PORT_TX_F_GRP_OFFSET		0x162A40
-#define _CNL_PORT_TX_AE_LN0_OFFSET		0x162440
-#define _CNL_PORT_TX_B_LN0_OFFSET		0x162640
-#define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40
-#define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40
-#define _CNL_PORT_TX_F_LN0_OFFSET		0x162840
-#define _CNL_PORT_TX_DW_GRP(dw, port)	(_PICK((port), \
-					       _CNL_PORT_TX_AE_GRP_OFFSET, \
-					       _CNL_PORT_TX_B_GRP_OFFSET, \
-					       _CNL_PORT_TX_B_GRP_OFFSET, \
-					       _CNL_PORT_TX_D_GRP_OFFSET, \
-					       _CNL_PORT_TX_AE_GRP_OFFSET, \
-					       _CNL_PORT_TX_F_GRP_OFFSET) + \
-					       4 * (dw))
-#define _CNL_PORT_TX_DW_LN0(dw, port)	(_PICK((port), \
-					       _CNL_PORT_TX_AE_LN0_OFFSET, \
-					       _CNL_PORT_TX_B_LN0_OFFSET, \
-					       _CNL_PORT_TX_B_LN0_OFFSET, \
-					       _CNL_PORT_TX_D_LN0_OFFSET, \
-					       _CNL_PORT_TX_AE_LN0_OFFSET, \
-					       _CNL_PORT_TX_F_LN0_OFFSET) + \
-					       4 * (dw))
-
+/* ICL Port TX registers */
 #define _ICL_PORT_TX_AUX		0x380
 #define _ICL_PORT_TX_GRP		0x680
 #define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
@@ -2037,8 +1979,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
 					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
 
-#define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(2, port))
-#define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(2, port))
 #define ICL_PORT_TX_DW2_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
 #define ICL_PORT_TX_DW2_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
 #define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
@@ -2051,13 +1991,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   RCOMP_SCALAR(x)		((x) << 0)
 #define   RCOMP_SCALAR_MASK		(0xFF << 0)
 
-#define _CNL_PORT_TX_DW4_LN0_AE		0x162450
-#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
-#define CNL_PORT_TX_DW4_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
-#define CNL_PORT_TX_DW4_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
-#define CNL_PORT_TX_DW4_LN(ln, port)   _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
-					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
-						    _CNL_PORT_TX_DW4_LN0_AE)))
 #define ICL_PORT_TX_DW4_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
 #define ICL_PORT_TX_DW4_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
 #define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
@@ -2070,8 +2003,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   CURSOR_COEFF(x)		((x) << 0)
 #define   CURSOR_COEFF_MASK		(0x3F << 0)
 
-#define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(5, port))
-#define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(5, port))
 #define ICL_PORT_TX_DW5_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
 #define ICL_PORT_TX_DW5_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
 #define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
@@ -2083,8 +2014,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   RTERM_SELECT(x)		((x) << 3)
 #define   RTERM_SELECT_MASK		(0x7 << 3)
 
-#define CNL_PORT_TX_DW7_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
-#define CNL_PORT_TX_DW7_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
 #define ICL_PORT_TX_DW7_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
 #define ICL_PORT_TX_DW7_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
 #define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
@@ -8135,7 +8064,6 @@ enum {
 #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
 
 #define CHICKEN_MISC_2		_MMIO(0x42084)
-#define  CNL_COMP_PWR_DOWN	(1 << 23)
 #define  KBL_ARB_FILL_SPARE_14	REG_BIT(14)
 #define  KBL_ARB_FILL_SPARE_13	REG_BIT(13)
 #define  GLK_CL2_PWR_DOWN	(1 << 12)
@@ -8175,7 +8103,7 @@ enum {
 					    [TRANSCODER_D] = _CHICKEN_TRANS_D))
 #define  HSW_FRAME_START_DELAY_MASK	(3 << 27)
 #define  HSW_FRAME_START_DELAY(x)	((x) << 27) /* 0-3 */
-#define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1 << 25) /* GLK and CNL+ */
+#define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1 << 25) /* GLK */
 #define  DDI_TRAINING_OVERRIDE_ENABLE	(1 << 19)
 #define  DDI_TRAINING_OVERRIDE_VALUE	(1 << 18)
 #define  DDIE_TRAINING_OVERRIDE_ENABLE	(1 << 17) /* CHICKEN_TRANS_A only */
@@ -8241,7 +8169,6 @@ enum {
 #define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)
 #define   ICL_DELAY_PMRSP		(1 << 22)
 #define   MASK_WAKEMEM			(1 << 13)
-#define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
 
 #define GEN11_CHICKEN_DCPR_2			_MMIO(0x46434)
 #define   DCPR_MASK_MAXLATENCY_MEMUP_CLR	REG_BIT(27)
@@ -8262,10 +8189,9 @@ enum {
 #define   SKL_DFSM_PIPE_B_DISABLE	(1 << 21)
 #define   SKL_DFSM_PIPE_C_DISABLE	(1 << 28)
 #define   TGL_DFSM_PIPE_D_DISABLE	(1 << 22)
-#define   CNL_DFSM_DISPLAY_DSC_DISABLE	(1 << 7)
+#define   GLK_DFSM_DISPLAY_DSC_DISABLE	(1 << 7)
 
 #define SKL_DSSM				_MMIO(0x51004)
-#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK		(7 << 29)
 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
@@ -8364,7 +8290,6 @@ enum {
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)
-#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
 #define ICL_HDC_MODE				_MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
@@ -9540,7 +9465,6 @@ enum {
 #define   HSW_SAMPLE_C_PERFORMANCE	(1 << 9)
 #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1 << 8)
 #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1 << 5)
-#define   CNL_FAST_ANISO_L1_BANKING_FIX	(1 << 4)
 #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1 << 1)
 
 #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
@@ -9721,15 +9645,12 @@ enum {
 /* HSW/BDW power well */
 #define   HSW_PW_CTL_IDX_GLOBAL			15
 
-/* SKL/BXT/GLK/CNL power wells */
+/* SKL/BXT/GLK power wells */
 #define   SKL_PW_CTL_IDX_PW_2			15
 #define   SKL_PW_CTL_IDX_PW_1			14
-#define   CNL_PW_CTL_IDX_AUX_F			12
-#define   CNL_PW_CTL_IDX_AUX_D			11
 #define   GLK_PW_CTL_IDX_AUX_C			10
 #define   GLK_PW_CTL_IDX_AUX_B			9
 #define   GLK_PW_CTL_IDX_AUX_A			8
-#define   CNL_PW_CTL_IDX_DDI_F			6
 #define   SKL_PW_CTL_IDX_DDI_D			4
 #define   SKL_PW_CTL_IDX_DDI_C			3
 #define   SKL_PW_CTL_IDX_DDI_B			2
@@ -10127,11 +10048,11 @@ enum skl_power_gate {
 #define  TRANS_DDI_BPC_10		(1 << 20)
 #define  TRANS_DDI_BPC_6		(2 << 20)
 #define  TRANS_DDI_BPC_12		(3 << 20)
-#define  TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK	REG_GENMASK(19, 18) /* bdw-cnl */
+#define  TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK	REG_GENMASK(19, 18)
 #define  TRANS_DDI_PORT_SYNC_MASTER_SELECT(x)	REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
 #define  TRANS_DDI_PVSYNC		(1 << 17)
 #define  TRANS_DDI_PHSYNC		(1 << 16)
-#define  TRANS_DDI_PORT_SYNC_ENABLE	REG_BIT(15) /* bdw-cnl */
+#define  TRANS_DDI_PORT_SYNC_ENABLE	REG_BIT(15)
 #define  TRANS_DDI_EDP_INPUT_MASK	(7 << 12)
 #define  TRANS_DDI_EDP_INPUT_A_ON	(0 << 12)
 #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4 << 12)
@@ -10487,17 +10408,6 @@ enum skl_power_gate {
 #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
 #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
 
-/*
- * CNL Clocks
- */
-#define DPCLKA_CFGCR0				_MMIO(0x6C200)
-#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
-						      (port) + 10))
-#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
-						(port) * 2)
-#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
-#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
-
 /* ICL Clocks */
 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24, 4, 5))
@@ -10730,60 +10640,52 @@ enum skl_power_gate {
 						   _MG_PLL_TDC_COLDST_BIAS_PORT1, \
 						   _MG_PLL_TDC_COLDST_BIAS_PORT2)
 
-#define _CNL_DPLL0_CFGCR0		0x6C000
-#define _CNL_DPLL1_CFGCR0		0x6C080
-#define  DPLL_CFGCR0_HDMI_MODE		(1 << 30)
-#define  DPLL_CFGCR0_SSC_ENABLE		(1 << 29)
-#define  DPLL_CFGCR0_SSC_ENABLE_ICL	(1 << 25)
-#define  DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
-#define  DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
-#define  DPLL_CFGCR0_LINK_RATE_1350	(1 << 25)
-#define  DPLL_CFGCR0_LINK_RATE_810	(2 << 25)
-#define  DPLL_CFGCR0_LINK_RATE_1620	(3 << 25)
-#define  DPLL_CFGCR0_LINK_RATE_1080	(4 << 25)
-#define  DPLL_CFGCR0_LINK_RATE_2160	(5 << 25)
-#define  DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
-#define  DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
-#define  DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
-#define  DPLL_CFGCR0_DCO_FRACTION_SHIFT	(10)
-#define  DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
-#define  DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
-#define CNL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
-
-#define _CNL_DPLL0_CFGCR1		0x6C004
-#define _CNL_DPLL1_CFGCR1		0x6C084
-#define  DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
-#define  DPLL_CFGCR1_QDIV_RATIO_SHIFT	(10)
-#define  DPLL_CFGCR1_QDIV_RATIO(x)	((x) << 10)
-#define  DPLL_CFGCR1_QDIV_MODE_SHIFT	(9)
-#define  DPLL_CFGCR1_QDIV_MODE(x)	((x) << 9)
-#define  DPLL_CFGCR1_KDIV_MASK		(7 << 6)
-#define  DPLL_CFGCR1_KDIV_SHIFT		(6)
-#define  DPLL_CFGCR1_KDIV(x)		((x) << 6)
-#define  DPLL_CFGCR1_KDIV_1		(1 << 6)
-#define  DPLL_CFGCR1_KDIV_2		(2 << 6)
-#define  DPLL_CFGCR1_KDIV_3		(4 << 6)
-#define  DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
-#define  DPLL_CFGCR1_PDIV_SHIFT		(2)
-#define  DPLL_CFGCR1_PDIV(x)		((x) << 2)
-#define  DPLL_CFGCR1_PDIV_2		(1 << 2)
-#define  DPLL_CFGCR1_PDIV_3		(2 << 2)
-#define  DPLL_CFGCR1_PDIV_5		(4 << 2)
-#define  DPLL_CFGCR1_PDIV_7		(8 << 2)
-#define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
-#define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
-#define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
-#define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
-
 #define _ICL_DPLL0_CFGCR0		0x164000
 #define _ICL_DPLL1_CFGCR0		0x164080
 #define ICL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
 						  _ICL_DPLL1_CFGCR0)
+#define   DPLL_CFGCR0_HDMI_MODE		(1 << 30)
+#define   DPLL_CFGCR0_SSC_ENABLE	(1 << 29)
+#define   DPLL_CFGCR0_SSC_ENABLE_ICL	(1 << 25)
+#define   DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
+#define   DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
+#define   DPLL_CFGCR0_LINK_RATE_1350	(1 << 25)
+#define   DPLL_CFGCR0_LINK_RATE_810	(2 << 25)
+#define   DPLL_CFGCR0_LINK_RATE_1620	(3 << 25)
+#define   DPLL_CFGCR0_LINK_RATE_1080	(4 << 25)
+#define   DPLL_CFGCR0_LINK_RATE_2160	(5 << 25)
+#define   DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
+#define   DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
+#define   DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
+#define   DPLL_CFGCR0_DCO_FRACTION_SHIFT	(10)
+#define   DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
+#define   DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
 
 #define _ICL_DPLL0_CFGCR1		0x164004
 #define _ICL_DPLL1_CFGCR1		0x164084
 #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
 						  _ICL_DPLL1_CFGCR1)
+#define   DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
+#define   DPLL_CFGCR1_QDIV_RATIO_SHIFT	(10)
+#define   DPLL_CFGCR1_QDIV_RATIO(x)	((x) << 10)
+#define   DPLL_CFGCR1_QDIV_MODE_SHIFT	(9)
+#define   DPLL_CFGCR1_QDIV_MODE(x)	((x) << 9)
+#define   DPLL_CFGCR1_KDIV_MASK		(7 << 6)
+#define   DPLL_CFGCR1_KDIV_SHIFT		(6)
+#define   DPLL_CFGCR1_KDIV(x)		((x) << 6)
+#define   DPLL_CFGCR1_KDIV_1		(1 << 6)
+#define   DPLL_CFGCR1_KDIV_2		(2 << 6)
+#define   DPLL_CFGCR1_KDIV_3		(4 << 6)
+#define   DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
+#define   DPLL_CFGCR1_PDIV_SHIFT		(2)
+#define   DPLL_CFGCR1_PDIV(x)		((x) << 2)
+#define   DPLL_CFGCR1_PDIV_2		(1 << 2)
+#define   DPLL_CFGCR1_PDIV_3		(2 << 2)
+#define   DPLL_CFGCR1_PDIV_5		(4 << 2)
+#define   DPLL_CFGCR1_PDIV_7		(8 << 2)
+#define   DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
+#define   DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
+#define   TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
 
 #define _TGL_DPLL0_CFGCR0		0x164284
 #define _TGL_DPLL1_CFGCR0		0x16428C
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 4319ae020c86..ffe3b5d89a63 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -365,7 +365,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 			info->display.has_dmc = 0;
 
 		if (DISPLAY_VER(dev_priv) >= 10 &&
-		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
+		    (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
 			info->display.has_dsc = 0;
 	}
 
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 28/30] drm/i915: rename/remove CNL registers

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:12PM -0700, Lucas De Marchi wrote:
> Remove registers that are not used anymore due to CNL removal and rename
> those that are.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 192 ++++++-----------------
>  drivers/gpu/drm/i915/intel_device_info.c |   2 +-
>  2 files changed, 48 insertions(+), 146 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8782d1723254..925cbdb53712 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1877,7 +1877,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
>  
>  /*
> - * CNL/ICL Port/COMBO-PHY Registers
> + * ICL Port/COMBO-PHY Registers
>   */
>  #define _ICL_COMBOPHY_A			0x162000
>  #define _ICL_COMBOPHY_B			0x6C000
> @@ -1891,11 +1891,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  					      _RKL_COMBOPHY_D, \
>  					      _ADL_COMBOPHY_E)
>  
> -/* CNL/ICL Port CL_DW registers */
> +/* ICL Port CL_DW registers */
>  #define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
>  					 4 * (dw))
>  
> -#define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
>  #define ICL_PORT_CL_DW5(phy)		_MMIO(_ICL_PORT_CL_DW(5, phy))
>  #define   CL_POWER_DOWN_ENABLE		(1 << 4)
>  #define   SUS_CLOCK_CONFIG		(3 << 0)
> @@ -1920,19 +1919,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define ICL_PORT_CL_DW12(phy)		_MMIO(_ICL_PORT_CL_DW(12, phy))
>  #define   ICL_LANE_ENABLE_AUX		(1 << 0)
>  
> -/* CNL/ICL Port COMP_DW registers */
> +/* ICL Port COMP_DW registers */
>  #define _ICL_PORT_COMP			0x100
>  #define _ICL_PORT_COMP_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
>  					 _ICL_PORT_COMP + 4 * (dw))
>  
> -#define CNL_PORT_COMP_DW0		_MMIO(0x162100)
>  #define ICL_PORT_COMP_DW0(phy)		_MMIO(_ICL_PORT_COMP_DW(0, phy))
>  #define   COMP_INIT			(1 << 31)
>  
> -#define CNL_PORT_COMP_DW1		_MMIO(0x162104)
>  #define ICL_PORT_COMP_DW1(phy)		_MMIO(_ICL_PORT_COMP_DW(1, phy))
>  
> -#define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
>  #define ICL_PORT_COMP_DW3(phy)		_MMIO(_ICL_PORT_COMP_DW(3, phy))
>  #define   PROCESS_INFO_DOT_0		(0 << 26)
>  #define   PROCESS_INFO_DOT_1		(1 << 26)
> @@ -1948,38 +1944,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define ICL_PORT_COMP_DW8(phy)		_MMIO(_ICL_PORT_COMP_DW(8, phy))
>  #define   IREFGEN			(1 << 24)
>  
> -#define CNL_PORT_COMP_DW9		_MMIO(0x162124)
>  #define ICL_PORT_COMP_DW9(phy)		_MMIO(_ICL_PORT_COMP_DW(9, phy))
>  
> -#define CNL_PORT_COMP_DW10		_MMIO(0x162128)
>  #define ICL_PORT_COMP_DW10(phy)		_MMIO(_ICL_PORT_COMP_DW(10, phy))
>  
> -/* CNL/ICL Port PCS registers */
> -#define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
> -#define _CNL_PORT_PCS_DW1_GRP_B		0x162384
> -#define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
> -#define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
> -#define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
> -#define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
> -#define _CNL_PORT_PCS_DW1_LN0_B		0x162604
> -#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
> -#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
> -#define _CNL_PORT_PCS_DW1_LN0_F		0x162804
> -#define CNL_PORT_PCS_DW1_GRP(phy)	_MMIO(_PICK(phy, \
> -						    _CNL_PORT_PCS_DW1_GRP_AE, \
> -						    _CNL_PORT_PCS_DW1_GRP_B, \
> -						    _CNL_PORT_PCS_DW1_GRP_C, \
> -						    _CNL_PORT_PCS_DW1_GRP_D, \
> -						    _CNL_PORT_PCS_DW1_GRP_AE, \
> -						    _CNL_PORT_PCS_DW1_GRP_F))
> -#define CNL_PORT_PCS_DW1_LN0(phy)	_MMIO(_PICK(phy, \
> -						    _CNL_PORT_PCS_DW1_LN0_AE, \
> -						    _CNL_PORT_PCS_DW1_LN0_B, \
> -						    _CNL_PORT_PCS_DW1_LN0_C, \
> -						    _CNL_PORT_PCS_DW1_LN0_D, \
> -						    _CNL_PORT_PCS_DW1_LN0_AE, \
> -						    _CNL_PORT_PCS_DW1_LN0_F))
> -
> +/* ICL Port PCS registers */
>  #define _ICL_PORT_PCS_AUX		0x300
>  #define _ICL_PORT_PCS_GRP		0x600
>  #define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
> @@ -1998,34 +1967,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define   LATENCY_OPTIM_MASK		(0x3 << 2)
>  #define   LATENCY_OPTIM_VAL(x)		((x) << 2)
>  
> -/* CNL/ICL Port TX registers */
> -#define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
> -#define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
> -#define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
> -#define _CNL_PORT_TX_D_GRP_OFFSET		0x162BC0
> -#define _CNL_PORT_TX_F_GRP_OFFSET		0x162A40
> -#define _CNL_PORT_TX_AE_LN0_OFFSET		0x162440
> -#define _CNL_PORT_TX_B_LN0_OFFSET		0x162640
> -#define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40
> -#define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40
> -#define _CNL_PORT_TX_F_LN0_OFFSET		0x162840
> -#define _CNL_PORT_TX_DW_GRP(dw, port)	(_PICK((port), \
> -					       _CNL_PORT_TX_AE_GRP_OFFSET, \
> -					       _CNL_PORT_TX_B_GRP_OFFSET, \
> -					       _CNL_PORT_TX_B_GRP_OFFSET, \
> -					       _CNL_PORT_TX_D_GRP_OFFSET, \
> -					       _CNL_PORT_TX_AE_GRP_OFFSET, \
> -					       _CNL_PORT_TX_F_GRP_OFFSET) + \
> -					       4 * (dw))
> -#define _CNL_PORT_TX_DW_LN0(dw, port)	(_PICK((port), \
> -					       _CNL_PORT_TX_AE_LN0_OFFSET, \
> -					       _CNL_PORT_TX_B_LN0_OFFSET, \
> -					       _CNL_PORT_TX_B_LN0_OFFSET, \
> -					       _CNL_PORT_TX_D_LN0_OFFSET, \
> -					       _CNL_PORT_TX_AE_LN0_OFFSET, \
> -					       _CNL_PORT_TX_F_LN0_OFFSET) + \
> -					       4 * (dw))
> -
> +/* ICL Port TX registers */
>  #define _ICL_PORT_TX_AUX		0x380
>  #define _ICL_PORT_TX_GRP		0x680
>  #define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
> @@ -2037,8 +1979,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
>  					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
>  
> -#define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(2, port))
> -#define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(2, port))
>  #define ICL_PORT_TX_DW2_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
>  #define ICL_PORT_TX_DW2_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
>  #define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
> @@ -2051,13 +1991,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define   RCOMP_SCALAR(x)		((x) << 0)
>  #define   RCOMP_SCALAR_MASK		(0xFF << 0)
>  
> -#define _CNL_PORT_TX_DW4_LN0_AE		0x162450
> -#define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
> -#define CNL_PORT_TX_DW4_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
> -#define CNL_PORT_TX_DW4_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
> -#define CNL_PORT_TX_DW4_LN(ln, port)   _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
> -					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
> -						    _CNL_PORT_TX_DW4_LN0_AE)))
>  #define ICL_PORT_TX_DW4_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
>  #define ICL_PORT_TX_DW4_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
>  #define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
> @@ -2070,8 +2003,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define   CURSOR_COEFF(x)		((x) << 0)
>  #define   CURSOR_COEFF_MASK		(0x3F << 0)
>  
> -#define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(5, port))
> -#define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(5, port))
>  #define ICL_PORT_TX_DW5_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
>  #define ICL_PORT_TX_DW5_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
>  #define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
> @@ -2083,8 +2014,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define   RTERM_SELECT(x)		((x) << 3)
>  #define   RTERM_SELECT_MASK		(0x7 << 3)
>  
> -#define CNL_PORT_TX_DW7_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
> -#define CNL_PORT_TX_DW7_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
>  #define ICL_PORT_TX_DW7_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
>  #define ICL_PORT_TX_DW7_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
>  #define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
> @@ -8135,7 +8064,6 @@ enum {
>  #define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)
>  
>  #define CHICKEN_MISC_2		_MMIO(0x42084)
> -#define  CNL_COMP_PWR_DOWN	(1 << 23)
>  #define  KBL_ARB_FILL_SPARE_14	REG_BIT(14)
>  #define  KBL_ARB_FILL_SPARE_13	REG_BIT(13)
>  #define  GLK_CL2_PWR_DOWN	(1 << 12)
> @@ -8175,7 +8103,7 @@ enum {
>  					    [TRANSCODER_D] = _CHICKEN_TRANS_D))
>  #define  HSW_FRAME_START_DELAY_MASK	(3 << 27)
>  #define  HSW_FRAME_START_DELAY(x)	((x) << 27) /* 0-3 */
> -#define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1 << 25) /* GLK and CNL+ */
> +#define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1 << 25) /* GLK */
>  #define  DDI_TRAINING_OVERRIDE_ENABLE	(1 << 19)
>  #define  DDI_TRAINING_OVERRIDE_VALUE	(1 << 18)
>  #define  DDIE_TRAINING_OVERRIDE_ENABLE	(1 << 17) /* CHICKEN_TRANS_A only */
> @@ -8241,7 +8169,6 @@ enum {
>  #define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)
>  #define   ICL_DELAY_PMRSP		(1 << 22)
>  #define   MASK_WAKEMEM			(1 << 13)
> -#define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
>  #define GEN11_CHICKEN_DCPR_2			_MMIO(0x46434)
>  #define   DCPR_MASK_MAXLATENCY_MEMUP_CLR	REG_BIT(27)
> @@ -8262,10 +8189,9 @@ enum {
>  #define   SKL_DFSM_PIPE_B_DISABLE	(1 << 21)
>  #define   SKL_DFSM_PIPE_C_DISABLE	(1 << 28)
>  #define   TGL_DFSM_PIPE_D_DISABLE	(1 << 22)
> -#define   CNL_DFSM_DISPLAY_DSC_DISABLE	(1 << 7)
> +#define   GLK_DFSM_DISPLAY_DSC_DISABLE	(1 << 7)
>  
>  #define SKL_DSSM				_MMIO(0x51004)
> -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
>  #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK		(7 << 29)
>  #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
>  #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz	(1 << 29)
> @@ -8364,7 +8290,6 @@ enum {
>  
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				_MMIO(0x7300)
> -#define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
>  #define ICL_HDC_MODE				_MMIO(0xE5F4)
>  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1 << 15)
>  #define  HDC_FENCE_DEST_SLM_DISABLE		(1 << 14)
> @@ -9540,7 +9465,6 @@ enum {
>  #define   HSW_SAMPLE_C_PERFORMANCE	(1 << 9)
>  #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1 << 8)
>  #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1 << 5)
> -#define   CNL_FAST_ANISO_L1_BANKING_FIX	(1 << 4)
>  #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1 << 1)
>  
>  #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
> @@ -9721,15 +9645,12 @@ enum {
>  /* HSW/BDW power well */
>  #define   HSW_PW_CTL_IDX_GLOBAL			15
>  
> -/* SKL/BXT/GLK/CNL power wells */
> +/* SKL/BXT/GLK power wells */
>  #define   SKL_PW_CTL_IDX_PW_2			15
>  #define   SKL_PW_CTL_IDX_PW_1			14
> -#define   CNL_PW_CTL_IDX_AUX_F			12
> -#define   CNL_PW_CTL_IDX_AUX_D			11
>  #define   GLK_PW_CTL_IDX_AUX_C			10
>  #define   GLK_PW_CTL_IDX_AUX_B			9
>  #define   GLK_PW_CTL_IDX_AUX_A			8
> -#define   CNL_PW_CTL_IDX_DDI_F			6
>  #define   SKL_PW_CTL_IDX_DDI_D			4
>  #define   SKL_PW_CTL_IDX_DDI_C			3
>  #define   SKL_PW_CTL_IDX_DDI_B			2
> @@ -10127,11 +10048,11 @@ enum skl_power_gate {
>  #define  TRANS_DDI_BPC_10		(1 << 20)
>  #define  TRANS_DDI_BPC_6		(2 << 20)
>  #define  TRANS_DDI_BPC_12		(3 << 20)
> -#define  TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK	REG_GENMASK(19, 18) /* bdw-cnl */
> +#define  TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK	REG_GENMASK(19, 18)
>  #define  TRANS_DDI_PORT_SYNC_MASTER_SELECT(x)	REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
>  #define  TRANS_DDI_PVSYNC		(1 << 17)
>  #define  TRANS_DDI_PHSYNC		(1 << 16)
> -#define  TRANS_DDI_PORT_SYNC_ENABLE	REG_BIT(15) /* bdw-cnl */
> +#define  TRANS_DDI_PORT_SYNC_ENABLE	REG_BIT(15)
>  #define  TRANS_DDI_EDP_INPUT_MASK	(7 << 12)
>  #define  TRANS_DDI_EDP_INPUT_A_ON	(0 << 12)
>  #define  TRANS_DDI_EDP_INPUT_A_ONOFF	(4 << 12)
> @@ -10487,17 +10408,6 @@ enum skl_power_gate {
>  #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
>  #define DPLL_CFGCR2(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
>  
> -/*
> - * CNL Clocks
> - */
> -#define DPCLKA_CFGCR0				_MMIO(0x6C200)
> -#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
> -						      (port) + 10))
> -#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
> -						(port) * 2)
> -#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> -#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> -
>  /* ICL Clocks */
>  #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
>  #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24, 4, 5))
> @@ -10730,60 +10640,52 @@ enum skl_power_gate {
>  						   _MG_PLL_TDC_COLDST_BIAS_PORT1, \
>  						   _MG_PLL_TDC_COLDST_BIAS_PORT2)
>  
> -#define _CNL_DPLL0_CFGCR0		0x6C000
> -#define _CNL_DPLL1_CFGCR0		0x6C080
> -#define  DPLL_CFGCR0_HDMI_MODE		(1 << 30)
> -#define  DPLL_CFGCR0_SSC_ENABLE		(1 << 29)
> -#define  DPLL_CFGCR0_SSC_ENABLE_ICL	(1 << 25)
> -#define  DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
> -#define  DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
> -#define  DPLL_CFGCR0_LINK_RATE_1350	(1 << 25)
> -#define  DPLL_CFGCR0_LINK_RATE_810	(2 << 25)
> -#define  DPLL_CFGCR0_LINK_RATE_1620	(3 << 25)
> -#define  DPLL_CFGCR0_LINK_RATE_1080	(4 << 25)
> -#define  DPLL_CFGCR0_LINK_RATE_2160	(5 << 25)
> -#define  DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
> -#define  DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
> -#define  DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
> -#define  DPLL_CFGCR0_DCO_FRACTION_SHIFT	(10)
> -#define  DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
> -#define  DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
> -#define CNL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
> -
> -#define _CNL_DPLL0_CFGCR1		0x6C004
> -#define _CNL_DPLL1_CFGCR1		0x6C084
> -#define  DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
> -#define  DPLL_CFGCR1_QDIV_RATIO_SHIFT	(10)
> -#define  DPLL_CFGCR1_QDIV_RATIO(x)	((x) << 10)
> -#define  DPLL_CFGCR1_QDIV_MODE_SHIFT	(9)
> -#define  DPLL_CFGCR1_QDIV_MODE(x)	((x) << 9)
> -#define  DPLL_CFGCR1_KDIV_MASK		(7 << 6)
> -#define  DPLL_CFGCR1_KDIV_SHIFT		(6)
> -#define  DPLL_CFGCR1_KDIV(x)		((x) << 6)
> -#define  DPLL_CFGCR1_KDIV_1		(1 << 6)
> -#define  DPLL_CFGCR1_KDIV_2		(2 << 6)
> -#define  DPLL_CFGCR1_KDIV_3		(4 << 6)
> -#define  DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
> -#define  DPLL_CFGCR1_PDIV_SHIFT		(2)
> -#define  DPLL_CFGCR1_PDIV(x)		((x) << 2)
> -#define  DPLL_CFGCR1_PDIV_2		(1 << 2)
> -#define  DPLL_CFGCR1_PDIV_3		(2 << 2)
> -#define  DPLL_CFGCR1_PDIV_5		(4 << 2)
> -#define  DPLL_CFGCR1_PDIV_7		(8 << 2)
> -#define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
> -#define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
> -#define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
> -#define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
> -
>  #define _ICL_DPLL0_CFGCR0		0x164000
>  #define _ICL_DPLL1_CFGCR0		0x164080
>  #define ICL_DPLL_CFGCR0(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
>  						  _ICL_DPLL1_CFGCR0)
> +#define   DPLL_CFGCR0_HDMI_MODE		(1 << 30)
> +#define   DPLL_CFGCR0_SSC_ENABLE	(1 << 29)
> +#define   DPLL_CFGCR0_SSC_ENABLE_ICL	(1 << 25)
> +#define   DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
> +#define   DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
> +#define   DPLL_CFGCR0_LINK_RATE_1350	(1 << 25)
> +#define   DPLL_CFGCR0_LINK_RATE_810	(2 << 25)
> +#define   DPLL_CFGCR0_LINK_RATE_1620	(3 << 25)
> +#define   DPLL_CFGCR0_LINK_RATE_1080	(4 << 25)
> +#define   DPLL_CFGCR0_LINK_RATE_2160	(5 << 25)
> +#define   DPLL_CFGCR0_LINK_RATE_3240	(6 << 25)
> +#define   DPLL_CFGCR0_LINK_RATE_4050	(7 << 25)
> +#define   DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
> +#define   DPLL_CFGCR0_DCO_FRACTION_SHIFT	(10)
> +#define   DPLL_CFGCR0_DCO_FRACTION(x)	((x) << 10)
> +#define   DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
>  
>  #define _ICL_DPLL0_CFGCR1		0x164004
>  #define _ICL_DPLL1_CFGCR1		0x164084
>  #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
>  						  _ICL_DPLL1_CFGCR1)
> +#define   DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
> +#define   DPLL_CFGCR1_QDIV_RATIO_SHIFT	(10)
> +#define   DPLL_CFGCR1_QDIV_RATIO(x)	((x) << 10)
> +#define   DPLL_CFGCR1_QDIV_MODE_SHIFT	(9)
> +#define   DPLL_CFGCR1_QDIV_MODE(x)	((x) << 9)
> +#define   DPLL_CFGCR1_KDIV_MASK		(7 << 6)
> +#define   DPLL_CFGCR1_KDIV_SHIFT		(6)
> +#define   DPLL_CFGCR1_KDIV(x)		((x) << 6)
> +#define   DPLL_CFGCR1_KDIV_1		(1 << 6)
> +#define   DPLL_CFGCR1_KDIV_2		(2 << 6)
> +#define   DPLL_CFGCR1_KDIV_3		(4 << 6)
> +#define   DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
> +#define   DPLL_CFGCR1_PDIV_SHIFT		(2)
> +#define   DPLL_CFGCR1_PDIV(x)		((x) << 2)
> +#define   DPLL_CFGCR1_PDIV_2		(1 << 2)
> +#define   DPLL_CFGCR1_PDIV_3		(2 << 2)
> +#define   DPLL_CFGCR1_PDIV_5		(4 << 2)
> +#define   DPLL_CFGCR1_PDIV_7		(8 << 2)
> +#define   DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
> +#define   DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
> +#define   TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
>  
>  #define _TGL_DPLL0_CFGCR0		0x164284
>  #define _TGL_DPLL1_CFGCR0		0x16428C
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 4319ae020c86..ffe3b5d89a63 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -365,7 +365,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  			info->display.has_dmc = 0;
>  
>  		if (DISPLAY_VER(dev_priv) >= 10 &&
> -		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
> +		    (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
>  			info->display.has_dsc = 0;
>  	}
>  
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 29/30] drm/i915: replace random CNL comments

[Lucas De Marchi]

Cleanup remaining cases that we find CNL in the codebase.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_dp_aux.c   | 1 -
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 -
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
 drivers/gpu/drm/i915/intel_device_info.h      | 2 +-
 6 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4172c8ee6aa6..e86e6ed2d3bf 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1998,7 +1998,7 @@ static void parse_ddi_port(struct drm_i915_private *i915,
 			    "Port %c VBT HDMI boost level: %d\n",
 			    port_name(port), hdmi_boost_level);
 
-	/* DP max link rate for CNL+ */
+	/* DP max link rate for GLK+ */
 	if (i915->vbt.version >= 216) {
 		if (i915->vbt.version >= 230)
 			info->dp_max_link_rate = parse_bdb_230_dp_max_link_rate(child->dp_max_link_rate);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ee6d5f8de24b..b49bf380baab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9778,7 +9778,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
 
 		/*
 		 * FIXME: This check is kept generic for all platforms.
-		 * Need to verify this for all gen9 and gen10 platforms to enable
+		 * Need to verify this for all gen9 platforms to enable
 		 * this selectively if required.
 		 */
 		switch (new_plane_state->hw.fb->modifier) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 7c048d2ecf43..f483f479dd0b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -158,7 +158,6 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 	/*
 	 * Max timeout values:
 	 * SKL-GLK: 1.6ms
-	 * CNL: 3.2ms
 	 * ICL+: 4ms
 	 */
 	ret = DP_AUX_CH_CTL_SEND_BUSY |
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 7fd031a70cfd..6b19f74efd61 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -206,7 +206,6 @@ struct intel_dpll_hw_state {
 
 	/* cnl */
 	u32 cfgcr0;
-	/* CNL also uses cfgcr1 */
 
 	/* bxt */
 	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index dbe24d7e7375..330077c2e588 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -456,7 +456,7 @@ struct child_device_config {
 	u16 dp_gpio_pin_num;					/* 195 */
 	u8 dp_iboost_level:4;					/* 196 */
 	u8 hdmi_iboost_level:4;					/* 196 */
-	u8 dp_max_link_rate:3;					/* 216/230 CNL+ */
+	u8 dp_max_link_rate:3;					/* 216/230 GLK+ */
 	u8 dp_max_link_rate_reserved:5;				/* 216/230 */
 } __packed;
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 057c9aa6f9c6..ef1eecd259e0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -103,7 +103,7 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_ULT	(0)
 #define INTEL_SUBPLATFORM_ULX	(1)
 
-/* CNL/ICL */
+/* ICL */
 #define INTEL_SUBPLATFORM_PORTF	(0)
 
 /* DG2 */
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 29/30] drm/i915: replace random CNL comments

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:13PM -0700, Lucas De Marchi wrote:
> Cleanup remaining cases that we find CNL in the codebase.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
>  drivers/gpu/drm/i915/display/intel_display.c  | 2 +-
>  drivers/gpu/drm/i915/display/intel_dp_aux.c   | 1 -
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 -
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
>  drivers/gpu/drm/i915/intel_device_info.h      | 2 +-
>  6 files changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4172c8ee6aa6..e86e6ed2d3bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1998,7 +1998,7 @@ static void parse_ddi_port(struct drm_i915_private *i915,
>  			    "Port %c VBT HDMI boost level: %d\n",
>  			    port_name(port), hdmi_boost_level);
>  
> -	/* DP max link rate for CNL+ */
> +	/* DP max link rate for GLK+ */
>  	if (i915->vbt.version >= 216) {
>  		if (i915->vbt.version >= 230)
>  			info->dp_max_link_rate = parse_bdb_230_dp_max_link_rate(child->dp_max_link_rate);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ee6d5f8de24b..b49bf380baab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9778,7 +9778,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
>  
>  		/*
>  		 * FIXME: This check is kept generic for all platforms.
> -		 * Need to verify this for all gen9 and gen10 platforms to enable
> +		 * Need to verify this for all gen9 platforms to enable
>  		 * this selectively if required.
>  		 */
>  		switch (new_plane_state->hw.fb->modifier) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 7c048d2ecf43..f483f479dd0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -158,7 +158,6 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
>  	/*
>  	 * Max timeout values:
>  	 * SKL-GLK: 1.6ms
> -	 * CNL: 3.2ms
>  	 * ICL+: 4ms
>  	 */
>  	ret = DP_AUX_CH_CTL_SEND_BUSY |
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 7fd031a70cfd..6b19f74efd61 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -206,7 +206,6 @@ struct intel_dpll_hw_state {
>  
>  	/* cnl */
>  	u32 cfgcr0;
> -	/* CNL also uses cfgcr1 */
>  
>  	/* bxt */
>  	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index dbe24d7e7375..330077c2e588 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -456,7 +456,7 @@ struct child_device_config {
>  	u16 dp_gpio_pin_num;					/* 195 */
>  	u8 dp_iboost_level:4;					/* 196 */
>  	u8 hdmi_iboost_level:4;					/* 196 */
> -	u8 dp_max_link_rate:3;					/* 216/230 CNL+ */
> +	u8 dp_max_link_rate:3;					/* 216/230 GLK+ */
>  	u8 dp_max_link_rate_reserved:5;				/* 216/230 */
>  } __packed;
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 057c9aa6f9c6..ef1eecd259e0 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -103,7 +103,7 @@ enum intel_platform {
>  #define INTEL_SUBPLATFORM_ULT	(0)
>  #define INTEL_SUBPLATFORM_ULX	(1)
>  
> -/* CNL/ICL */
> +/* ICL */
>  #define INTEL_SUBPLATFORM_PORTF	(0)
>  
>  /* DG2 */
> -- 
> 2.31.1
> 
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[Intel-gfx] [PATCH 30/30] drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER

[Lucas De Marchi]

The numbers of scalers and sprites depend on the display version, so use
it instead of GRAPHICS_VER. We were mixing both, which let me confused
while removing CNL and GRAPHICS_VER == 10.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index ffe3b5d89a63..7023d36a9a28 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -265,10 +265,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_scalers[pipe] = 0;
-	else if (GRAPHICS_VER(dev_priv) >= 11) {
+	else if (DISPLAY_VER(dev_priv) >= 11) {
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_scalers[pipe] = 2;
-	} else if (GRAPHICS_VER(dev_priv) == 9) {
+	} else if (DISPLAY_VER(dev_priv) == 9) {
 		runtime->num_scalers[PIPE_A] = 2;
 		runtime->num_scalers[PIPE_B] = 2;
 		runtime->num_scalers[PIPE_C] = 1;
@@ -279,7 +279,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 4;
-	else if (GRAPHICS_VER(dev_priv) >= 11)
+	else if (DISPLAY_VER(dev_priv) >= 11)
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 6;
 	else if (IS_GEMINILAKE(dev_priv))
@@ -301,7 +301,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 2;
-	} else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
+	} else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 		for_each_pipe(dev_priv, pipe)
 			runtime->num_sprites[pipe] = 1;
 	}
-- 
2.31.1

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Re: [Intel-gfx] [PATCH 30/30] drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER

[Rodrigo Vivi]

On Fri, Jul 23, 2021 at 05:11:14PM -0700, Lucas De Marchi wrote:
> The numbers of scalers and sprites depend on the display version, so use
> it instead of GRAPHICS_VER. We were mixing both, which let me confused
> while removing CNL and GRAPHICS_VER == 10.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_device_info.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index ffe3b5d89a63..7023d36a9a28 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -265,10 +265,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_scalers[pipe] = 0;
> -	else if (GRAPHICS_VER(dev_priv) >= 11) {
> +	else if (DISPLAY_VER(dev_priv) >= 11) {
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_scalers[pipe] = 2;
> -	} else if (GRAPHICS_VER(dev_priv) == 9) {
> +	} else if (DISPLAY_VER(dev_priv) == 9) {
>  		runtime->num_scalers[PIPE_A] = 2;
>  		runtime->num_scalers[PIPE_B] = 2;
>  		runtime->num_scalers[PIPE_C] = 1;
> @@ -279,7 +279,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_sprites[pipe] = 4;
> -	else if (GRAPHICS_VER(dev_priv) >= 11)
> +	else if (DISPLAY_VER(dev_priv) >= 11)
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_sprites[pipe] = 6;
>  	else if (IS_GEMINILAKE(dev_priv))

while at it we could probably change this to DISPLAY_VER == 10?!

but anyway:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> @@ -301,7 +301,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_sprites[pipe] = 2;
> -	} else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> +	} else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
>  		for_each_pipe(dev_priv, pipe)
>  			runtime->num_sprites[pipe] = 1;
>  	}
> -- 
> 2.31.1
> 
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 30/30] drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER

[Lucas De Marchi]

On Mon, Jul 26, 2021 at 06:13:10AM -0400, Rodrigo Vivi wrote:
>On Fri, Jul 23, 2021 at 05:11:14PM -0700, Lucas De Marchi wrote:
>> The numbers of scalers and sprites depend on the display version, so use
>> it instead of GRAPHICS_VER. We were mixing both, which let me confused
>> while removing CNL and GRAPHICS_VER == 10.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_device_info.c | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index ffe3b5d89a63..7023d36a9a28 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -265,10 +265,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>>  	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
>>  		for_each_pipe(dev_priv, pipe)
>>  			runtime->num_scalers[pipe] = 0;
>> -	else if (GRAPHICS_VER(dev_priv) >= 11) {
>> +	else if (DISPLAY_VER(dev_priv) >= 11) {
>>  		for_each_pipe(dev_priv, pipe)
>>  			runtime->num_scalers[pipe] = 2;
>> -	} else if (GRAPHICS_VER(dev_priv) == 9) {
>> +	} else if (DISPLAY_VER(dev_priv) == 9) {
>>  		runtime->num_scalers[PIPE_A] = 2;
>>  		runtime->num_scalers[PIPE_B] = 2;
>>  		runtime->num_scalers[PIPE_C] = 1;
>> @@ -279,7 +279,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>>  	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
>>  		for_each_pipe(dev_priv, pipe)
>>  			runtime->num_sprites[pipe] = 4;
>> -	else if (GRAPHICS_VER(dev_priv) >= 11)
>> +	else if (DISPLAY_VER(dev_priv) >= 11)
>>  		for_each_pipe(dev_priv, pipe)
>>  			runtime->num_sprites[pipe] = 6;
>>  	else if (IS_GEMINILAKE(dev_priv))
>
>while at it we could probably change this to DISPLAY_VER == 10?!

yep, sounds good


>
>but anyway:
>
>Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

thanks
Lucas De Marchi

>
>
>
>> @@ -301,7 +301,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>>  		for_each_pipe(dev_priv, pipe)
>>  			runtime->num_sprites[pipe] = 2;
>> -	} else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
>> +	} else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
>>  		for_each_pipe(dev_priv, pipe)
>>  			runtime->num_sprites[pipe] = 1;
>>  	}
>> --
>> 2.31.1
>>
>> _______________________________________________
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Remove CNL support

[Patchwork]

== Series Details ==

Series: Remove CNL support
URL   : https://patchwork.freedesktop.org/series/92969/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e27adf09b131 drm/i915: fix not reading DSC disable fuse in GLK
91073b079293 drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
c099818fef38 drm/i915/display: remove PORT_F workaround for CNL
8d7b56c07e9b drm/i915/display: remove explicit CNL handling from intel_cdclk.c
7bd00018c7aa drm/i915/display: remove explicit CNL handling from intel_color.c
6ab58693b2da drm/i915/display: remove explicit CNL handling from intel_combo_phy.c
9e5d5cfb2392 drm/i915/display: remove explicit CNL handling from intel_crtc.c
7f8343b9406f drm/i915/display: remove explicit CNL handling from intel_ddi.c
76af756baae1 drm/i915/display: remove explicit CNL handling from intel_display_debugfs.c
10405420ea13 drm/i915/display: remove explicit CNL handling from intel_dmc.c
dee4fc5073cd drm/i915/display: remove explicit CNL handling from intel_dp.c
f5c60701839b drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c
819a20382c15 drm/i915/display: remove explicit CNL handling from intel_vdsc.c
dd5b184d9cb7 drm/i915/display: remove explicit CNL handling from skl_universal_plane.c
b32eaf8c4d7e drm/i915/display: remove explicit CNL handling from intel_display_power.c
633e7f1a81a8 drm/i915/display: remove CNL ddi buf translation tables
828ec76c74ef drm/i915/display: rename CNL references in skl_scaler.c
-:62: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#62: FILE: drivers/gpu/drm/i915/i915_reg.h:7729:
+#define GLK_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,    \
 			_ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
 			_ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)

-:62: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'set' - possible side-effects?
#62: FILE: drivers/gpu/drm/i915/i915_reg.h:7729:
+#define GLK_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,    \
 			_ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
 			_ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)

-:67: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id' - possible side-effects?
#67: FILE: drivers/gpu/drm/i915/i915_reg.h:7733:
+#define GLK_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe,     \
 			_ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
 			_ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)

-:67: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'set' - possible side-effects?
#67: FILE: drivers/gpu/drm/i915/i915_reg.h:7733:
+#define GLK_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe,     \
 			_ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
 			_ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)

total: 0 errors, 0 warnings, 4 checks, 48 lines checked
071a58d392be drm/i915: remove explicit CNL handling from i915_irq.c
b058b944fc94 drm/i915: remove explicit CNL handling from intel_pm.c
8a8d2696ed73 drm/i915: remove explicit CNL handling from intel_mocs.c
a0e2f6ca543f drm/i915: remove explicit CNL handling from intel_pch.c
4a321e62dc67 drm/i915: remove explicit CNL handling from intel_wopcm.c
33da770b8bf4 drm/i915/gt: remove explicit CNL handling from intel_sseu.c
0d714eb77ee5 drm/i915: rename CNL references in intel_dram.c
c96bee68580b drm/i915/gt: rename CNL references in intel_engine.h
85aa4acee2d7 drm/i915: finish removal of CNL
11866a4c25c7 drm/i915: remove GRAPHICS_VER == 10
-:347: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#347: FILE: drivers/gpu/drm/i915/i915_drv.h:1652:
+#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
 					IS_GEMINILAKE(dev_priv) || \
 					IS_KABYLAKE(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 336 lines checked
83a3a03bfc68 drm/i915: rename/remove CNL registers
3c6ba298796c drm/i915: replace random CNL comments
67e1ddc63970 drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Remove CNL support

[Patchwork]

== Series Details ==

Series: Remove CNL support
URL   : https://patchwork.freedesktop.org/series/92969/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1896:21:    expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1896:21:    got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1896:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34:    expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34:    got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:    expected struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:    got struct i915_address_space *
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:    expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:    got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined


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[Intel-gfx] ✓ Fi.CI.BAT: success for Remove CNL support

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 7414 bytes --]

== Series Details ==

Series: Remove CNL support
URL   : https://patchwork.freedesktop.org/series/92969/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10383 -> Patchwork_20701
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/index.html

Known issues
------------

  Here are the changes found in Patchwork_20701 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-gfx:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][1] ([fdo#109271]) +23 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-kbl-soraka/igt@amdgpu/amd_basic@cs-gfx.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-soraka:      NOTRUN -> [FAIL][3] ([i915#579])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-kbl-soraka/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [PASS][4] -> [INCOMPLETE][5] ([i915#2782] / [i915#2940])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#2291])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
    - fi-bsw-nick:        NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1436])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-bsw-nick/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-soraka:      [INCOMPLETE][10] ([i915#155]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/fi-kbl-soraka/igt@gem_exec_suspend@basic-s0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-kbl-soraka/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-1115g4:      [FAIL][12] ([i915#1888]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_selftest@live@perf:
    - {fi-tgl-dsi}:       [DMESG-WARN][14] ([i915#2867]) -> [PASS][15] +12 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/fi-tgl-dsi/igt@i915_selftest@live@perf.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/fi-tgl-dsi/igt@i915_selftest@live@perf.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579


Participating hosts (43 -> 36)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adls-4 fi-ctg-p8600 bat-adls-3 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_10383 -> Patchwork_20701

  CI-20190529: 20190529
  CI_DRM_10383: cc4f843734cc8a22416dc00f84f4841d93c75e42 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6149: 34ff2cf2bc352dce691593db803389fe0eb2be03 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20701: 67e1ddc639702dd40528bcd4edee281174c47a7b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

67e1ddc63970 drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER
3c6ba298796c drm/i915: replace random CNL comments
83a3a03bfc68 drm/i915: rename/remove CNL registers
11866a4c25c7 drm/i915: remove GRAPHICS_VER == 10
85aa4acee2d7 drm/i915: finish removal of CNL
c96bee68580b drm/i915/gt: rename CNL references in intel_engine.h
0d714eb77ee5 drm/i915: rename CNL references in intel_dram.c
33da770b8bf4 drm/i915/gt: remove explicit CNL handling from intel_sseu.c
4a321e62dc67 drm/i915: remove explicit CNL handling from intel_wopcm.c
a0e2f6ca543f drm/i915: remove explicit CNL handling from intel_pch.c
8a8d2696ed73 drm/i915: remove explicit CNL handling from intel_mocs.c
b058b944fc94 drm/i915: remove explicit CNL handling from intel_pm.c
071a58d392be drm/i915: remove explicit CNL handling from i915_irq.c
828ec76c74ef drm/i915/display: rename CNL references in skl_scaler.c
633e7f1a81a8 drm/i915/display: remove CNL ddi buf translation tables
b32eaf8c4d7e drm/i915/display: remove explicit CNL handling from intel_display_power.c
dd5b184d9cb7 drm/i915/display: remove explicit CNL handling from skl_universal_plane.c
819a20382c15 drm/i915/display: remove explicit CNL handling from intel_vdsc.c
f5c60701839b drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c
dee4fc5073cd drm/i915/display: remove explicit CNL handling from intel_dp.c
10405420ea13 drm/i915/display: remove explicit CNL handling from intel_dmc.c
76af756baae1 drm/i915/display: remove explicit CNL handling from intel_display_debugfs.c
7f8343b9406f drm/i915/display: remove explicit CNL handling from intel_ddi.c
9e5d5cfb2392 drm/i915/display: remove explicit CNL handling from intel_crtc.c
6ab58693b2da drm/i915/display: remove explicit CNL handling from intel_combo_phy.c
7bd00018c7aa drm/i915/display: remove explicit CNL handling from intel_color.c
8d7b56c07e9b drm/i915/display: remove explicit CNL handling from intel_cdclk.c
c099818fef38 drm/i915/display: remove PORT_F workaround for CNL
91073b079293 drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
e27adf09b131 drm/i915: fix not reading DSC disable fuse in GLK

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/index.html

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Re: [Intel-gfx] [PATCH 00/30] Remove CNL support

[Jason Ekstrand]

[-- Attachment #1.1: Type: text/plain, Size: 5446 bytes --]

Generally a big fan. 👍

--Jason

On July 23, 2021 19:11:34 Lucas De Marchi <lucas.demarchi@intel.com> wrote:

> Patches 1 and 2 are already being reviewed elsewhere. Discussion on 2nd
> patch made me revive something I started after comment from Ville
> at 
> https://patchwork.freedesktop.org/patch/428168/?series=88988&rev=1#comment_768918
>
> This removes CNL completely from the driver, while trying to rename
> functions and macros where appropriate (usually to GLK when dealing with
> display or with ICL otherwise). It starts with display, which is more
> straightforward, and then proceed to the rest of i915.
>
> diff stat removing 1600 lines of dead code seems to pay the pain of
> doing this.
>
>
> Lucas De Marchi (30):
>  drm/i915: fix not reading DSC disable fuse in GLK
>  drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
>  drm/i915/display: remove PORT_F workaround for CNL
>  drm/i915/display: remove explicit CNL handling from intel_cdclk.c
>  drm/i915/display: remove explicit CNL handling from intel_color.c
>  drm/i915/display: remove explicit CNL handling from intel_combo_phy.c
>  drm/i915/display: remove explicit CNL handling from intel_crtc.c
>  drm/i915/display: remove explicit CNL handling from intel_ddi.c
>  drm/i915/display: remove explicit CNL handling from
>    intel_display_debugfs.c
>  drm/i915/display: remove explicit CNL handling from intel_dmc.c
>  drm/i915/display: remove explicit CNL handling from intel_dp.c
>  drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c
>  drm/i915/display: remove explicit CNL handling from intel_vdsc.c
>  drm/i915/display: remove explicit CNL handling from
>    skl_universal_plane.c
>  drm/i915/display: remove explicit CNL handling from
>    intel_display_power.c
>  drm/i915/display: remove CNL ddi buf translation tables
>  drm/i915/display: rename CNL references in skl_scaler.c
>  drm/i915: remove explicit CNL handling from i915_irq.c
>  drm/i915: remove explicit CNL handling from intel_pm.c
>  drm/i915: remove explicit CNL handling from intel_mocs.c
>  drm/i915: remove explicit CNL handling from intel_pch.c
>  drm/i915: remove explicit CNL handling from intel_wopcm.c
>  drm/i915/gt: remove explicit CNL handling from intel_sseu.c
>  drm/i915: rename CNL references in intel_dram.c
>  drm/i915/gt: rename CNL references in intel_engine.h
>  drm/i915: finish removal of CNL
>  drm/i915: remove GRAPHICS_VER == 10
>  drm/i915: rename/remove CNL registers
>  drm/i915: replace random CNL comments
>  drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER
>
> drivers/gpu/drm/i915/display/intel_bios.c     |   8 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c    |  72 +-
> drivers/gpu/drm/i915/display/intel_color.c    |   5 +-
> .../gpu/drm/i915/display/intel_combo_phy.c    | 106 +--
> drivers/gpu/drm/i915/display/intel_crtc.c     |   2 +-
> drivers/gpu/drm/i915/display/intel_ddi.c      | 266 +-------
> .../drm/i915/display/intel_ddi_buf_trans.c    | 616 +++++-------------
> .../drm/i915/display/intel_ddi_buf_trans.h    |   4 +-
> drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
> .../drm/i915/display/intel_display_debugfs.c  |   2 +-
> .../drm/i915/display/intel_display_power.c    | 289 --------
> .../drm/i915/display/intel_display_power.h    |   2 -
> drivers/gpu/drm/i915/display/intel_dmc.c      |   9 -
> drivers/gpu/drm/i915/display/intel_dp.c       |  35 +-
> drivers/gpu/drm/i915/display/intel_dp_aux.c   |   1 -
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 586 +++--------------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   1 -
> drivers/gpu/drm/i915/display/intel_vbt_defs.h |   2 +-
> drivers/gpu/drm/i915/display/intel_vdsc.c     |   5 +-
> drivers/gpu/drm/i915/display/skl_scaler.c     |  10 +-
> .../drm/i915/display/skl_universal_plane.c    |  14 +-
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c    |   1 -
> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c       |  10 +-
> drivers/gpu/drm/i915/gt/intel_engine.h        |   2 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c     |   3 -
> drivers/gpu/drm/i915/gt/intel_ggtt.c          |   4 +-
> .../gpu/drm/i915/gt/intel_gt_clock_utils.c    |  10 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c           |   6 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c           |  42 +-
> drivers/gpu/drm/i915/gt/intel_mocs.c          |   2 +-
> drivers/gpu/drm/i915/gt/intel_rc6.c           |   2 +-
> drivers/gpu/drm/i915/gt/intel_rps.c           |   4 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c          |  79 ---
> drivers/gpu/drm/i915/gt/intel_sseu.h          |   2 +-
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c  |   6 +-
> drivers/gpu/drm/i915/gvt/gtt.c                |   2 +-
> drivers/gpu/drm/i915/i915_debugfs.c           |   6 +-
> drivers/gpu/drm/i915/i915_drv.h               |  13 +-
> drivers/gpu/drm/i915/i915_irq.c               |   7 +-
> drivers/gpu/drm/i915/i915_pci.c               |  23 +-
> drivers/gpu/drm/i915/i915_perf.c              |  22 +-
> drivers/gpu/drm/i915/i915_reg.h               | 245 ++-----
> drivers/gpu/drm/i915/intel_device_info.c      |  23 +-
> drivers/gpu/drm/i915/intel_device_info.h      |   4 +-
> drivers/gpu/drm/i915/intel_dram.c             |  32 +-
> drivers/gpu/drm/i915/intel_pch.c              |   5 +-
> drivers/gpu/drm/i915/intel_pm.c               |  41 +-
> drivers/gpu/drm/i915/intel_wopcm.c            |  10 +-
> 48 files changed, 516 insertions(+), 2128 deletions(-)
>
> --
> 2.31.1


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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for Remove CNL support

[Patchwork]

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== Series Details ==

Series: Remove CNL support
URL   : https://patchwork.freedesktop.org/series/92969/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10383_full -> Patchwork_20701_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20701_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20701_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20701_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_universal_plane@universal-plane-pipe-b-sanity:
    - shard-glk:          [PASS][1] -> [FAIL][2] +23 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk8/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk1/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html

  
Known issues
------------

  Here are the changes found in Patchwork_20701_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([i915#658])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@feature_discovery@psr2.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@feature_discovery@psr2.html

  * igt@gem_ctx_persistence@engines-queued:
    - shard-snb:          NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb6/igt@gem_ctx_persistence@engines-queued.html

  * igt@gem_eio@in-flight-suspend:
    - shard-apl:          [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl2/igt@gem_eio@in-flight-suspend.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl6/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][8] -> [FAIL][9] ([i915#2846])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk8/igt@gem_exec_fair@basic-deadline.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk1/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          [PASS][10] -> [FAIL][11] ([i915#2842]) +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk9/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
    - shard-kbl:          [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl4/igt@gem_exec_fair@basic-none@vcs1.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl2/igt@gem_exec_fair@basic-none@vcs1.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglb:         [PASS][14] -> [FAIL][15] ([i915#2851])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb5/igt@gem_exec_fair@basic-pace@rcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb2/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-kbl:          NOTRUN -> [FAIL][16] ([i915#2842]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_schedule@pi-ringfull@vecs0:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([i915#3397])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl4/igt@gem_exec_schedule@pi-ringfull@vecs0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl8/igt@gem_exec_schedule@pi-ringfull@vecs0.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@input-checking:
    - shard-snb:          NOTRUN -> [DMESG-WARN][20] ([i915#3002])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb6/igt@gem_userptr_blits@input-checking.html

  * igt@i915_pm_rpm@drm-resources-equal:
    - shard-tglb:         NOTRUN -> [SKIP][21] ([i915#579])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb1/igt@i915_pm_rpm@drm-resources-equal.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-skl:          [PASS][22] -> [FAIL][23] ([i915#2521])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
    - shard-glk:          [PASS][24] -> [DMESG-WARN][25] ([i915#118] / [i915#95])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk7/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3777]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-skl:          NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3777])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-tglb:         NOTRUN -> [SKIP][28] ([fdo#111615])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb1/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([i915#3689])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb1/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +21 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl3/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
    - shard-snb:          NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +13 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html

  * igt@kms_color_chamelium@pipe-a-ctm-0-25:
    - shard-skl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_color_chamelium@pipe-a-ctm-0-25.html

  * igt@kms_color_chamelium@pipe-a-ctm-0-75:
    - shard-kbl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl7/igt@kms_color_chamelium@pipe-a-ctm-0-75.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          NOTRUN -> [TIMEOUT][34] ([i915#1319])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_cursor_legacy@pipe-d-single-bo:
    - shard-kbl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#533]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_cursor_legacy@pipe-d-single-bo.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#109278]) +3 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1:
    - shard-glk:          [PASS][37] -> [FAIL][38] ([i915#2122])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [PASS][39] -> [FAIL][40] ([i915#79])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
    - shard-glk:          [PASS][41] -> [FAIL][42] ([i915#79])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [PASS][43] -> [FAIL][44] ([i915#2122]) +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@b-dp1:
    - shard-kbl:          [PASS][45] -> [FAIL][46] ([i915#79])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl2/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-apl:          NOTRUN -> [DMESG-WARN][47] ([i915#180])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
    - shard-apl:          NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#2672])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
    - shard-iclb:         NOTRUN -> [SKIP][49] ([fdo#109280]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
    - shard-kbl:          NOTRUN -> [SKIP][50] ([fdo#109271]) +54 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
    - shard-snb:          NOTRUN -> [SKIP][51] ([fdo#109271]) +287 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-kbl:          NOTRUN -> [FAIL][52] ([fdo#108145] / [i915#265]) +1 similar issue
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265]) +3 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][54] ([i915#265])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_lowres@pipe-b-tiling-yf:
    - shard-iclb:         NOTRUN -> [SKIP][55] ([i915#3536])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_plane_lowres@pipe-b-tiling-yf.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
    - shard-apl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658]) +4 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-kbl:          NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][58] -> [SKIP][59] ([fdo#109441]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_setmode@basic:
    - shard-snb:          NOTRUN -> [FAIL][60] ([i915#31])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb6/igt@kms_setmode@basic.html

  * igt@kms_sysfs_edid_timing:
    - shard-skl:          NOTRUN -> [FAIL][61] ([IGT#2])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-b-accuracy-idle:
    - shard-glk:          [PASS][62] -> [FAIL][63] ([i915#43])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk4/igt@kms_vblank@pipe-b-accuracy-idle.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk3/igt@kms_vblank@pipe-b-accuracy-idle.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-apl:          NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#533]) +4 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-apl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2437]) +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@kms_writeback@writeback-fb-id.html

  * igt@perf@polling-parameterized:
    - shard-tglb:         [PASS][66] -> [FAIL][67] ([i915#1542])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb5/igt@perf@polling-parameterized.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb2/igt@perf@polling-parameterized.html

  * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
    - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271]) +308 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html

  * igt@prime_nv_api@i915_self_import:
    - shard-skl:          NOTRUN -> [SKIP][69] ([fdo#109271]) +22 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@prime_nv_api@i915_self_import.html

  * igt@sysfs_clients@fair-7:
    - shard-apl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2994]) +3 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@sysfs_clients@fair-7.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@engines-hang@rcs0:
    - {shard-rkl}:        [FAIL][71] ([i915#2410]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@gem_ctx_persistence@engines-hang@rcs0.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [FAIL][73] ([i915#2846]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl3/igt@gem_exec_fair@basic-deadline.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl1/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [FAIL][75] ([i915#2842]) -> [PASS][76] +1 similar issue
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          [FAIL][77] ([i915#2842]) -> [PASS][78] +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@bcs0:
    - shard-iclb:         [FAIL][79] ([i915#2842]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@gem_exec_fair@basic-none@bcs0.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@gem_exec_fair@basic-none@bcs0.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [DMESG-WARN][81] ([i915#1436] / [i915#716]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@gen9_exec_parse@allowed-single.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_pm_backlight@fade:
    - {shard-rkl}:        [SKIP][83] ([i915#3012]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@i915_pm_backlight@fade.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@i915_pm_backlight@fade.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglb:         [WARN][85] ([i915#2681]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb6/igt@i915_pm_rc6_residency@rc6-fence.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb7/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180:
    - {shard-rkl}:        [SKIP][87] ([i915#3721]) -> [PASS][88] +4 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-180:
    - {shard-rkl}:        [SKIP][89] ([i915#3638]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - {shard-rkl}:        [FAIL][91] ([i915#3678]) -> [PASS][92] +4 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_color@pipe-c-ctm-max:
    - {shard-rkl}:        [SKIP][93] ([i915#1149] / [i915#1849]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_color@pipe-c-ctm-max.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_color@pipe-c-ctm-max.html

  * igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent:
    - {shard-rkl}:        [SKIP][95] ([fdo#112022]) -> [PASS][96] +5 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - {shard-rkl}:        [SKIP][97] ([fdo#111825]) -> [PASS][98] +2 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled:
    - {shard-rkl}:        [SKIP][99] ([fdo#111314]) -> [PASS][100] +3 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [INCOMPLETE][101] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-apl:          [DMESG-WARN][103] ([i915#180]) -> [PASS][104] +2 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [FAIL][105] ([i915#2122]) -> [PASS][106] +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - {shard-rkl}:        [SKIP][107] ([i915#1849]) -> [PASS][108] +24 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [DMESG-WARN][109] ([i915#180]) -> [PASS][110] +1 similar issue
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane@pixel-format@pipe-a-planes:
    - {shard-rkl}:        [SKIP][111] ([i915#3558]) -> [PASS][112] +1 similar issue
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_plane@pixel-format@pipe-a-planes.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_plane@pixel-format@pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][113] ([fdo#108145] / [i915#265]) -> [PASS][114] +1 similar issue
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@primary_blt:
    - {shard-rkl}:        [SKIP][115] ([i915#1072]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_psr@primary_blt.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_psr@primary_blt.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [SKIP][117] ([fdo#109441]) -> [PASS][118] +2 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_vblank@pipe-c-query-forked-hang:
    - {shard-rkl}:        [SKIP][119] ([i915#1845]) -> [PASS][120] +11 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_vblank@pipe-c-query-forked-hang.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_vblank@pipe-c-query-forked-hang.html

  * igt@perf@blocking:
    - {shard-rkl}:        [FAIL][121] ([i915#1542]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-6/igt@perf@blocking.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@perf@blocking.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [FAIL][123] ([i915#1542]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@perf@polling-parameterized.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@perf@polling-parameterized.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         [FAIL][125] ([i915#2852]) -> [FAIL][126] ([i915#2842])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-iclb:         [SKIP][127] ([i915#2920]) -> [SKIP][128] ([i915#658]) +2 similar issues
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
    - shard-iclb:         [SKIP][129] ([i915#658]) -> [SKIP][130] ([i915#2920]) +2 similar issues
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135]) ([i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#92]) -> ([FAIL][136], [FAIL][137]) ([i915#3002] / [i915#3363])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl7/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl3/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl6/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl7/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl3/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl4/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@runner@aborted.html
    - shard-apl:          ([FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146]) ([i915#1610] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl6/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl1/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl2/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl7/igt@runner@aborted.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl6/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl6/igt@runner@aborted.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl3/igt@runner@aborted.html
    - shard-skl:          ([FAIL][147], [FAIL][148], [FAIL][149]) ([i915#1436] / [i915#3002] / [i915#3363]) -> ([FAIL][150], [FAIL][151]) ([i915#3002] / [i915#3363])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl8/igt@runner@aborted.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl5/igt@runner@aborted.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@runner@aborted.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl1/igt@runner@aborted.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl10/igt@runner@aborted.html

  
  {name}: Th

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/index.html

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_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Remove CNL support

[Rodrigo Vivi]

On Sat, Jul 24, 2021 at 12:37:18PM -0000, Patchwork wrote:
>    Patch Details
> 
>    Series:  Remove CNL support
>    URL:     [1]https://patchwork.freedesktop.org/series/92969/
>    State:   failure
>    Details:
>    [2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/index.html
> 
>       CI Bug Log - changes from CI_DRM_10383_full -> Patchwork_20701_full
> 
> Summary
> 
>    FAILURE
> 
>    Serious unknown changes coming with Patchwork_20701_full absolutely
>    need to be
>    verified manually.
> 
>    If you think the reported changes have nothing to do with the changes
>    introduced in Patchwork_20701_full, please notify your bug team to
>    allow them
>    to document this new failure mode, which will reduce false positives in
>    CI.
> 
> Possible new issues
> 
>    Here are the unknown changes that may have been introduced in
>    Patchwork_20701_full:
> 
>   IGT changes
> 
>     Possible regressions
> 
>      * igt@kms_universal_plane@universal-plane-pipe-b-sanity:
>           + shard-glk: [3]PASS -> [4]FAIL +23 similar issues

I got to the end of the display related ones and I couldn't spot
where this bug is :(

> 
> Known issues
> 
>    Here are the changes found in Patchwork_20701_full that come from known
>    issues:
> 
>   IGT changes
> 
>     Issues hit
> 
>      * igt@feature_discovery@psr2:
>           + shard-iclb: [5]PASS -> [6]SKIP ([i915#658])
>      * igt@gem_ctx_persistence@engines-queued:
>           + shard-snb: NOTRUN -> [7]SKIP ([fdo#109271] / [i915#1099])
>      * igt@gem_eio@in-flight-suspend:
>           + shard-apl: [8]PASS -> [9]DMESG-WARN ([i915#180]) +2 similar
>             issues
>      * igt@gem_exec_fair@basic-deadline:
>           + shard-glk: [10]PASS -> [11]FAIL ([i915#2846])
>      * igt@gem_exec_fair@basic-none-rrul@rcs0:
>           + shard-glk: [12]PASS -> [13]FAIL ([i915#2842]) +2 similar
>             issues
>      * igt@gem_exec_fair@basic-none@vcs1:
>           + shard-kbl: [14]PASS -> [15]FAIL ([i915#2842]) +1 similar issue
>      * igt@gem_exec_fair@basic-pace@rcs0:
>           + shard-tglb: [16]PASS -> [17]FAIL ([i915#2851])
>      * igt@gem_exec_fair@basic-pace@vecs0:
>           + shard-kbl: NOTRUN -> [18]FAIL ([i915#2842]) +1 similar issue
>      * igt@gem_exec_schedule@pi-ringfull@vecs0:
>           + shard-skl: [19]PASS -> [20]FAIL ([i915#3397])
>      * igt@gem_userptr_blits@dmabuf-sync:
>           + shard-apl: NOTRUN -> [21]SKIP ([fdo#109271] / [i915#3323])
>      * igt@gem_userptr_blits@input-checking:
>           + shard-snb: NOTRUN -> [22]DMESG-WARN ([i915#3002])
>      * igt@i915_pm_rpm@drm-resources-equal:
>           + shard-tglb: NOTRUN -> [23]SKIP ([i915#579])
>      * igt@kms_async_flips@alternate-sync-async-flip:
>           + shard-skl: [24]PASS -> [25]FAIL ([i915#2521])
>      * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
>           + shard-glk: [26]PASS -> [27]DMESG-WARN ([i915#118] / [i915#95])
>      * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
>           + shard-apl: NOTRUN -> [28]SKIP ([fdo#109271] / [i915#3777]) +1
>             similar issue
>      * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
>           + shard-skl: NOTRUN -> [29]SKIP ([fdo#109271] / [i915#3777])
>      * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
>           + shard-tglb: NOTRUN -> [30]SKIP ([fdo#111615])
>      * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs:
>           + shard-tglb: NOTRUN -> [31]SKIP ([i915#3689])
>      * igt@kms_chamelium@dp-mode-timings:
>           + shard-apl: NOTRUN -> [32]SKIP ([fdo#109271] / [fdo#111827])
>             +21 similar issues
>      * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
>           + shard-snb: NOTRUN -> [33]SKIP ([fdo#109271] / [fdo#111827])
>             +13 similar issues
>      * igt@kms_color_chamelium@pipe-a-ctm-0-25:
>           + shard-skl: NOTRUN -> [34]SKIP ([fdo#109271] / [fdo#111827]) +1
>             similar issue
>      * igt@kms_color_chamelium@pipe-a-ctm-0-75:
>           + shard-kbl: NOTRUN -> [35]SKIP ([fdo#109271] / [fdo#111827]) +4
>             similar issues
>      * igt@kms_content_protection@atomic-dpms:
>           + shard-apl: NOTRUN -> [36]TIMEOUT ([i915#1319])
>      * igt@kms_cursor_legacy@pipe-d-single-bo:
>           + shard-kbl: NOTRUN -> [37]SKIP ([fdo#109271] / [i915#533]) +1
>             similar issue
>      * igt@kms_cursor_legacy@pipe-d-torture-bo:
>           + shard-iclb: NOTRUN -> [38]SKIP ([fdo#109278]) +3 similar
>             issues
>      * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1:
>           + shard-glk: [39]PASS -> [40]FAIL ([i915#2122])
>      * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
>           + shard-skl: [41]PASS -> [42]FAIL ([i915#79])
>      * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
>           + shard-glk: [43]PASS -> [44]FAIL ([i915#79])
>      * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
>           + shard-skl: [45]PASS -> [46]FAIL ([i915#2122]) +2 similar
>             issues
>      * igt@kms_flip@flip-vs-expired-vblank@b-dp1:
>           + shard-kbl: [47]PASS -> [48]FAIL ([i915#79])
>      * igt@kms_flip@flip-vs-suspend@a-dp1:
>           + shard-apl: NOTRUN -> [49]DMESG-WARN ([i915#180])
>      * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
>           + shard-apl: NOTRUN -> [50]SKIP ([fdo#109271] / [i915#2672])
>      * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
>           + shard-iclb: NOTRUN -> [51]SKIP ([fdo#109280]) +1 similar issue
>      * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
>           + shard-kbl: NOTRUN -> [52]SKIP ([fdo#109271]) +54 similar
>             issues
>      * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-rend
>        er:
>           + shard-snb: NOTRUN -> [53]SKIP ([fdo#109271]) +287 similar
>             issues
>      * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
>           + shard-kbl: NOTRUN -> [54]FAIL ([fdo#108145] / [i915#265]) +1
>             similar issue
>      * igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
>           + shard-apl: NOTRUN -> [55]FAIL ([fdo#108145] / [i915#265]) +3
>             similar issues
>      * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
>           + shard-apl: NOTRUN -> [56]FAIL ([i915#265])
>      * igt@kms_plane_lowres@pipe-b-tiling-yf:
>           + shard-iclb: NOTRUN -> [57]SKIP ([i915#3536])
>      * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
>           + shard-apl: NOTRUN -> [58]SKIP ([fdo#109271] / [i915#658]) +4
>             similar issues
>      * igt@kms_psr2_su@frontbuffer:
>           + shard-kbl: NOTRUN -> [59]SKIP ([fdo#109271] / [i915#658])
>      * igt@kms_psr@psr2_cursor_render:
>           + shard-iclb: [60]PASS -> [61]SKIP ([fdo#109441]) +1 similar
>             issue
>      * igt@kms_setmode@basic:
>           + shard-snb: NOTRUN -> [62]FAIL ([i915#31])
>      * igt@kms_sysfs_edid_timing:
>           + shard-skl: NOTRUN -> [63]FAIL ([IGT#2])
>      * igt@kms_vblank@pipe-b-accuracy-idle:
>           + shard-glk: [64]PASS -> [65]FAIL ([i915#43])
>      * igt@kms_vblank@pipe-d-wait-idle:
>           + shard-apl: NOTRUN -> [66]SKIP ([fdo#109271] / [i915#533]) +4
>             similar issues
>      * igt@kms_writeback@writeback-fb-id:
>           + shard-apl: NOTRUN -> [67]SKIP ([fdo#109271] / [i915#2437]) +1
>             similar issue
>      * igt@perf@polling-parameterized:
>           + shard-tglb: [68]PASS -> [69]FAIL ([i915#1542])
>      * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
>           + shard-apl: NOTRUN -> [70]SKIP ([fdo#109271]) +308 similar
>             issues
>      * igt@prime_nv_api@i915_self_import:
>           + shard-skl: NOTRUN -> [71]SKIP ([fdo#109271]) +22 similar
>             issues
>      * igt@sysfs_clients@fair-7:
>           + shard-apl: NOTRUN -> [72]SKIP ([fdo#109271] / [i915#2994]) +3
>             similar issues
> 
>     Possible fixes
> 
>      * igt@gem_ctx_persistence@engines-hang@rcs0:
>           + {shard-rkl}: [73]FAIL ([i915#2410]) -> [74]PASS
>      * igt@gem_exec_fair@basic-deadline:
>           + shard-kbl: [75]FAIL ([i915#2846]) -> [76]PASS
>      * igt@gem_exec_fair@basic-flow@rcs0:
>           + shard-tglb: [77]FAIL ([i915#2842]) -> [78]PASS +1 similar
>             issue
>      * igt@gem_exec_fair@basic-none-solo@rcs0:
>           + shard-kbl: [79]FAIL ([i915#2842]) -> [80]PASS +1 similar issue
>      * igt@gem_exec_fair@basic-none@bcs0:
>           + shard-iclb: [81]FAIL ([i915#2842]) -> [82]PASS
>      * igt@gen9_exec_parse@allowed-single:
>           + shard-skl: [83]DMESG-WARN ([i915#1436] / [i915#716]) ->
>             [84]PASS
>      * igt@i915_pm_backlight@fade:
>           + {shard-rkl}: [85]SKIP ([i915#3012]) -> [86]PASS
>      * igt@i915_pm_rc6_residency@rc6-fence:
>           + shard-tglb: [87]WARN ([i915#2681]) -> [88]PASS
>      * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180:
>           + {shard-rkl}: [89]SKIP ([i915#3721]) -> [90]PASS +4 similar
>             issues
>      * igt@kms_big_fb@y-tiled-64bpp-rotate-180:
>           + {shard-rkl}: [91]SKIP ([i915#3638]) -> [92]PASS
>      * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
>           + {shard-rkl}: [93]FAIL ([i915#3678]) -> [94]PASS +4 similar
>             issues
>      * igt@kms_color@pipe-c-ctm-max:
>           + {shard-rkl}: [95]SKIP ([i915#1149] / [i915#1849]) -> [96]PASS
>      * igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent:
>           + {shard-rkl}: [97]SKIP ([fdo#112022]) -> [98]PASS +5 similar
>             issues
>      * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
>           + {shard-rkl}: [99]SKIP ([fdo#111825]) -> [100]PASS +2 similar
>             issues
>      * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled:
>           + {shard-rkl}: [101]SKIP ([fdo#111314]) -> [102]PASS +3 similar
>             issues
>      * igt@kms_fbcon_fbt@fbc-suspend:
>           + shard-kbl: [103]INCOMPLETE ([i915#155] / [i915#180] /
>             [i915#636]) -> [104]PASS
>      * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
>           + shard-apl: [105]DMESG-WARN ([i915#180]) -> [106]PASS +2
>             similar issues
>      * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
>           + shard-skl: [107]FAIL ([i915#2122]) -> [108]PASS +1 similar
>             issue
>      * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap
>        -gtt:
>           + {shard-rkl}: [109]SKIP ([i915#1849]) -> [110]PASS +24 similar
>             issues
>      * igt@kms_hdr@bpc-switch-suspend:
>           + shard-kbl: [111]DMESG-WARN ([i915#180]) -> [112]PASS +1
>             similar issue
>      * igt@kms_plane@pixel-format@pipe-a-planes:
>           + {shard-rkl}: [113]SKIP ([i915#3558]) -> [114]PASS +1 similar
>             issue
>      * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>           + shard-skl: [115]FAIL ([fdo#108145] / [i915#265]) -> [116]PASS
>             +1 similar issue
>      * igt@kms_psr@primary_blt:
>           + {shard-rkl}: [117]SKIP ([i915#1072]) -> [118]PASS
>      * igt@kms_psr@psr2_primary_page_flip:
>           + shard-iclb: [119]SKIP ([fdo#109441]) -> [120]PASS +2 similar
>             issues
>      * igt@kms_vblank@pipe-c-query-forked-hang:
>           + {shard-rkl}: [121]SKIP ([i915#1845]) -> [122]PASS +11 similar
>             issues
>      * igt@perf@blocking:
>           + {shard-rkl}: [123]FAIL ([i915#1542]) -> [124]PASS
>      * igt@perf@polling-parameterized:
>           + shard-skl: [125]FAIL ([i915#1542]) -> [126]PASS
> 
>     Warnings
> 
>      * igt@gem_exec_fair@basic-none-rrul@rcs0:
>           + shard-iclb: [127]FAIL ([i915#2852]) -> [128]FAIL ([i915#2842])
>      * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
>           + shard-iclb: [129]SKIP ([i915#2920]) -> [130]SKIP ([i915#658])
>             +2 similar issues
>      * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
>           + shard-iclb: [131]SKIP ([i915#658]) -> [132]SKIP ([i915#2920])
>             +2 similar issues
>      * igt@runner@aborted:
>           + shard-kbl: ([133]FAIL, [134]FAIL, [135]FAIL, [136]FAIL,
>             [137]FAIL) ([i915#180] / [i915#1814] / [i915#2505] /
>             [i915#3002] / [i915#3363] / [i915#92]) -> ([138]FAIL,
>             [139]FAIL) ([i915#3002] / [i915#3363])
>           + shard-apl: ([140]FAIL, [141]FAIL, [142]FAIL, [143]FAIL)
>             ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) ->
>             ([144]FAIL, [145]FAIL, [146]FAIL, [147]FAIL, [148]FAIL)
>             ([i915#1610] / [i915#180] / [i915#1814] / [i915#3002] /
>             [i915#3363])
>           + shard-skl: ([149]FAIL, [150]FAIL, [151]FAIL) ([i915#1436] /
>             [i915#3002] / [i915#3363]) -> ([152]FAIL, [153]FAIL)
>             ([i915#3002] / [i915#3363])
> 
>    {name}: Th
> 
> References
> 
>    1. https://patchwork.freedesktop.org/series/92969/
>    2. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/index.html
>    3. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk8/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html
>    4. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk1/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html
>    5. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@feature_discovery@psr2.html
>    6. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@feature_discovery@psr2.html
>    7. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb6/igt@gem_ctx_persistence@engines-queued.html
>    8. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl2/igt@gem_eio@in-flight-suspend.html
>    9. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl6/igt@gem_eio@in-flight-suspend.html
>   10. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk8/igt@gem_exec_fair@basic-deadline.html
>   11. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk1/igt@gem_exec_fair@basic-deadline.html
>   12. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>   13. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>   14. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl4/igt@gem_exec_fair@basic-none@vcs1.html
>   15. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl2/igt@gem_exec_fair@basic-none@vcs1.html
>   16. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb5/igt@gem_exec_fair@basic-pace@rcs0.html
>   17. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb2/igt@gem_exec_fair@basic-pace@rcs0.html
>   18. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
>   19. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl4/igt@gem_exec_schedule@pi-ringfull@vecs0.html
>   20. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl8/igt@gem_exec_schedule@pi-ringfull@vecs0.html
>   21. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@gem_userptr_blits@dmabuf-sync.html
>   22. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb6/igt@gem_userptr_blits@input-checking.html
>   23. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb1/igt@i915_pm_rpm@drm-resources-equal.html
>   24. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip.html
>   25. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
>   26. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk7/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
>   27. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
>   28. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
>   29. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
>   30. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb1/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
>   31. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb1/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs.html
>   32. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl3/igt@kms_chamelium@dp-mode-timings.html
>   33. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
>   34. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
>   35. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl7/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
>   36. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_content_protection@atomic-dpms.html
>   37. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_cursor_legacy@pipe-d-single-bo.html
>   38. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_cursor_legacy@pipe-d-torture-bo.html
>   39. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
>   40. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
>   41. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
>   42. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
>   43. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
>   44. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
>   45. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
>   46. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
>   47. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html
>   48. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl2/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html
>   49. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
>   50. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
>   51. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
>   52. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
>   53. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
>   54. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
>   55. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
>   56. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
>   57. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_plane_lowres@pipe-b-tiling-yf.html
>   58. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
>   59. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_psr2_su@frontbuffer.html
>   60. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
>   61. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
>   62. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb6/igt@kms_setmode@basic.html
>   63. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_sysfs_edid_timing.html
>   64. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk4/igt@kms_vblank@pipe-b-accuracy-idle.html
>   65. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk3/igt@kms_vblank@pipe-b-accuracy-idle.html
>   66. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@kms_vblank@pipe-d-wait-idle.html
>   67. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@kms_writeback@writeback-fb-id.html
>   68. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb5/igt@perf@polling-parameterized.html
>   69. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb2/igt@perf@polling-parameterized.html
>   70. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
>   71. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@prime_nv_api@i915_self_import.html
>   72. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@sysfs_clients@fair-7.html
>   73. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@gem_ctx_persistence@engines-hang@rcs0.html
>   74. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@rcs0.html
>   75. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl3/igt@gem_exec_fair@basic-deadline.html
>   76. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
>   77. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
>   78. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
>   79. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
>   80. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
>   81. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@gem_exec_fair@basic-none@bcs0.html
>   82. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@gem_exec_fair@basic-none@bcs0.html
>   83. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@gen9_exec_parse@allowed-single.html
>   84. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@gen9_exec_parse@allowed-single.html
>   85. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@i915_pm_backlight@fade.html
>   86. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@i915_pm_backlight@fade.html
>   87. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb6/igt@i915_pm_rc6_residency@rc6-fence.html
>   88. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb7/igt@i915_pm_rc6_residency@rc6-fence.html
>   89. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html
>   90. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html
>   91. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
>   92. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
>   93. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
>   94. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
>   95. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_color@pipe-c-ctm-max.html
>   96. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_color@pipe-c-ctm-max.html
>   97. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
>   98. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
>   99. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
>  100. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
>  101. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
>  102. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
>  103. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
>  104. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
>  105. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
>  106. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
>  107. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
>  108. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
>  109. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
>  110. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
>  111. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html
>  112. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html
>  113. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_plane@pixel-format@pipe-a-planes.html
>  114. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_plane@pixel-format@pipe-a-planes.html
>  115. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>  116. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>  117. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_psr@primary_blt.html
>  118. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_psr@primary_blt.html
>  119. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
>  120. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
>  121. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_vblank@pipe-c-query-forked-hang.html
>  122. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_vblank@pipe-c-query-forked-hang.html
>  123. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-6/igt@perf@blocking.html
>  124. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@perf@blocking.html
>  125. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@perf@polling-parameterized.html
>  126. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@perf@polling-parameterized.html
>  127. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>  128. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>  129. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
>  130. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
>  131. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
>  132. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
>  133. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl7/igt@runner@aborted.html
>  134. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl3/igt@runner@aborted.html
>  135. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl6/igt@runner@aborted.html
>  136. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl7/igt@runner@aborted.html
>  137. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl3/igt@runner@aborted.html
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Remove CNL support

[Lucas De Marchi]

On Mon, Jul 26, 2021 at 07:07:49AM -0400, Rodrigo Vivi wrote:
>On Sat, Jul 24, 2021 at 12:37:18PM -0000, Patchwork wrote:
>>    Patch Details
>>
>>    Series:  Remove CNL support
>>    URL:     [1]https://patchwork.freedesktop.org/series/92969/
>>    State:   failure
>>    Details:
>>    [2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/index.html
>>
>>       CI Bug Log - changes from CI_DRM_10383_full -> Patchwork_20701_full
>>
>> Summary
>>
>>    FAILURE
>>
>>    Serious unknown changes coming with Patchwork_20701_full absolutely
>>    need to be
>>    verified manually.
>>
>>    If you think the reported changes have nothing to do with the changes
>>    introduced in Patchwork_20701_full, please notify your bug team to
>>    allow them
>>    to document this new failure mode, which will reduce false positives in
>>    CI.
>>
>> Possible new issues
>>
>>    Here are the unknown changes that may have been introduced in
>>    Patchwork_20701_full:
>>
>>   IGT changes
>>
>>     Possible regressions
>>
>>      * igt@kms_universal_plane@universal-plane-pipe-b-sanity:
>>           + shard-glk: [3]PASS -> [4]FAIL +23 similar issues
>
>I got to the end of the display related ones and I couldn't spot
>where this bug is :(

although since this is GLK, it's very suspicious. I will take another
look and maybe try to split the patches to check what CI thinks.

Thanks!
Lucas De Marchi

>
>>
>> Known issues
>>
>>    Here are the changes found in Patchwork_20701_full that come from known
>>    issues:
>>
>>   IGT changes
>>
>>     Issues hit
>>
>>      * igt@feature_discovery@psr2:
>>           + shard-iclb: [5]PASS -> [6]SKIP ([i915#658])
>>      * igt@gem_ctx_persistence@engines-queued:
>>           + shard-snb: NOTRUN -> [7]SKIP ([fdo#109271] / [i915#1099])
>>      * igt@gem_eio@in-flight-suspend:
>>           + shard-apl: [8]PASS -> [9]DMESG-WARN ([i915#180]) +2 similar
>>             issues
>>      * igt@gem_exec_fair@basic-deadline:
>>           + shard-glk: [10]PASS -> [11]FAIL ([i915#2846])
>>      * igt@gem_exec_fair@basic-none-rrul@rcs0:
>>           + shard-glk: [12]PASS -> [13]FAIL ([i915#2842]) +2 similar
>>             issues
>>      * igt@gem_exec_fair@basic-none@vcs1:
>>           + shard-kbl: [14]PASS -> [15]FAIL ([i915#2842]) +1 similar issue
>>      * igt@gem_exec_fair@basic-pace@rcs0:
>>           + shard-tglb: [16]PASS -> [17]FAIL ([i915#2851])
>>      * igt@gem_exec_fair@basic-pace@vecs0:
>>           + shard-kbl: NOTRUN -> [18]FAIL ([i915#2842]) +1 similar issue
>>      * igt@gem_exec_schedule@pi-ringfull@vecs0:
>>           + shard-skl: [19]PASS -> [20]FAIL ([i915#3397])
>>      * igt@gem_userptr_blits@dmabuf-sync:
>>           + shard-apl: NOTRUN -> [21]SKIP ([fdo#109271] / [i915#3323])
>>      * igt@gem_userptr_blits@input-checking:
>>           + shard-snb: NOTRUN -> [22]DMESG-WARN ([i915#3002])
>>      * igt@i915_pm_rpm@drm-resources-equal:
>>           + shard-tglb: NOTRUN -> [23]SKIP ([i915#579])
>>      * igt@kms_async_flips@alternate-sync-async-flip:
>>           + shard-skl: [24]PASS -> [25]FAIL ([i915#2521])
>>      * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
>>           + shard-glk: [26]PASS -> [27]DMESG-WARN ([i915#118] / [i915#95])
>>      * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
>>           + shard-apl: NOTRUN -> [28]SKIP ([fdo#109271] / [i915#3777]) +1
>>             similar issue
>>      * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
>>           + shard-skl: NOTRUN -> [29]SKIP ([fdo#109271] / [i915#3777])
>>      * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
>>           + shard-tglb: NOTRUN -> [30]SKIP ([fdo#111615])
>>      * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs:
>>           + shard-tglb: NOTRUN -> [31]SKIP ([i915#3689])
>>      * igt@kms_chamelium@dp-mode-timings:
>>           + shard-apl: NOTRUN -> [32]SKIP ([fdo#109271] / [fdo#111827])
>>             +21 similar issues
>>      * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
>>           + shard-snb: NOTRUN -> [33]SKIP ([fdo#109271] / [fdo#111827])
>>             +13 similar issues
>>      * igt@kms_color_chamelium@pipe-a-ctm-0-25:
>>           + shard-skl: NOTRUN -> [34]SKIP ([fdo#109271] / [fdo#111827]) +1
>>             similar issue
>>      * igt@kms_color_chamelium@pipe-a-ctm-0-75:
>>           + shard-kbl: NOTRUN -> [35]SKIP ([fdo#109271] / [fdo#111827]) +4
>>             similar issues
>>      * igt@kms_content_protection@atomic-dpms:
>>           + shard-apl: NOTRUN -> [36]TIMEOUT ([i915#1319])
>>      * igt@kms_cursor_legacy@pipe-d-single-bo:
>>           + shard-kbl: NOTRUN -> [37]SKIP ([fdo#109271] / [i915#533]) +1
>>             similar issue
>>      * igt@kms_cursor_legacy@pipe-d-torture-bo:
>>           + shard-iclb: NOTRUN -> [38]SKIP ([fdo#109278]) +3 similar
>>             issues
>>      * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1:
>>           + shard-glk: [39]PASS -> [40]FAIL ([i915#2122])
>>      * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
>>           + shard-skl: [41]PASS -> [42]FAIL ([i915#79])
>>      * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
>>           + shard-glk: [43]PASS -> [44]FAIL ([i915#79])
>>      * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
>>           + shard-skl: [45]PASS -> [46]FAIL ([i915#2122]) +2 similar
>>             issues
>>      * igt@kms_flip@flip-vs-expired-vblank@b-dp1:
>>           + shard-kbl: [47]PASS -> [48]FAIL ([i915#79])
>>      * igt@kms_flip@flip-vs-suspend@a-dp1:
>>           + shard-apl: NOTRUN -> [49]DMESG-WARN ([i915#180])
>>      * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
>>           + shard-apl: NOTRUN -> [50]SKIP ([fdo#109271] / [i915#2672])
>>      * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
>>           + shard-iclb: NOTRUN -> [51]SKIP ([fdo#109280]) +1 similar issue
>>      * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
>>           + shard-kbl: NOTRUN -> [52]SKIP ([fdo#109271]) +54 similar
>>             issues
>>      * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-rend
>>        er:
>>           + shard-snb: NOTRUN -> [53]SKIP ([fdo#109271]) +287 similar
>>             issues
>>      * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
>>           + shard-kbl: NOTRUN -> [54]FAIL ([fdo#108145] / [i915#265]) +1
>>             similar issue
>>      * igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
>>           + shard-apl: NOTRUN -> [55]FAIL ([fdo#108145] / [i915#265]) +3
>>             similar issues
>>      * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
>>           + shard-apl: NOTRUN -> [56]FAIL ([i915#265])
>>      * igt@kms_plane_lowres@pipe-b-tiling-yf:
>>           + shard-iclb: NOTRUN -> [57]SKIP ([i915#3536])
>>      * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
>>           + shard-apl: NOTRUN -> [58]SKIP ([fdo#109271] / [i915#658]) +4
>>             similar issues
>>      * igt@kms_psr2_su@frontbuffer:
>>           + shard-kbl: NOTRUN -> [59]SKIP ([fdo#109271] / [i915#658])
>>      * igt@kms_psr@psr2_cursor_render:
>>           + shard-iclb: [60]PASS -> [61]SKIP ([fdo#109441]) +1 similar
>>             issue
>>      * igt@kms_setmode@basic:
>>           + shard-snb: NOTRUN -> [62]FAIL ([i915#31])
>>      * igt@kms_sysfs_edid_timing:
>>           + shard-skl: NOTRUN -> [63]FAIL ([IGT#2])
>>      * igt@kms_vblank@pipe-b-accuracy-idle:
>>           + shard-glk: [64]PASS -> [65]FAIL ([i915#43])
>>      * igt@kms_vblank@pipe-d-wait-idle:
>>           + shard-apl: NOTRUN -> [66]SKIP ([fdo#109271] / [i915#533]) +4
>>             similar issues
>>      * igt@kms_writeback@writeback-fb-id:
>>           + shard-apl: NOTRUN -> [67]SKIP ([fdo#109271] / [i915#2437]) +1
>>             similar issue
>>      * igt@perf@polling-parameterized:
>>           + shard-tglb: [68]PASS -> [69]FAIL ([i915#1542])
>>      * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
>>           + shard-apl: NOTRUN -> [70]SKIP ([fdo#109271]) +308 similar
>>             issues
>>      * igt@prime_nv_api@i915_self_import:
>>           + shard-skl: NOTRUN -> [71]SKIP ([fdo#109271]) +22 similar
>>             issues
>>      * igt@sysfs_clients@fair-7:
>>           + shard-apl: NOTRUN -> [72]SKIP ([fdo#109271] / [i915#2994]) +3
>>             similar issues
>>
>>     Possible fixes
>>
>>      * igt@gem_ctx_persistence@engines-hang@rcs0:
>>           + {shard-rkl}: [73]FAIL ([i915#2410]) -> [74]PASS
>>      * igt@gem_exec_fair@basic-deadline:
>>           + shard-kbl: [75]FAIL ([i915#2846]) -> [76]PASS
>>      * igt@gem_exec_fair@basic-flow@rcs0:
>>           + shard-tglb: [77]FAIL ([i915#2842]) -> [78]PASS +1 similar
>>             issue
>>      * igt@gem_exec_fair@basic-none-solo@rcs0:
>>           + shard-kbl: [79]FAIL ([i915#2842]) -> [80]PASS +1 similar issue
>>      * igt@gem_exec_fair@basic-none@bcs0:
>>           + shard-iclb: [81]FAIL ([i915#2842]) -> [82]PASS
>>      * igt@gen9_exec_parse@allowed-single:
>>           + shard-skl: [83]DMESG-WARN ([i915#1436] / [i915#716]) ->
>>             [84]PASS
>>      * igt@i915_pm_backlight@fade:
>>           + {shard-rkl}: [85]SKIP ([i915#3012]) -> [86]PASS
>>      * igt@i915_pm_rc6_residency@rc6-fence:
>>           + shard-tglb: [87]WARN ([i915#2681]) -> [88]PASS
>>      * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180:
>>           + {shard-rkl}: [89]SKIP ([i915#3721]) -> [90]PASS +4 similar
>>             issues
>>      * igt@kms_big_fb@y-tiled-64bpp-rotate-180:
>>           + {shard-rkl}: [91]SKIP ([i915#3638]) -> [92]PASS
>>      * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
>>           + {shard-rkl}: [93]FAIL ([i915#3678]) -> [94]PASS +4 similar
>>             issues
>>      * igt@kms_color@pipe-c-ctm-max:
>>           + {shard-rkl}: [95]SKIP ([i915#1149] / [i915#1849]) -> [96]PASS
>>      * igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent:
>>           + {shard-rkl}: [97]SKIP ([fdo#112022]) -> [98]PASS +5 similar
>>             issues
>>      * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
>>           + {shard-rkl}: [99]SKIP ([fdo#111825]) -> [100]PASS +2 similar
>>             issues
>>      * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled:
>>           + {shard-rkl}: [101]SKIP ([fdo#111314]) -> [102]PASS +3 similar
>>             issues
>>      * igt@kms_fbcon_fbt@fbc-suspend:
>>           + shard-kbl: [103]INCOMPLETE ([i915#155] / [i915#180] /
>>             [i915#636]) -> [104]PASS
>>      * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
>>           + shard-apl: [105]DMESG-WARN ([i915#180]) -> [106]PASS +2
>>             similar issues
>>      * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
>>           + shard-skl: [107]FAIL ([i915#2122]) -> [108]PASS +1 similar
>>             issue
>>      * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap
>>        -gtt:
>>           + {shard-rkl}: [109]SKIP ([i915#1849]) -> [110]PASS +24 similar
>>             issues
>>      * igt@kms_hdr@bpc-switch-suspend:
>>           + shard-kbl: [111]DMESG-WARN ([i915#180]) -> [112]PASS +1
>>             similar issue
>>      * igt@kms_plane@pixel-format@pipe-a-planes:
>>           + {shard-rkl}: [113]SKIP ([i915#3558]) -> [114]PASS +1 similar
>>             issue
>>      * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>>           + shard-skl: [115]FAIL ([fdo#108145] / [i915#265]) -> [116]PASS
>>             +1 similar issue
>>      * igt@kms_psr@primary_blt:
>>           + {shard-rkl}: [117]SKIP ([i915#1072]) -> [118]PASS
>>      * igt@kms_psr@psr2_primary_page_flip:
>>           + shard-iclb: [119]SKIP ([fdo#109441]) -> [120]PASS +2 similar
>>             issues
>>      * igt@kms_vblank@pipe-c-query-forked-hang:
>>           + {shard-rkl}: [121]SKIP ([i915#1845]) -> [122]PASS +11 similar
>>             issues
>>      * igt@perf@blocking:
>>           + {shard-rkl}: [123]FAIL ([i915#1542]) -> [124]PASS
>>      * igt@perf@polling-parameterized:
>>           + shard-skl: [125]FAIL ([i915#1542]) -> [126]PASS
>>
>>     Warnings
>>
>>      * igt@gem_exec_fair@basic-none-rrul@rcs0:
>>           + shard-iclb: [127]FAIL ([i915#2852]) -> [128]FAIL ([i915#2842])
>>      * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
>>           + shard-iclb: [129]SKIP ([i915#2920]) -> [130]SKIP ([i915#658])
>>             +2 similar issues
>>      * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
>>           + shard-iclb: [131]SKIP ([i915#658]) -> [132]SKIP ([i915#2920])
>>             +2 similar issues
>>      * igt@runner@aborted:
>>           + shard-kbl: ([133]FAIL, [134]FAIL, [135]FAIL, [136]FAIL,
>>             [137]FAIL) ([i915#180] / [i915#1814] / [i915#2505] /
>>             [i915#3002] / [i915#3363] / [i915#92]) -> ([138]FAIL,
>>             [139]FAIL) ([i915#3002] / [i915#3363])
>>           + shard-apl: ([140]FAIL, [141]FAIL, [142]FAIL, [143]FAIL)
>>             ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) ->
>>             ([144]FAIL, [145]FAIL, [146]FAIL, [147]FAIL, [148]FAIL)
>>             ([i915#1610] / [i915#180] / [i915#1814] / [i915#3002] /
>>             [i915#3363])
>>           + shard-skl: ([149]FAIL, [150]FAIL, [151]FAIL) ([i915#1436] /
>>             [i915#3002] / [i915#3363]) -> ([152]FAIL, [153]FAIL)
>>             ([i915#3002] / [i915#3363])
>>
>>    {name}: Th
>>
>> References
>>
>>    1. https://patchwork.freedesktop.org/series/92969/
>>    2. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/index.html
>>    3. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk8/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html
>>    4. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk1/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html
>>    5. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@feature_discovery@psr2.html
>>    6. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@feature_discovery@psr2.html
>>    7. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb6/igt@gem_ctx_persistence@engines-queued.html
>>    8. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl2/igt@gem_eio@in-flight-suspend.html
>>    9. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl6/igt@gem_eio@in-flight-suspend.html
>>   10. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk8/igt@gem_exec_fair@basic-deadline.html
>>   11. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk1/igt@gem_exec_fair@basic-deadline.html
>>   12. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>>   13. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>>   14. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl4/igt@gem_exec_fair@basic-none@vcs1.html
>>   15. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl2/igt@gem_exec_fair@basic-none@vcs1.html
>>   16. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb5/igt@gem_exec_fair@basic-pace@rcs0.html
>>   17. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb2/igt@gem_exec_fair@basic-pace@rcs0.html
>>   18. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
>>   19. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl4/igt@gem_exec_schedule@pi-ringfull@vecs0.html
>>   20. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl8/igt@gem_exec_schedule@pi-ringfull@vecs0.html
>>   21. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@gem_userptr_blits@dmabuf-sync.html
>>   22. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb6/igt@gem_userptr_blits@input-checking.html
>>   23. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb1/igt@i915_pm_rpm@drm-resources-equal.html
>>   24. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip.html
>>   25. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
>>   26. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk7/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
>>   27. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
>>   28. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
>>   29. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
>>   30. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb1/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
>>   31. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb1/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs.html
>>   32. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl3/igt@kms_chamelium@dp-mode-timings.html
>>   33. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
>>   34. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
>>   35. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl7/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
>>   36. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_content_protection@atomic-dpms.html
>>   37. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_cursor_legacy@pipe-d-single-bo.html
>>   38. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_cursor_legacy@pipe-d-torture-bo.html
>>   39. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
>>   40. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
>>   41. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
>>   42. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
>>   43. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
>>   44. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
>>   45. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
>>   46. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
>>   47. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html
>>   48. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl2/igt@kms_flip@flip-vs-expired-vblank@b-dp1.html
>>   49. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
>>   50. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
>>   51. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
>>   52. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
>>   53. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
>>   54. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
>>   55. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
>>   56. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
>>   57. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_plane_lowres@pipe-b-tiling-yf.html
>>   58. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
>>   59. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@kms_psr2_su@frontbuffer.html
>>   60. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
>>   61. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
>>   62. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-snb6/igt@kms_setmode@basic.html
>>   63. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@kms_sysfs_edid_timing.html
>>   64. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-glk4/igt@kms_vblank@pipe-b-accuracy-idle.html
>>   65. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-glk3/igt@kms_vblank@pipe-b-accuracy-idle.html
>>   66. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@kms_vblank@pipe-d-wait-idle.html
>>   67. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@kms_writeback@writeback-fb-id.html
>>   68. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb5/igt@perf@polling-parameterized.html
>>   69. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb2/igt@perf@polling-parameterized.html
>>   70. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl2/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
>>   71. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@prime_nv_api@i915_self_import.html
>>   72. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl8/igt@sysfs_clients@fair-7.html
>>   73. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@gem_ctx_persistence@engines-hang@rcs0.html
>>   74. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@rcs0.html
>>   75. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl3/igt@gem_exec_fair@basic-deadline.html
>>   76. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
>>   77. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
>>   78. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
>>   79. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
>>   80. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
>>   81. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@gem_exec_fair@basic-none@bcs0.html
>>   82. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@gem_exec_fair@basic-none@bcs0.html
>>   83. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@gen9_exec_parse@allowed-single.html
>>   84. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@gen9_exec_parse@allowed-single.html
>>   85. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@i915_pm_backlight@fade.html
>>   86. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@i915_pm_backlight@fade.html
>>   87. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-tglb6/igt@i915_pm_rc6_residency@rc6-fence.html
>>   88. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-tglb7/igt@i915_pm_rc6_residency@rc6-fence.html
>>   89. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html
>>   90. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html
>>   91. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
>>   92. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
>>   93. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
>>   94. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
>>   95. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_color@pipe-c-ctm-max.html
>>   96. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_color@pipe-c-ctm-max.html
>>   97. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
>>   98. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
>>   99. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
>>  100. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
>>  101. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
>>  102. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
>>  103. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
>>  104. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
>>  105. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
>>  106. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
>>  107. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
>>  108. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
>>  109. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
>>  110. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
>>  111. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html
>>  112. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html
>>  113. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_plane@pixel-format@pipe-a-planes.html
>>  114. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_plane@pixel-format@pipe-a-planes.html
>>  115. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>>  116. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>>  117. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_psr@primary_blt.html
>>  118. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_psr@primary_blt.html
>>  119. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
>>  120. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
>>  121. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-2/igt@kms_vblank@pipe-c-query-forked-hang.html
>>  122. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@kms_vblank@pipe-c-query-forked-hang.html
>>  123. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-rkl-6/igt@perf@blocking.html
>>  124. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-rkl-6/igt@perf@blocking.html
>>  125. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@perf@polling-parameterized.html
>>  126. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl4/igt@perf@polling-parameterized.html
>>  127. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>>  128. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
>>  129. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
>>  130. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
>>  131. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
>>  132. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
>>  133. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl7/igt@runner@aborted.html
>>  134. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl3/igt@runner@aborted.html
>>  135. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl6/igt@runner@aborted.html
>>  136. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl7/igt@runner@aborted.html
>>  137. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-kbl3/igt@runner@aborted.html
>>  138. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl4/igt@runner@aborted.html
>>  139. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-kbl3/igt@runner@aborted.html
>>  140. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl6/igt@runner@aborted.html
>>  141. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl1/igt@runner@aborted.html
>>  142. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl2/igt@runner@aborted.html
>>  143. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-apl7/igt@runner@aborted.html
>>  144. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@runner@aborted.html
>>  145. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl6/igt@runner@aborted.html
>>  146. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl1/igt@runner@aborted.html
>>  147. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl6/igt@runner@aborted.html
>>  148. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-apl3/igt@runner@aborted.html
>>  149. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl8/igt@runner@aborted.html
>>  150. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl5/igt@runner@aborted.html
>>  151. https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10383/shard-skl3/igt@runner@aborted.html
>>  152. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl1/igt@runner@aborted.html
>>  153. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/shard-skl10/igt@runner@aborted.html
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