* [Intel-gfx] [RFC PATCH 00/25] refactor display struct
@ 2021-09-07 7:25 Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 01/25] drm/i915: move display funcs into a display struct. (v3) Dave Airlie
` (27 more replies)
0 siblings, 28 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
This is a reworked version of the complete series into a _display
pointed to by display for now. There is a fair few places the
abstraction leaks around container_of, these need to be resolved
to move the code into cleaner separation.
I might also have been over-zealous moving stuff, or not zealous
enough.
Dave.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 01/25] drm/i915: move display funcs into a display struct. (v3)
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 02/25] drm/i915/display: move cdclk info into display Dave Airlie
` (26 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
This is the first step in an idea to refactor the display code
into a bit more of a corner.
v2: move display to being a pointer.
v3: add missing pointer setup line
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 24 +--
drivers/gpu/drm/i915/display/intel_cdclk.c | 148 +++++++++---------
drivers/gpu/drm/i915/display/intel_color.c | 64 ++++----
drivers/gpu/drm/i915/display/intel_display.c | 110 ++++++-------
.../drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 16 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 6 +-
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 11 +-
drivers/gpu/drm/i915/i915_irq.c | 14 +-
drivers/gpu/drm/i915/intel_pm.c | 104 ++++++------
12 files changed, 255 insertions(+), 249 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 532237588511..c8c7847498e1 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->display.audio_codec_enable)
- dev_priv->display.audio_codec_enable(encoder,
+ if (dev_priv->display->funcs.audio_codec_enable)
+ dev_priv->display->funcs.audio_codec_enable(encoder,
crtc_state,
conn_state);
@@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->display.audio_codec_disable)
- dev_priv->display.audio_codec_disable(encoder,
+ if (dev_priv->display->funcs.audio_codec_disable)
+ dev_priv->display->funcs.audio_codec_disable(encoder,
old_crtc_state,
old_conn_state);
@@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
- dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
+ dev_priv->display->funcs.audio_codec_enable = g4x_audio_codec_enable;
+ dev_priv->display->funcs.audio_codec_disable = g4x_audio_codec_disable;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->display->funcs.audio_codec_enable = ilk_audio_codec_enable;
+ dev_priv->display->funcs.audio_codec_disable = ilk_audio_codec_disable;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
- dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
+ dev_priv->display->funcs.audio_codec_enable = hsw_audio_codec_enable;
+ dev_priv->display->funcs.audio_codec_disable = hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->display->funcs.audio_codec_enable = ilk_audio_codec_enable;
+ dev_priv->display->funcs.audio_codec_disable = ilk_audio_codec_disable;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 34fa4130d5c4..1aa45b46f317 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1466,7 +1466,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
* at least what the CDCLK frequency requires.
*/
cdclk_config->voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
+ dev_priv->display->funcs.calc_voltage_level(cdclk_config->cdclk);
}
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1777,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ dev_priv->display->funcs.calc_voltage_level(cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
@@ -1789,7 +1789,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ dev_priv->display->funcs.calc_voltage_level(cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
}
@@ -1932,7 +1932,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
+ if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display->funcs.set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -1956,7 +1956,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
&dev_priv->gmbus_mutex);
}
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->display->funcs.set_cdclk(dev_priv, cdclk_config, pipe);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2414,7 +2414,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->logical.cdclk = cdclk;
cdclk_state->logical.voltage_level =
max_t(int, min_voltage_level,
- dev_priv->display.calc_voltage_level(cdclk));
+ dev_priv->display->funcs.calc_voltage_level(cdclk));
if (!cdclk_state->active_pipes) {
cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2423,7 +2423,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
cdclk_state->actual.vco = vco;
cdclk_state->actual.cdclk = cdclk;
cdclk_state->actual.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk);
+ dev_priv->display->funcs.calc_voltage_level(cdclk);
} else {
cdclk_state->actual = cdclk_state->logical;
}
@@ -2515,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
new_cdclk_state->active_pipes =
intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
- ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
+ ret = dev_priv->display->funcs.modeset_calc_cdclk(new_cdclk_state);
if (ret)
return ret;
@@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
*/
void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
- dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
+ dev_priv->display->funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
/*
* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
@@ -2852,119 +2852,119 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display->funcs.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display->funcs.calc_voltage_level = tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display->funcs.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display->funcs.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
+ dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display->funcs.calc_voltage_level = ehl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
+ dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display->funcs.calc_voltage_level = icl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
+ dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+ dev_priv->display->funcs.calc_voltage_level = bxt_calc_voltage_level;
if (IS_GEMINILAKE(dev_priv))
dev_priv->cdclk.table = glk_cdclk_table;
else
dev_priv->cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = skl_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->display->funcs.set_cdclk = skl_set_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = skl_modeset_calc_cdclk;
} else if (IS_BROADWELL(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = bdw_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->display->funcs.set_cdclk = bdw_set_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = chv_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->display->funcs.set_cdclk = chv_set_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.set_cdclk = vlv_set_cdclk;
- dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->display->funcs.set_cdclk = vlv_set_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
} else {
- dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
+ dev_priv->display->funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+ dev_priv->display->funcs.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
}
if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
- dev_priv->display.get_cdclk = bxt_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = bxt_get_cdclk;
else if (DISPLAY_VER(dev_priv) == 9)
- dev_priv->display.get_cdclk = skl_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = skl_get_cdclk;
else if (IS_BROADWELL(dev_priv))
- dev_priv->display.get_cdclk = bdw_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = bdw_get_cdclk;
else if (IS_HASWELL(dev_priv))
- dev_priv->display.get_cdclk = hsw_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = hsw_get_cdclk;
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->display.get_cdclk = vlv_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = vlv_get_cdclk;
else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = fixed_400mhz_get_cdclk;
else if (IS_IRONLAKE(dev_priv))
- dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = fixed_450mhz_get_cdclk;
else if (IS_GM45(dev_priv))
- dev_priv->display.get_cdclk = gm45_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = gm45_get_cdclk;
else if (IS_G45(dev_priv))
- dev_priv->display.get_cdclk = g33_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = g33_get_cdclk;
else if (IS_I965GM(dev_priv))
- dev_priv->display.get_cdclk = i965gm_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = i965gm_get_cdclk;
else if (IS_I965G(dev_priv))
- dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = fixed_400mhz_get_cdclk;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->display.get_cdclk = pnv_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = pnv_get_cdclk;
else if (IS_G33(dev_priv))
- dev_priv->display.get_cdclk = g33_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = g33_get_cdclk;
else if (IS_I945GM(dev_priv))
- dev_priv->display.get_cdclk = i945gm_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = i945gm_get_cdclk;
else if (IS_I945G(dev_priv))
- dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = fixed_400mhz_get_cdclk;
else if (IS_I915GM(dev_priv))
- dev_priv->display.get_cdclk = i915gm_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = i915gm_get_cdclk;
else if (IS_I915G(dev_priv))
- dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = fixed_333mhz_get_cdclk;
else if (IS_I865G(dev_priv))
- dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = fixed_266mhz_get_cdclk;
else if (IS_I85X(dev_priv))
- dev_priv->display.get_cdclk = i85x_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = i85x_get_cdclk;
else if (IS_I845G(dev_priv))
- dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = fixed_200mhz_get_cdclk;
else if (IS_I830(dev_priv))
- dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = fixed_133mhz_get_cdclk;
- if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,
+ if (drm_WARN(&dev_priv->drm, !dev_priv->display->funcs.get_cdclk,
"Unknown platform. Assuming 133 MHz CDCLK\n"))
- dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
+ dev_priv->display->funcs.get_cdclk = fixed_133mhz_get_cdclk;
}
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index afcb4bf3826c..b1eac554a4b3 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.load_luts(crtc_state);
+ dev_priv->display->funcs.load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.color_commit(crtc_state);
+ dev_priv->display->funcs.color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->display.color_check(crtc_state);
+ return dev_priv->display->funcs.color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->display.read_luts)
- dev_priv->display.read_luts(crtc_state);
+ if (dev_priv->display->funcs.read_luts)
+ dev_priv->display->funcs.read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.color_check = chv_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = chv_load_luts;
- dev_priv->display.read_luts = chv_read_luts;
+ dev_priv->display->funcs.color_check = chv_color_check;
+ dev_priv->display->funcs.color_commit = i9xx_color_commit;
+ dev_priv->display->funcs.load_luts = chv_load_luts;
+ dev_priv->display->funcs.read_luts = chv_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 4) {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i965_load_luts;
- dev_priv->display.read_luts = i965_read_luts;
+ dev_priv->display->funcs.color_check = i9xx_color_check;
+ dev_priv->display->funcs.color_commit = i9xx_color_commit;
+ dev_priv->display->funcs.load_luts = i965_load_luts;
+ dev_priv->display->funcs.read_luts = i965_read_luts;
} else {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i9xx_load_luts;
- dev_priv->display.read_luts = i9xx_read_luts;
+ dev_priv->display->funcs.color_check = i9xx_color_check;
+ dev_priv->display->funcs.color_commit = i9xx_color_commit;
+ dev_priv->display->funcs.load_luts = i9xx_load_luts;
+ dev_priv->display->funcs.read_luts = i9xx_read_luts;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.color_check = icl_color_check;
+ dev_priv->display->funcs.color_check = icl_color_check;
else if (DISPLAY_VER(dev_priv) >= 10)
- dev_priv->display.color_check = glk_color_check;
+ dev_priv->display->funcs.color_check = glk_color_check;
else if (DISPLAY_VER(dev_priv) >= 7)
- dev_priv->display.color_check = ivb_color_check;
+ dev_priv->display->funcs.color_check = ivb_color_check;
else
- dev_priv->display.color_check = ilk_color_check;
+ dev_priv->display->funcs.color_check = ilk_color_check;
if (DISPLAY_VER(dev_priv) >= 9)
- dev_priv->display.color_commit = skl_color_commit;
+ dev_priv->display->funcs.color_commit = skl_color_commit;
else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- dev_priv->display.color_commit = hsw_color_commit;
+ dev_priv->display->funcs.color_commit = hsw_color_commit;
else
- dev_priv->display.color_commit = ilk_color_commit;
+ dev_priv->display->funcs.color_commit = ilk_color_commit;
if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->display.load_luts = icl_load_luts;
- dev_priv->display.read_luts = icl_read_luts;
+ dev_priv->display->funcs.load_luts = icl_load_luts;
+ dev_priv->display->funcs.read_luts = icl_read_luts;
} else if (DISPLAY_VER(dev_priv) == 10) {
- dev_priv->display.load_luts = glk_load_luts;
- dev_priv->display.read_luts = glk_read_luts;
+ dev_priv->display->funcs.load_luts = glk_load_luts;
+ dev_priv->display->funcs.read_luts = glk_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->display.load_luts = bdw_load_luts;
+ dev_priv->display->funcs.load_luts = bdw_load_luts;
} else if (DISPLAY_VER(dev_priv) >= 7) {
- dev_priv->display.load_luts = ivb_load_luts;
+ dev_priv->display->funcs.load_luts = ivb_load_luts;
} else {
- dev_priv->display.load_luts = ilk_load_luts;
- dev_priv->display.read_luts = ilk_read_luts;
+ dev_priv->display->funcs.load_luts = ilk_load_luts;
+ dev_priv->display->funcs.read_luts = ilk_read_luts;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1f447ba776c7..aabc1badb517 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2060,7 +2060,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
assert_pch_transcoder_disabled(dev_priv, pipe);
/* For PCH output, training FDI link */
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ dev_priv->display->funcs.fdi_link_train(crtc, crtc_state);
/* We need to program the right clock selection before writing the pixel
* mutliplier into the DPLL. */
@@ -2526,8 +2526,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
* we'll continue to update watermarks the old way, if flags tell
* us to.
*/
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->display->funcs.initial_watermarks)
+ dev_priv->display->funcs.initial_watermarks(state, crtc);
else if (new_crtc_state->update_wm_pre)
intel_update_watermarks(crtc);
}
@@ -2901,8 +2901,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->display->funcs.initial_watermarks)
+ dev_priv->display->funcs.initial_watermarks(state, crtc);
intel_enable_pipe(new_crtc_state);
if (new_crtc_state->has_pch_encoder)
@@ -3112,8 +3112,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) >= 11)
icl_set_pipe_chicken(new_crtc_state);
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->display->funcs.initial_watermarks)
+ dev_priv->display->funcs.initial_watermarks(state, crtc);
if (DISPLAY_VER(dev_priv) >= 11) {
const struct intel_dbuf_state *dbuf_state =
@@ -3530,7 +3530,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
- dev_priv->display.initial_watermarks(state, crtc);
+ dev_priv->display->funcs.initial_watermarks(state, crtc);
intel_enable_pipe(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3573,8 +3573,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(new_crtc_state);
- if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->display->funcs.initial_watermarks)
+ dev_priv->display->funcs.initial_watermarks(state, crtc);
else
intel_update_watermarks(crtc);
intel_enable_pipe(new_crtc_state);
@@ -3642,7 +3642,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->display.initial_watermarks)
+ if (!dev_priv->display->funcs.initial_watermarks)
intel_update_watermarks(crtc);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -3696,7 +3696,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
+ dev_priv->display->funcs.crtc_disable(to_intel_atomic_state(state), crtc);
drm_atomic_state_put(state);
@@ -5901,7 +5901,7 @@ static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- if (!i915->display.get_pipe_config(crtc, crtc_state))
+ if (!i915->display->funcs.get_pipe_config(crtc, crtc_state))
return false;
crtc_state->hw.active = true;
@@ -6728,10 +6728,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->display.crtc_compute_clock &&
+ dev_priv->display->funcs.crtc_compute_clock &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->display.crtc_compute_clock(crtc_state);
+ ret = dev_priv->display->funcs.crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -6750,8 +6750,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
return ret;
}
- if (dev_priv->display.compute_pipe_wm) {
- ret = dev_priv->display.compute_pipe_wm(state, crtc);
+ if (dev_priv->display->funcs.compute_pipe_wm) {
+ ret = dev_priv->display->funcs.compute_pipe_wm(state, crtc);
if (ret) {
drm_dbg_kms(&dev_priv->drm,
"Target pipe watermarks are invalid\n");
@@ -6760,9 +6760,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
}
- if (dev_priv->display.compute_intermediate_wm) {
+ if (dev_priv->display->funcs.compute_intermediate_wm) {
if (drm_WARN_ON(&dev_priv->drm,
- !dev_priv->display.compute_pipe_wm))
+ !dev_priv->display->funcs.compute_pipe_wm))
return 0;
/*
@@ -6770,7 +6770,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
* old state and the new state. We can program these
* immediately.
*/
- ret = dev_priv->display.compute_intermediate_wm(state, crtc);
+ ret = dev_priv->display->funcs.compute_intermediate_wm(state, crtc);
if (ret) {
drm_dbg_kms(&dev_priv->drm,
"No valid intermediate pipe watermarks are possible\n");
@@ -8767,7 +8767,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->display.crtc_compute_clock)
+ if (!dev_priv->display->funcs.crtc_compute_clock)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
@@ -8879,8 +8879,8 @@ static int calc_watermark_data(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(dev);
/* Is there platform-specific watermark information to calculate? */
- if (dev_priv->display.compute_global_watermarks)
- return dev_priv->display.compute_global_watermarks(state);
+ if (dev_priv->display->funcs.compute_global_watermarks)
+ return dev_priv->display->funcs.compute_global_watermarks(state);
return 0;
}
@@ -9080,7 +9080,7 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
*need_cdclk_calc = true;
- ret = dev_priv->display.bw_calc_min_cdclk(state);
+ ret = dev_priv->display->funcs.bw_calc_min_cdclk(state);
if (ret)
return ret;
@@ -9705,8 +9705,8 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
- if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state, crtc);
+ if (dev_priv->display->funcs.atomic_update_watermarks)
+ dev_priv->display->funcs.atomic_update_watermarks(state, crtc);
}
static void commit_pipe_post_planes(struct intel_atomic_state *state,
@@ -9738,7 +9738,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(state, crtc);
+ dev_priv->display->funcs.crtc_enable(state, crtc);
if (new_crtc_state->bigjoiner_slave)
return;
@@ -9826,7 +9826,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(state, crtc);
+ dev_priv->display->funcs.crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -9834,8 +9834,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
/* FIXME unify this for all platforms */
if (!new_crtc_state->hw.active &&
!HAS_GMCH(dev_priv) &&
- dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, crtc);
+ dev_priv->display->funcs.initial_watermarks)
+ dev_priv->display->funcs.initial_watermarks(state, crtc);
}
static void intel_commit_modeset_disables(struct intel_atomic_state *state)
@@ -10206,7 +10206,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
- dev_priv->display.commit_modeset_enables(state);
+ dev_priv->display->funcs.commit_modeset_enables(state);
if (state->modeset) {
intel_encoders_update_complete(state);
@@ -10257,8 +10257,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
- if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state, crtc);
+ if (dev_priv->display->funcs.optimize_watermarks)
+ dev_priv->display->funcs.optimize_watermarks(state, crtc);
}
intel_dbuf_post_plane_update(state);
@@ -11225,36 +11225,36 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
intel_dpll_init_clock_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable = hsw_crtc_enable;
- dev_priv->display.crtc_disable = hsw_crtc_disable;
+ dev_priv->display->funcs.get_pipe_config = hsw_get_pipe_config;
+ dev_priv->display->funcs.crtc_enable = hsw_crtc_enable;
+ dev_priv->display->funcs.crtc_disable = hsw_crtc_disable;
} else if (HAS_DDI(dev_priv)) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable = hsw_crtc_enable;
- dev_priv->display.crtc_disable = hsw_crtc_disable;
+ dev_priv->display->funcs.get_pipe_config = hsw_get_pipe_config;
+ dev_priv->display->funcs.crtc_enable = hsw_crtc_enable;
+ dev_priv->display->funcs.crtc_disable = hsw_crtc_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.get_pipe_config = ilk_get_pipe_config;
- dev_priv->display.crtc_enable = ilk_crtc_enable;
- dev_priv->display.crtc_disable = ilk_crtc_disable;
+ dev_priv->display->funcs.get_pipe_config = ilk_get_pipe_config;
+ dev_priv->display->funcs.crtc_enable = ilk_crtc_enable;
+ dev_priv->display->funcs.crtc_disable = ilk_crtc_disable;
} else if (IS_CHERRYVIEW(dev_priv) ||
IS_VALLEYVIEW(dev_priv)) {
- dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
- dev_priv->display.crtc_enable = valleyview_crtc_enable;
- dev_priv->display.crtc_disable = i9xx_crtc_disable;
+ dev_priv->display->funcs.get_pipe_config = i9xx_get_pipe_config;
+ dev_priv->display->funcs.crtc_enable = valleyview_crtc_enable;
+ dev_priv->display->funcs.crtc_disable = i9xx_crtc_disable;
} else {
- dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
- dev_priv->display.crtc_enable = i9xx_crtc_enable;
- dev_priv->display.crtc_disable = i9xx_crtc_disable;
+ dev_priv->display->funcs.get_pipe_config = i9xx_get_pipe_config;
+ dev_priv->display->funcs.crtc_enable = i9xx_crtc_enable;
+ dev_priv->display->funcs.crtc_disable = i9xx_crtc_disable;
}
intel_fdi_init_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
- dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
+ dev_priv->display->funcs.commit_modeset_enables = skl_commit_modeset_enables;
+ dev_priv->display->funcs.get_initial_plane_config = skl_get_initial_plane_config;
} else {
- dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
- dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
+ dev_priv->display->funcs.commit_modeset_enables = intel_commit_modeset_enables;
+ dev_priv->display->funcs.get_initial_plane_config = i9xx_get_initial_plane_config;
}
}
@@ -11326,7 +11326,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->display.optimize_watermarks)
+ if (!dev_priv->display->funcs.optimize_watermarks)
return;
state = drm_atomic_state_alloc(&dev_priv->drm);
@@ -11359,7 +11359,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
/* Write calculated watermark values back */
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
crtc_state->wm.need_postvbl_update = true;
- dev_priv->display.optimize_watermarks(intel_state, crtc);
+ dev_priv->display->funcs.optimize_watermarks(intel_state, crtc);
to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
}
@@ -11683,7 +11683,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
* can even allow for smooth boot transitions if the BIOS
* fb is large enough for the active pipe configuration.
*/
- i915->display.get_initial_plane_config(crtc, &plane_config);
+ i915->display->funcs.get_initial_plane_config(crtc, &plane_config);
/*
* If the fb is shared between multiple heads, we'll
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cce1a926fcc1..b9195e614cd4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1195,7 +1195,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
+ dev_priv->display->funcs.get_cdclk(dev_priv, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
drm_WARN_ON(&dev_priv->drm,
intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 210f91f4a576..7b1dfb00d1b3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1367,21 +1367,21 @@ void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
+ dev_priv->display->funcs.crtc_compute_clock = hsw_crtc_compute_clock;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
+ dev_priv->display->funcs.crtc_compute_clock = ilk_crtc_compute_clock;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
+ dev_priv->display->funcs.crtc_compute_clock = chv_crtc_compute_clock;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
+ dev_priv->display->funcs.crtc_compute_clock = vlv_crtc_compute_clock;
else if (IS_G4X(dev_priv))
- dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
+ dev_priv->display->funcs.crtc_compute_clock = g4x_crtc_compute_clock;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
+ dev_priv->display->funcs.crtc_compute_clock = pnv_crtc_compute_clock;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
+ dev_priv->display->funcs.crtc_compute_clock = i9xx_crtc_compute_clock;
else
- dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
+ dev_priv->display->funcs.crtc_compute_clock = i8xx_crtc_compute_clock;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index fc09b781f15f..82b6c754c51b 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -1009,11 +1009,11 @@ void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->display.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->display->funcs.fdi_link_train = ilk_fdi_link_train;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->display->funcs.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->display->funcs.fdi_link_train = ivb_manual_fdi_link_train;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 47c85ac97c87..425da9f9c735 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
- i915->display.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->display->funcs.hpd_irq_setup)
+ i915->display->funcs.hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 59fb4c710c8c..87c3db974c4c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -770,6 +770,7 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
if (IS_ERR(i915))
return i915;
+ i915->display = &i915->_display;
pci_set_drvdata(pdev, i915);
/* Device parameters start as a copy of module parameters. */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be2392bbcecc..1a1d24557702 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -825,6 +825,11 @@ struct i915_selftest_stash {
struct ida mock_region_instances;
};
+struct drm_i915_display {
+ /* Display functions */
+ struct drm_i915_display_funcs funcs;
+};
+
struct drm_i915_private {
struct drm_device drm;
@@ -838,6 +843,9 @@ struct drm_i915_private {
struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
struct intel_driver_caps caps;
+ struct drm_i915_display _display;
+ struct drm_i915_display *display;
+
/**
* Data Stolen Memory - aka "i915 stolen memory" gives us the start and
* end of stolen which we can optionally use to create GEM objects
@@ -971,9 +979,6 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
- /* Display functions */
- struct drm_i915_display_funcs display;
-
/* PCH chipset type */
enum intel_pch pch_type;
unsigned short pch_id;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0a1681384c84..0b35ab7b421d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+ dev_priv->display->funcs.hpd_irq_setup = i915_hpd_irq_setup;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ dev_priv->display->funcs.hpd_irq_setup = dg1_hpd_irq_setup;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+ dev_priv->display->funcs.hpd_irq_setup = gen11_hpd_irq_setup;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ dev_priv->display->funcs.hpd_irq_setup = bxt_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
+ dev_priv->display->funcs.hpd_irq_setup = icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+ dev_priv->display->funcs.hpd_irq_setup = spt_hpd_irq_setup;
else
- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ dev_priv->display->funcs.hpd_irq_setup = ilk_hpd_irq_setup;
}
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfc41f8fa74a..acc3e88c28fe 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2347,7 +2347,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
else
wm_info = &i830_a_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
+ fifo_size = dev_priv->display->funcs.get_fifo_size(dev_priv, PLANE_A);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2374,7 +2374,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
if (DISPLAY_VER(dev_priv) == 2)
wm_info = &i830_bc_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
+ fifo_size = dev_priv->display->funcs.get_fifo_size(dev_priv, PLANE_B);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2490,7 +2490,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
pipe_mode = &crtc->config->hw.pipe_mode;
planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
&i845_wm_info,
- dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
+ dev_priv->display->funcs.get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
fwater_lo |= (3<<8) | planea_wm;
@@ -7167,8 +7167,8 @@ void intel_update_watermarks(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (dev_priv->display.update_wm)
- dev_priv->display.update_wm(crtc);
+ if (dev_priv->display->funcs.update_wm)
+ dev_priv->display->funcs.update_wm(crtc);
}
void intel_enable_ipc(struct drm_i915_private *dev_priv)
@@ -7910,7 +7910,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->display.init_clock_gating(dev_priv);
+ dev_priv->display->funcs.init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7937,52 +7937,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = adlp_init_clock_gating;
else if (IS_DG1(dev_priv))
- dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = dg1_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = gen12lp_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->display.init_clock_gating = icl_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = icl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = skl_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = skl_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = kbl_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
- dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = bxt_init_clock_gating;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->display.init_clock_gating = glk_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = glk_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
- dev_priv->display.init_clock_gating = bdw_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.init_clock_gating = chv_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = chv_init_clock_gating;
else if (IS_HASWELL(dev_priv))
- dev_priv->display.init_clock_gating = hsw_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = hsw_init_clock_gating;
else if (IS_IVYBRIDGE(dev_priv))
- dev_priv->display.init_clock_gating = ivb_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = ivb_init_clock_gating;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->display.init_clock_gating = vlv_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = vlv_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 6)
- dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = gen6_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 5)
- dev_priv->display.init_clock_gating = ilk_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = ilk_init_clock_gating;
else if (IS_G4X(dev_priv))
- dev_priv->display.init_clock_gating = g4x_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = g4x_init_clock_gating;
else if (IS_I965GM(dev_priv))
- dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = i965gm_init_clock_gating;
else if (IS_I965G(dev_priv))
- dev_priv->display.init_clock_gating = i965g_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = i965g_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 3)
- dev_priv->display.init_clock_gating = gen3_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = gen3_init_clock_gating;
else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
- dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = i85x_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 2)
- dev_priv->display.init_clock_gating = i830_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = i830_init_clock_gating;
else {
MISSING_CASE(INTEL_DEVID(dev_priv));
- dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ dev_priv->display->funcs.init_clock_gating = nop_init_clock_gating;
}
}
@@ -8001,7 +8001,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
/* For FIFO watermark updates */
if (DISPLAY_VER(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
- dev_priv->display.compute_global_watermarks = skl_compute_wm;
+ dev_priv->display->funcs.compute_global_watermarks = skl_compute_wm;
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
@@ -8009,12 +8009,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
(DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
- dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
- dev_priv->display.compute_intermediate_wm =
+ dev_priv->display->funcs.compute_pipe_wm = ilk_compute_pipe_wm;
+ dev_priv->display->funcs.compute_intermediate_wm =
ilk_compute_intermediate_wm;
- dev_priv->display.initial_watermarks =
+ dev_priv->display->funcs.initial_watermarks =
ilk_initial_watermarks;
- dev_priv->display.optimize_watermarks =
+ dev_priv->display->funcs.optimize_watermarks =
ilk_optimize_watermarks;
} else {
drm_dbg_kms(&dev_priv->drm,
@@ -8023,17 +8023,17 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
}
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev_priv);
- dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
- dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
- dev_priv->display.initial_watermarks = vlv_initial_watermarks;
- dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
- dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
+ dev_priv->display->funcs.compute_pipe_wm = vlv_compute_pipe_wm;
+ dev_priv->display->funcs.compute_intermediate_wm = vlv_compute_intermediate_wm;
+ dev_priv->display->funcs.initial_watermarks = vlv_initial_watermarks;
+ dev_priv->display->funcs.optimize_watermarks = vlv_optimize_watermarks;
+ dev_priv->display->funcs.atomic_update_watermarks = vlv_atomic_update_fifo;
} else if (IS_G4X(dev_priv)) {
g4x_setup_wm_latency(dev_priv);
- dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
- dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
- dev_priv->display.initial_watermarks = g4x_initial_watermarks;
- dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
+ dev_priv->display->funcs.compute_pipe_wm = g4x_compute_pipe_wm;
+ dev_priv->display->funcs.compute_intermediate_wm = g4x_compute_intermediate_wm;
+ dev_priv->display->funcs.initial_watermarks = g4x_initial_watermarks;
+ dev_priv->display->funcs.optimize_watermarks = g4x_optimize_watermarks;
} else if (IS_PINEVIEW(dev_priv)) {
if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
dev_priv->is_ddr3,
@@ -8047,21 +8047,21 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->fsb_freq, dev_priv->mem_freq);
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(dev_priv, false);
- dev_priv->display.update_wm = NULL;
+ dev_priv->display->funcs.update_wm = NULL;
} else
- dev_priv->display.update_wm = pnv_update_wm;
+ dev_priv->display->funcs.update_wm = pnv_update_wm;
} else if (DISPLAY_VER(dev_priv) == 4) {
- dev_priv->display.update_wm = i965_update_wm;
+ dev_priv->display->funcs.update_wm = i965_update_wm;
} else if (DISPLAY_VER(dev_priv) == 3) {
- dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
+ dev_priv->display->funcs.update_wm = i9xx_update_wm;
+ dev_priv->display->funcs.get_fifo_size = i9xx_get_fifo_size;
} else if (DISPLAY_VER(dev_priv) == 2) {
if (INTEL_NUM_PIPES(dev_priv) == 1) {
- dev_priv->display.update_wm = i845_update_wm;
- dev_priv->display.get_fifo_size = i845_get_fifo_size;
+ dev_priv->display->funcs.update_wm = i845_update_wm;
+ dev_priv->display->funcs.get_fifo_size = i845_get_fifo_size;
} else {
- dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i830_get_fifo_size;
+ dev_priv->display->funcs.update_wm = i9xx_update_wm;
+ dev_priv->display->funcs.get_fifo_size = i830_get_fifo_size;
}
} else {
drm_err(&dev_priv->drm,
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 02/25] drm/i915/display: move cdclk info into display
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 01/25] drm/i915: move display funcs into a display struct. (v3) Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 03/25] drm/i915: move more pll/clocks into display struct Dave Airlie
` (25 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 4 +-
.../gpu/drm/i915/display/intel_backlight.c | 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 196 +++++++++---------
drivers/gpu/drm/i915/display/intel_cdclk.h | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 16 +-
.../drm/i915/display/intel_display_power.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 23 +-
13 files changed, 136 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index c8c7847498e1..671af864fe0b 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -530,7 +530,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
vdsc_bpp = crtc_state->dsc.compressed_bpp;
- cdclk = i915->cdclk.hw.cdclk;
+ cdclk = i915->display->cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261;
link_clk = crtc_state->port_clock;
@@ -1076,7 +1076,7 @@ static int i915_audio_component_get_cdclk_freq(struct device *kdev)
if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
return -ENODEV;
- return dev_priv->cdclk.hw.cdclk;
+ return dev_priv->display->cdclk.hw.cdclk;
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 9523411cddd8..41e10d1afe72 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1108,7 +1108,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
if (IS_PINEVIEW(dev_priv))
clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
else
- clock = KHz(dev_priv->cdclk.hw.cdclk);
+ clock = KHz(dev_priv->display->cdclk.hw.cdclk);
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32);
}
@@ -1126,7 +1126,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
if (IS_G4X(dev_priv))
clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
else
- clock = KHz(dev_priv->cdclk.hw.cdclk);
+ clock = KHz(dev_priv->display->cdclk.hw.cdclk);
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128);
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 1aa45b46f317..e9152c8fb63a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -506,7 +506,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
else
default_credits = PFI_CREDIT(8);
- if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
+ if (dev_priv->display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
/* CHV suggested value is 31 or 63 */
if (IS_CHERRYVIEW(dev_priv))
credits = PFI_CREDIT_63;
@@ -985,7 +985,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
drm_err(&dev_priv->drm, "DPLL0 not locked\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display->cdclk.hw.vco = vco;
/* We'll want to keep using the current vco from now on. */
skl_set_preferred_cdclk_vco(dev_priv, vco);
@@ -999,7 +999,7 @@ static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display->cdclk.hw.vco = 0;
}
static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
@@ -1008,7 +1008,7 @@ static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
switch (cdclk) {
default:
drm_WARN_ON(&dev_priv->drm,
- cdclk != dev_priv->cdclk.hw.bypass);
+ cdclk != dev_priv->display->cdclk.hw.bypass);
drm_WARN_ON(&dev_priv->drm, vco != 0);
fallthrough;
case 308571:
@@ -1057,13 +1057,13 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display->cdclk.hw.vco != 0 &&
+ dev_priv->display->cdclk.hw.vco != vco)
skl_dpll0_disable(dev_priv);
cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
- if (dev_priv->cdclk.hw.vco != vco) {
+ if (dev_priv->display->cdclk.hw.vco != vco) {
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
@@ -1075,7 +1075,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
intel_de_posting_read(dev_priv, CDCLK_CTL);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display->cdclk.hw.vco != vco)
skl_dpll0_enable(dev_priv, vco);
/* Wa Display #1183: skl,kbl,cfl */
@@ -1110,11 +1110,11 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
goto sanitize;
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_dump_cdclk_config(&dev_priv->display->cdclk.hw, "Current CDCLK");
/* Is PLL enabled and locked ? */
- if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+ if (dev_priv->display->cdclk.hw.vco == 0 ||
+ dev_priv->display->cdclk.hw.cdclk == dev_priv->display->cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
@@ -1125,7 +1125,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
*/
cdctl = intel_de_read(dev_priv, CDCLK_CTL);
expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
- skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
+ skl_cdclk_decimal(dev_priv->display->cdclk.hw.cdclk);
if (cdctl == expected)
/* All well; nothing to sanitize */
return;
@@ -1134,9 +1134,9 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
/* force cdclk programming */
- dev_priv->cdclk.hw.cdclk = 0;
+ dev_priv->display->cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
- dev_priv->cdclk.hw.vco = -1;
+ dev_priv->display->cdclk.hw.vco = -1;
}
static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
@@ -1145,19 +1145,19 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
skl_sanitize_cdclk(dev_priv);
- if (dev_priv->cdclk.hw.cdclk != 0 &&
- dev_priv->cdclk.hw.vco != 0) {
+ if (dev_priv->display->cdclk.hw.cdclk != 0 &&
+ dev_priv->display->cdclk.hw.vco != 0) {
/*
* Use the current vco as our initial
* guess as to what the preferred vco is.
*/
if (dev_priv->skl_preferred_vco_freq == 0)
skl_set_preferred_cdclk_vco(dev_priv,
- dev_priv->cdclk.hw.vco);
+ dev_priv->display->cdclk.hw.vco);
return;
}
- cdclk_config = dev_priv->cdclk.hw;
+ cdclk_config = dev_priv->display->cdclk.hw;
cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
if (cdclk_config.vco == 0)
@@ -1170,7 +1170,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
+ struct intel_cdclk_config cdclk_config = dev_priv->display->cdclk.hw;
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
@@ -1291,35 +1291,35 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ const struct intel_cdclk_vals *table = dev_priv->display->cdclk.table;
int i;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+ if (table[i].refclk == dev_priv->display->cdclk.hw.ref &&
table[i].cdclk >= min_cdclk)
return table[i].cdclk;
drm_WARN(&dev_priv->drm, 1,
"Cannot satisfy minimum cdclk %d with refclk %u\n",
- min_cdclk, dev_priv->cdclk.hw.ref);
+ min_cdclk, dev_priv->display->cdclk.hw.ref);
return 0;
}
static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ const struct intel_cdclk_vals *table = dev_priv->display->cdclk.table;
int i;
- if (cdclk == dev_priv->cdclk.hw.bypass)
+ if (cdclk == dev_priv->display->cdclk.hw.bypass)
return 0;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+ if (table[i].refclk == dev_priv->display->cdclk.hw.ref &&
table[i].cdclk == cdclk)
- return dev_priv->cdclk.hw.ref * table[i].ratio;
+ return dev_priv->display->cdclk.hw.ref * table[i].ratio;
drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
- cdclk, dev_priv->cdclk.hw.ref);
+ cdclk, dev_priv->display->cdclk.hw.ref);
return 0;
}
@@ -1478,12 +1478,12 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display->cdclk.hw.vco = 0;
}
static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display->cdclk.hw.ref);
intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
@@ -1495,7 +1495,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display->cdclk.hw.vco = vco;
}
static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
@@ -1507,12 +1507,12 @@ static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display->cdclk.hw.vco = 0;
}
static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display->cdclk.hw.ref);
u32 val;
val = ICL_CDCLK_PLL_RATIO(ratio);
@@ -1525,12 +1525,12 @@ static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display->cdclk.hw.vco = vco;
}
static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display->cdclk.hw.ref);
u32 val;
/* Write PLL ratio without disabling */
@@ -1549,7 +1549,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
val &= ~BXT_DE_PLL_FREQ_REQ;
intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display->cdclk.hw.vco = vco;
}
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
@@ -1579,7 +1579,7 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
default:
drm_WARN_ON(&dev_priv->drm,
- cdclk != dev_priv->cdclk.hw.bypass);
+ cdclk != dev_priv->display->cdclk.hw.bypass);
drm_WARN_ON(&dev_priv->drm, vco != 0);
fallthrough;
case 2:
@@ -1624,22 +1624,22 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
- if (dev_priv->cdclk.hw.vco != vco)
+ if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display->cdclk.hw.vco > 0 && vco > 0) {
+ if (dev_priv->display->cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
} else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display->cdclk.hw.vco != 0 &&
+ dev_priv->display->cdclk.hw.vco != vco)
icl_cdclk_pll_disable(dev_priv);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display->cdclk.hw.vco != vco)
icl_cdclk_pll_enable(dev_priv, vco);
} else {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display->cdclk.hw.vco != 0 &&
+ dev_priv->display->cdclk.hw.vco != vco)
bxt_de_pll_disable(dev_priv);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display->cdclk.hw.vco != vco)
bxt_de_pll_enable(dev_priv, vco);
}
@@ -1689,7 +1689,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* Can't read out the voltage level :(
* Let's just assume everything is as expected.
*/
- dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
+ dev_priv->display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
}
static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
@@ -1698,10 +1698,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
int cdclk, vco;
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_dump_cdclk_config(&dev_priv->display->cdclk.hw, "Current CDCLK");
- if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+ if (dev_priv->display->cdclk.hw.vco == 0 ||
+ dev_priv->display->cdclk.hw.cdclk == dev_priv->display->cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
@@ -1719,28 +1719,28 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
/* Make sure this is a legal cdclk value for the platform */
- cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
- if (cdclk != dev_priv->cdclk.hw.cdclk)
+ cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display->cdclk.hw.cdclk);
+ if (cdclk != dev_priv->display->cdclk.hw.cdclk)
goto sanitize;
/* Make sure the VCO is correct for the cdclk */
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
- if (vco != dev_priv->cdclk.hw.vco)
+ if (vco != dev_priv->display->cdclk.hw.vco)
goto sanitize;
expected = skl_cdclk_decimal(cdclk);
/* Figure out what CD2X divider we should be using for this cdclk */
expected |= bxt_cdclk_cd2x_div_sel(dev_priv,
- dev_priv->cdclk.hw.cdclk,
- dev_priv->cdclk.hw.vco);
+ dev_priv->display->cdclk.hw.cdclk,
+ dev_priv->display->cdclk.hw.vco);
/*
* Disable SSA Precharge when CD clock frequency < 500 MHz,
* enable otherwise.
*/
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
- dev_priv->cdclk.hw.cdclk >= 500000)
+ dev_priv->display->cdclk.hw.cdclk >= 500000)
expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
if (cdctl == expected)
@@ -1751,10 +1751,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
/* force cdclk programming */
- dev_priv->cdclk.hw.cdclk = 0;
+ dev_priv->display->cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
- dev_priv->cdclk.hw.vco = -1;
+ dev_priv->display->cdclk.hw.vco = -1;
}
static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
@@ -1763,11 +1763,11 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
bxt_sanitize_cdclk(dev_priv);
- if (dev_priv->cdclk.hw.cdclk != 0 &&
- dev_priv->cdclk.hw.vco != 0)
+ if (dev_priv->display->cdclk.hw.cdclk != 0 &&
+ dev_priv->display->cdclk.hw.vco != 0)
return;
- cdclk_config = dev_priv->cdclk.hw;
+ cdclk_config = dev_priv->display->cdclk.hw;
/*
* FIXME:
@@ -1784,7 +1784,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
+ struct intel_cdclk_config cdclk_config = dev_priv->display->cdclk.hw;
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
@@ -1798,7 +1798,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
* intel_cdclk_init_hw - Initialize CDCLK hardware
* @i915: i915 device
*
- * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
+ * Initialize CDCLK. This consists mainly of initializing dev_priv->display->cdclk.hw and
* sanitizing the state of the hardware if needed. This is generally done only
* during the display core initialization sequence, after which the DMC will
* take care of turning CDCLK off/on as needed.
@@ -1929,7 +1929,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
{
struct intel_encoder *encoder;
- if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
+ if (!intel_cdclk_changed(&dev_priv->display->cdclk.hw, cdclk_config))
return;
if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display->funcs.set_cdclk))
@@ -1972,9 +1972,9 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
}
if (drm_WARN(&dev_priv->drm,
- intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
+ intel_cdclk_changed(&dev_priv->display->cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
+ intel_dump_cdclk_config(&dev_priv->display->cdclk.hw, "[hw state]");
intel_dump_cdclk_config(cdclk_config, "[sw state]");
}
}
@@ -2155,13 +2155,13 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
*/
min_cdclk = max_t(int, min_cdclk,
min_t(int, crtc_state->pixel_rate,
- dev_priv->max_cdclk_freq));
+ dev_priv->display->max_cdclk_freq));
}
- if (min_cdclk > dev_priv->max_cdclk_freq) {
+ if (min_cdclk > dev_priv->display->max_cdclk_freq) {
drm_dbg_kms(&dev_priv->drm,
"required cdclk (%d kHz) exceeds max (%d kHz)\n",
- min_cdclk, dev_priv->max_cdclk_freq);
+ min_cdclk, dev_priv->display->max_cdclk_freq);
return -EINVAL;
}
@@ -2477,7 +2477,7 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *cdclk_state;
- cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
+ cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display->cdclk.obj);
if (IS_ERR(cdclk_state))
return ERR_CAST(cdclk_state);
@@ -2492,7 +2492,7 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
if (!cdclk_state)
return -ENOMEM;
- intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->display->cdclk.obj,
&cdclk_state->base, &intel_cdclk_funcs);
return 0;
@@ -2593,7 +2593,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
- int max_cdclk_freq = dev_priv->max_cdclk_freq;
+ int max_cdclk_freq = dev_priv->display->max_cdclk_freq;
if (DISPLAY_VER(dev_priv) >= 10)
return 2 * max_cdclk_freq;
@@ -2619,19 +2619,19 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
if (IS_JSL_EHL(dev_priv)) {
- if (dev_priv->cdclk.hw.ref == 24000)
- dev_priv->max_cdclk_freq = 552000;
+ if (dev_priv->display->cdclk.hw.ref == 24000)
+ dev_priv->display->max_cdclk_freq = 552000;
else
- dev_priv->max_cdclk_freq = 556800;
+ dev_priv->display->max_cdclk_freq = 556800;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->cdclk.hw.ref == 24000)
- dev_priv->max_cdclk_freq = 648000;
+ if (dev_priv->display->cdclk.hw.ref == 24000)
+ dev_priv->display->max_cdclk_freq = 648000;
else
- dev_priv->max_cdclk_freq = 652800;
+ dev_priv->display->max_cdclk_freq = 652800;
} else if (IS_GEMINILAKE(dev_priv)) {
- dev_priv->max_cdclk_freq = 316800;
+ dev_priv->display->max_cdclk_freq = 316800;
} else if (IS_BROXTON(dev_priv)) {
- dev_priv->max_cdclk_freq = 624000;
+ dev_priv->display->max_cdclk_freq = 624000;
} else if (DISPLAY_VER(dev_priv) == 9) {
u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
@@ -2653,7 +2653,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
else
max_cdclk = 308571;
- dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
+ dev_priv->display->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
} else if (IS_BROADWELL(dev_priv)) {
/*
* FIXME with extra cooling we can allow
@@ -2662,26 +2662,26 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
* available? PCI ID, VTB, something else?
*/
if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
- dev_priv->max_cdclk_freq = 450000;
+ dev_priv->display->max_cdclk_freq = 450000;
else if (IS_BDW_ULX(dev_priv))
- dev_priv->max_cdclk_freq = 450000;
+ dev_priv->display->max_cdclk_freq = 450000;
else if (IS_BDW_ULT(dev_priv))
- dev_priv->max_cdclk_freq = 540000;
+ dev_priv->display->max_cdclk_freq = 540000;
else
- dev_priv->max_cdclk_freq = 675000;
+ dev_priv->display->max_cdclk_freq = 675000;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->max_cdclk_freq = 320000;
+ dev_priv->display->max_cdclk_freq = 320000;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->max_cdclk_freq = 400000;
+ dev_priv->display->max_cdclk_freq = 400000;
} else {
/* otherwise assume cdclk is fixed */
- dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
+ dev_priv->display->max_cdclk_freq = dev_priv->display->cdclk.hw.cdclk;
}
dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
- dev_priv->max_cdclk_freq);
+ dev_priv->display->max_cdclk_freq);
drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
dev_priv->max_dotclk_freq);
@@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
*/
void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
- dev_priv->display->funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
+ dev_priv->display->funcs.get_cdclk(dev_priv, &dev_priv->display->cdclk.hw);
/*
* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
@@ -2705,7 +2705,7 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
*/
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_de_write(dev_priv, GMBUSFREQ_VLV,
- DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
+ DIV_ROUND_UP(dev_priv->display->cdclk.hw.cdclk, 1000));
}
static int dg1_rawclk(struct drm_i915_private *dev_priv)
@@ -2856,7 +2856,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display->funcs.calc_voltage_level = tgl_calc_voltage_level;
- dev_priv->cdclk.table = dg2_cdclk_table;
+ dev_priv->display->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
@@ -2864,42 +2864,42 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
dev_priv->display->funcs.calc_voltage_level = tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- dev_priv->cdclk.table = adlp_a_step_cdclk_table;
+ dev_priv->display->cdclk.table = adlp_a_step_cdclk_table;
else
- dev_priv->cdclk.table = adlp_cdclk_table;
+ dev_priv->display->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display->funcs.calc_voltage_level = tgl_calc_voltage_level;
- dev_priv->cdclk.table = rkl_cdclk_table;
+ dev_priv->display->cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display->funcs.calc_voltage_level = tgl_calc_voltage_level;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display->cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display->funcs.calc_voltage_level = ehl_calc_voltage_level;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display->cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display->funcs.calc_voltage_level = icl_calc_voltage_level;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display->cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display->funcs.set_cdclk = bxt_set_cdclk;
dev_priv->display->funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display->funcs.calc_voltage_level = bxt_calc_voltage_level;
if (IS_GEMINILAKE(dev_priv))
- dev_priv->cdclk.table = glk_cdclk_table;
+ dev_priv->display->cdclk.table = glk_cdclk_table;
else
- dev_priv->cdclk.table = bxt_cdclk_table;
+ dev_priv->display->cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
dev_priv->display->funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display->funcs.set_cdclk = skl_set_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index b34eb00fb327..80e56bcd34f6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -74,9 +74,9 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
#define intel_atomic_get_old_cdclk_state(state) \
- to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display->cdclk.obj))
#define intel_atomic_get_new_cdclk_state(state) \
- to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display->cdclk.obj))
int intel_cdclk_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index aabc1badb517..3cfac2dc2d12 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3658,7 +3658,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct intel_bw_state *bw_state =
to_intel_bw_state(dev_priv->bw_obj.state);
struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+ to_intel_cdclk_state(dev_priv->display->cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(dev_priv->dbuf.obj.state);
struct intel_crtc_state *crtc_state =
@@ -3827,7 +3827,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
* Should measure whether using a lower cdclk w/o IPS
*/
if (IS_BROADWELL(dev_priv) &&
- crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100)
+ crtc_state->pixel_rate > dev_priv->display->max_cdclk_freq * 95 / 100)
return false;
return true;
@@ -4038,7 +4038,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
if (DISPLAY_VER(dev_priv) < 4) {
- clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
+ clock_limit = dev_priv->display->max_cdclk_freq * 9 / 10;
/*
* Enable double wide mode when the dot clock
@@ -11266,11 +11266,11 @@ void intel_modeset_init_hw(struct drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return;
- cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
+ cdclk_state = to_intel_cdclk_state(i915->display->cdclk.obj.state);
intel_update_cdclk(i915);
- intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
- cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
+ intel_dump_cdclk_config(&i915->display->cdclk.hw, "Current CDCLK");
+ cdclk_state->logical = cdclk_state->actual = i915->display->cdclk.hw;
}
static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
@@ -11652,7 +11652,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
intel_hdcp_component_init(i915);
- if (i915->max_cdclk_freq == 0)
+ if (i915->display->max_cdclk_freq == 0)
intel_update_max_cdclk(i915);
/*
@@ -12146,7 +12146,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+ to_intel_cdclk_state(dev_priv->display->cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(dev_priv->dbuf.obj.state);
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b9195e614cd4..02a321a2efdd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1198,7 +1198,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
dev_priv->display->funcs.get_cdclk(dev_priv, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
drm_WARN_ON(&dev_priv->drm,
- intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
+ intel_cdclk_needs_modeset(&dev_priv->display->cdclk.hw,
&cdclk_config));
gen9_assert_dbuf_enabled(dev_priv);
@@ -5482,7 +5482,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_update_cdclk(dev_priv);
- intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
+ intel_dump_cdclk_config(&dev_priv->display->cdclk.hw, "Current CDCLK");
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4f2fd33529ca..4a6a50ca60b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -576,7 +576,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
if (bigjoiner) {
u32 max_bpp_bigjoiner =
- i915->max_cdclk_freq * 48 /
+ i915->display->max_cdclk_freq * 48 /
intel_dp_mode_to_fec_clock(mode_clock);
DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
@@ -1348,7 +1348,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* is greater than the maximum Cdclock and if slice count is even
* then we need to use 2 VDSC instances.
*/
- if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
+ if (adjusted_mode->crtc_clock > dev_priv->display->max_cdclk_freq ||
pipe_config->bigjoiner) {
if (pipe_config->dsc.slice_count < 2) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index f483f479dd0b..60a94bab922a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -86,7 +86,7 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
* divide by 2000 and use that
*/
if (dig_port->aux_ch == AUX_CH_A)
- freq = dev_priv->cdclk.hw.cdclk;
+ freq = dev_priv->display->cdclk.hw.cdclk;
else
freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
return DIV_ROUND_CLOSEST(freq, 2000);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 055992d099c7..11fefa6de27e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1782,7 +1782,7 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+ i915->dpll.ref_clks.nssc = i915->display->cdclk.hw.ref;
}
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -3867,7 +3867,7 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+ i915->dpll.ref_clks.nssc = i915->display->cdclk.hw.ref;
}
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index b1c1a23c36be..b3f47a6308f6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -874,7 +874,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
/* WaFbcExceedCdClockThreshold:hsw,bdw */
if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
- cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
+ cache->crtc.hsw_bdw_pixel_rate >= dev_priv->display->cdclk.hw.cdclk * 95 / 100) {
fbc->no_fbc_reason = "pixel rate is too big";
return false;
}
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index d6f5836396f8..5b8375f1a2b1 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -474,8 +474,8 @@ static int frequency_show(struct seq_file *m, void *unused)
seq_puts(m, "no P-state info available\n");
}
- seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);
- seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq);
+ seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display->cdclk.hw.cdclk);
+ seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display->max_cdclk_freq);
seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
intel_runtime_pm_put(uncore->rpm, wakeref);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 44969f5dde50..81dc7c47671d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -575,8 +575,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_puts(m, "no P-state info available\n");
}
- seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
- seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
+ seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->display->cdclk.hw.cdclk);
+ seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->display->max_cdclk_freq);
seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1a1d24557702..d6d5e4fe49e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -826,8 +826,20 @@ struct i915_selftest_stash {
};
struct drm_i915_display {
+ struct drm_device *drm;
/* Display functions */
struct drm_i915_display_funcs funcs;
+
+ struct {
+ /* The current hardware cdclk configuration */
+ struct intel_cdclk_config hw;
+
+ /* cdclk, divider, and ratio table from bspec */
+ const struct intel_cdclk_vals *table;
+
+ struct intel_global_obj obj;
+ } cdclk;
+ unsigned int max_cdclk_freq;
};
struct drm_i915_private {
@@ -941,23 +953,12 @@ struct drm_i915_private {
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
- unsigned int max_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
- struct {
- /* The current hardware cdclk configuration */
- struct intel_cdclk_config hw;
-
- /* cdclk, divider, and ratio table from bspec */
- const struct intel_cdclk_vals *table;
-
- struct intel_global_obj obj;
- } cdclk;
-
struct {
/* The current hardware dbuf configuration */
u8 enabled_slices;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 03/25] drm/i915: move more pll/clocks into display struct.
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 01/25] drm/i915: move display funcs into a display struct. (v3) Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 02/25] drm/i915/display: move cdclk info into display Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 04/25] drm/i915/display: move gmbus " Dave Airlie
` (24 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 24 ++++++++++----------
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++------
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 8 +++----
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
drivers/gpu/drm/i915/display/intel_tv.c | 2 +-
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 4 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 13 ++++++-----
17 files changed, 45 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index e9152c8fb63a..89df878a7953 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -434,7 +434,7 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
- int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
+ int freq_320 = (dev_priv->display->hpll_freq << 1) % 320000 != 0 ?
333333 : 320000;
/*
@@ -467,7 +467,7 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
* hardware has shown that we just need to write the desired
* CCK divider into the Punit register.
*/
- return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
+ return DIV_ROUND_CLOSEST(dev_priv->display->hpll_freq << 1, cdclk) - 1;
}
}
@@ -506,7 +506,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
else
default_credits = PFI_CREDIT(8);
- if (dev_priv->display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
+ if (dev_priv->display->cdclk.hw.cdclk >= dev_priv->display->czclk_freq) {
/* CHV suggested value is 31 or 63 */
if (IS_CHERRYVIEW(dev_priv))
credits = PFI_CREDIT_63;
@@ -581,7 +581,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
if (cdclk == 400000) {
u32 divider;
- divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
+ divider = DIV_ROUND_CLOSEST(dev_priv->display->hpll_freq << 1,
cdclk) - 1;
/* adjust cdclk divider */
@@ -942,9 +942,9 @@ static int skl_cdclk_decimal(int cdclk)
static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
int vco)
{
- bool changed = dev_priv->skl_preferred_vco_freq != vco;
+ bool changed = dev_priv->display->skl_preferred_vco_freq != vco;
- dev_priv->skl_preferred_vco_freq = vco;
+ dev_priv->display->skl_preferred_vco_freq = vco;
if (changed)
intel_update_max_cdclk(dev_priv);
@@ -1151,7 +1151,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
* Use the current vco as our initial
* guess as to what the preferred vco is.
*/
- if (dev_priv->skl_preferred_vco_freq == 0)
+ if (dev_priv->display->skl_preferred_vco_freq == 0)
skl_set_preferred_cdclk_vco(dev_priv,
dev_priv->display->cdclk.hw.vco);
return;
@@ -1159,7 +1159,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
cdclk_config = dev_priv->display->cdclk.hw;
- cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
+ cdclk_config.vco = dev_priv->display->skl_preferred_vco_freq;
if (cdclk_config.vco == 0)
cdclk_config.vco = 8100000;
cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
@@ -2331,7 +2331,7 @@ static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
vco = cdclk_state->logical.vco;
if (!vco)
- vco = dev_priv->skl_preferred_vco_freq;
+ vco = dev_priv->display->skl_preferred_vco_freq;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
if (!crtc_state->hw.enable)
@@ -2636,7 +2636,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
- vco = dev_priv->skl_preferred_vco_freq;
+ vco = dev_priv->display->skl_preferred_vco_freq;
drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
/*
@@ -2678,13 +2678,13 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
dev_priv->display->max_cdclk_freq = dev_priv->display->cdclk.hw.cdclk;
}
- dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
+ dev_priv->display->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
dev_priv->display->max_cdclk_freq);
drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
- dev_priv->max_dotclk_freq);
+ dev_priv->display->max_dotclk_freq);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 408f82b0dc7d..97a274f0a38d 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -342,7 +342,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
{
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- int max_dotclk = dev_priv->max_dotclk_freq;
+ int max_dotclk = dev_priv->display->max_dotclk_freq;
int max_clock;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3cfac2dc2d12..60ef938aed0e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -160,10 +160,10 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
vlv_cck_get(dev_priv);
- if (dev_priv->hpll_freq == 0)
- dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
+ if (dev_priv->display->hpll_freq == 0)
+ dev_priv->display->hpll_freq = vlv_get_hpll_vco(dev_priv);
- hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
+ hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->display->hpll_freq);
vlv_cck_put(dev_priv);
@@ -175,11 +175,11 @@ static void intel_update_czclk(struct drm_i915_private *dev_priv)
if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
return;
- dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
+ dev_priv->display->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
CCK_CZ_CLOCK_CONTROL);
drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
- dev_priv->czclk_freq);
+ dev_priv->display->czclk_freq);
}
/* WA Display #0827: Gen9:all */
@@ -4006,7 +4006,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_display_mode *pipe_mode = &pipe_config->hw.pipe_mode;
- int clock_limit = dev_priv->max_dotclk_freq;
+ int clock_limit = dev_priv->display->max_dotclk_freq;
drm_mode_copy(pipe_mode, &pipe_config->hw.adjusted_mode);
@@ -4046,7 +4046,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
*/
if (intel_crtc_supports_double_wide(crtc) &&
pipe_mode->crtc_clock > clock_limit) {
- clock_limit = dev_priv->max_dotclk_freq;
+ clock_limit = dev_priv->display->max_dotclk_freq;
pipe_config->double_wide = true;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4a6a50ca60b6..0737fe4e435f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -785,7 +785,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
struct drm_i915_private *dev_priv = to_i915(connector->dev);
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
- int max_dotclk = dev_priv->max_dotclk_freq;
+ int max_dotclk = dev_priv->display->max_dotclk_freq;
u16 dsc_max_output_bpp = 0;
u8 dsc_slice_count = 0;
enum drm_mode_status status;
@@ -1427,7 +1427,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
limits.max_lane_count, limits.max_rate,
limits.max_bpp, adjusted_mode->crtc_clock);
- if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
+ if ((adjusted_mode->crtc_clock > i915->display->max_dotclk_freq ||
adjusted_mode->crtc_hdisplay > 5120) &&
intel_dp_can_bigjoiner(intel_dp))
pipe_config->bigjoiner = true;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index d104441344c0..e650bed14527 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -683,7 +683,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
struct drm_dp_mst_port *port = intel_connector->port;
const int min_bpp = 18;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display->max_dotclk_freq;
int max_rate, mode_rate, max_lanes, max_link_clock;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index f453ceb8d149..cf58e087cfc0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -59,7 +59,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_connector *intel_connector = to_intel_connector(connector);
const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display->max_dotclk_freq;
drm_dbg_kms(&dev_priv->drm, "\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 86c903e9df60..6a9960b1647a 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -226,7 +226,7 @@ intel_dvo_mode_valid(struct drm_connector *connector,
struct intel_dvo *intel_dvo = intel_attached_dvo(to_intel_connector(connector));
const struct drm_display_mode *fixed_mode =
to_intel_connector(connector)->panel.fixed_mode;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display->max_dotclk_freq;
int target_clock = mode->clock;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 82b6c754c51b..fc92c7f5d4c9 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -104,14 +104,14 @@ void intel_fdi_pll_freq_update(struct drm_i915_private *i915)
u32 fdi_pll_clk =
intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
- i915->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
+ i915->display->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
} else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) {
- i915->fdi_pll_freq = 270000;
+ i915->display->fdi_pll_freq = 270000;
} else {
return;
}
- drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->fdi_pll_freq);
+ drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display->fdi_pll_freq);
}
int intel_fdi_link_freq(struct drm_i915_private *i915,
@@ -120,7 +120,7 @@ int intel_fdi_link_freq(struct drm_i915_private *i915,
if (HAS_DDI(i915))
return pipe_config->port_clock; /* SPLL */
else
- return i915->fdi_pll_freq;
+ return i915->display->fdi_pll_freq;
}
int ilk_fdi_compute_config(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 1bc33766ed39..e52e67d7d170 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1950,7 +1950,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
struct drm_i915_private *dev_priv = to_i915(dev);
enum drm_mode_status status;
int clock = mode->clock;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display->max_dotclk_freq;
bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
bool ycbcr_420_only;
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index e9fb402708a7..a4714b8e11f0 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -388,7 +388,7 @@ intel_lvds_mode_valid(struct drm_connector *connector,
{
struct intel_connector *intel_connector = to_intel_connector(connector);
struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
- int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_pixclk = to_i915(connector->dev)->display->max_dotclk_freq;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 6cb27599ea03..f9a6e8f6c15a 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1866,7 +1866,7 @@ intel_sdvo_mode_valid(struct drm_connector *connector,
struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
struct intel_sdvo_connector *intel_sdvo_connector =
to_intel_sdvo_connector(connector);
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display->max_dotclk_freq;
bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, connector->state);
int clock = mode->clock;
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index d02f09f7e750..080b3603b7e1 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -956,7 +956,7 @@ intel_tv_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+ int max_dotclk = to_i915(connector->dev)->display->max_dotclk_freq;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 5b8375f1a2b1..ae916832101a 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -476,7 +476,7 @@ static int frequency_show(struct seq_file *m, void *unused)
seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display->cdclk.hw.cdclk);
seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display->max_cdclk_freq);
- seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
+ seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->display->max_dotclk_freq);
intel_runtime_pm_put(uncore->rpm, wakeref);
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 799d382eea79..9474867cc405 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -757,7 +757,7 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
mul = 1000000;
- div = i915->czclk_freq;
+ div = i915->display->czclk_freq;
overflow_hw = BIT_ULL(40);
time_hw = vlv_residency_raw(uncore, reg);
} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index d812b27835f8..bd9f1bc56255 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1514,7 +1514,7 @@ static void vlv_init_gpll_ref_freq(struct intel_rps *rps)
rps->gpll_ref_freq =
vlv_get_cck_clock(i915, "GPLL ref",
CCK_GPLL_CLOCK_CONTROL,
- i915->czclk_freq);
+ i915->display->czclk_freq);
drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n",
rps->gpll_ref_freq);
@@ -1646,7 +1646,7 @@ static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir)
time = ktime_us_delta(now.ktime, prev->ktime);
- time *= rps_to_i915(rps)->czclk_freq;
+ time *= rps_to_i915(rps)->display->czclk_freq;
/* Workload can be split between render + media,
* e.g. SwapBuffers being blitted in X after being rendered in
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 81dc7c47671d..da83b8a52b10 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -577,7 +577,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->display->cdclk.hw.cdclk);
seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->display->max_cdclk_freq);
- seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
+ seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->display->max_dotclk_freq);
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d6d5e4fe49e1..343cc351d57f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -840,6 +840,13 @@ struct drm_i915_display {
struct intel_global_obj obj;
} cdclk;
unsigned int max_cdclk_freq;
+
+ unsigned int skl_preferred_vco_freq;
+
+ unsigned int max_dotclk_freq;
+ unsigned int hpll_freq;
+ unsigned int fdi_pll_freq;
+ unsigned int czclk_freq;
};
struct drm_i915_private {
@@ -952,12 +959,6 @@ struct drm_i915_private {
struct mutex pps_mutex;
unsigned int fsb_freq, mem_freq, is_ddr3;
- unsigned int skl_preferred_vco_freq;
-
- unsigned int max_dotclk_freq;
- unsigned int hpll_freq;
- unsigned int fdi_pll_freq;
- unsigned int czclk_freq;
struct {
/* The current hardware dbuf configuration */
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 04/25] drm/i915/display: move gmbus into display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (2 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 03/25] drm/i915: move more pll/clocks into display struct Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 05/25] drm/i915/display: move intel_dmc " Dave Airlie
` (23 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +--
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 42 ++++++++++-----------
drivers/gpu/drm/i915/i915_drv.h | 27 +++++++------
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 14 +++----
6 files changed, 47 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 89df878a7953..cd6fcfb660c6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1948,12 +1948,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
* functions use cdclk. Not all platforms/ports do,
* but we'll lock them all for simplicity.
*/
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display->gmbus_mutex);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
- &dev_priv->gmbus_mutex);
+ &dev_priv->display->gmbus_mutex);
}
dev_priv->display->funcs.set_cdclk(dev_priv, cdclk_config, pipe);
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
mutex_unlock(&intel_dp->aux.hw_mutex);
}
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display->gmbus_mutex);
for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 60a94bab922a..0fc1ad7c4506 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -42,7 +42,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
bool done;
#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->gmbus_wait_queue, C,
+ done = wait_event_timeout(i915->display->gmbus_wait_queue, C,
msecs_to_jiffies_timeout(timeout_ms));
/* just trace the final value */
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index ceb1bf8a8c3c..5cc1a66b9708 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -347,7 +347,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
if (!HAS_GMBUS_IRQ(dev_priv))
irq_en = 0;
- add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ add_wait_queue(&dev_priv->display->gmbus_wait_queue, &wait);
intel_de_write_fw(dev_priv, GMBUS4, irq_en);
status |= GMBUS_SATOER;
@@ -358,7 +358,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
50);
intel_de_write_fw(dev_priv, GMBUS4, 0);
- remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ remove_wait_queue(&dev_priv->display->gmbus_wait_queue, &wait);
if (gmbus2 & GMBUS_SATOER)
return -ENXIO;
@@ -378,7 +378,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
if (HAS_GMBUS_IRQ(dev_priv))
irq_enable = GMBUS_IDLE_EN;
- add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ add_wait_queue(&dev_priv->display->gmbus_wait_queue, &wait);
intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
ret = intel_wait_for_register_fw(&dev_priv->uncore,
@@ -386,7 +386,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
10);
intel_de_write_fw(dev_priv, GMBUS4, 0);
- remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ remove_wait_queue(&dev_priv->display->gmbus_wait_queue, &wait);
return ret;
}
@@ -773,7 +773,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
int ret;
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display->gmbus_mutex);
/*
* In order to output Aksv to the receiver, use an indexed write to
@@ -782,7 +782,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
*/
ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display->gmbus_mutex);
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
return ret;
@@ -808,7 +808,7 @@ static void gmbus_lock_bus(struct i2c_adapter *adapter,
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display->gmbus_mutex);
}
static int gmbus_trylock_bus(struct i2c_adapter *adapter,
@@ -817,7 +817,7 @@ static int gmbus_trylock_bus(struct i2c_adapter *adapter,
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- return mutex_trylock(&dev_priv->gmbus_mutex);
+ return mutex_trylock(&dev_priv->display->gmbus_mutex);
}
static void gmbus_unlock_bus(struct i2c_adapter *adapter,
@@ -826,7 +826,7 @@ static void gmbus_unlock_bus(struct i2c_adapter *adapter,
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display->gmbus_mutex);
}
static const struct i2c_lock_operations gmbus_lock_ops = {
@@ -847,22 +847,22 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
int ret;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
+ dev_priv->display->gpio_mmio_base = VLV_DISPLAY_BASE;
else if (!HAS_GMCH(dev_priv))
/*
* Broxton uses the same PCH offsets for South Display Engine,
* even though it doesn't have a PCH.
*/
- dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
+ dev_priv->display->gpio_mmio_base = PCH_DISPLAY_BASE;
- mutex_init(&dev_priv->gmbus_mutex);
- init_waitqueue_head(&dev_priv->gmbus_wait_queue);
+ mutex_init(&dev_priv->display->gmbus_mutex);
+ init_waitqueue_head(&dev_priv->display->gmbus_wait_queue);
- for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
+ for (pin = 0; pin < ARRAY_SIZE(dev_priv->display->gmbus); pin++) {
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
continue;
- bus = &dev_priv->gmbus[pin];
+ bus = &dev_priv->display->gmbus[pin];
bus->adapter.owner = THIS_MODULE;
bus->adapter.class = I2C_CLASS_DDC;
@@ -906,7 +906,7 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
continue;
- bus = &dev_priv->gmbus[pin];
+ bus = &dev_priv->display->gmbus[pin];
i2c_del_adapter(&bus->adapter);
}
return ret;
@@ -919,7 +919,7 @@ struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
!intel_gmbus_is_valid_pin(dev_priv, pin)))
return NULL;
- return &dev_priv->gmbus[pin].adapter;
+ return &dev_priv->display->gmbus[pin].adapter;
}
void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
@@ -934,7 +934,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display->gmbus_mutex);
bus->force_bit += force_bit ? 1 : -1;
drm_dbg_kms(&dev_priv->drm,
@@ -942,7 +942,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
force_bit ? "en" : "dis", adapter->name,
bus->force_bit);
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display->gmbus_mutex);
}
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
@@ -957,11 +957,11 @@ void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
struct intel_gmbus *bus;
unsigned int pin;
- for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
+ for (pin = 0; pin < ARRAY_SIZE(dev_priv->display->gmbus); pin++) {
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
continue;
- bus = &dev_priv->gmbus[pin];
+ bus = &dev_priv->display->gmbus[pin];
i2c_del_adapter(&bus->adapter);
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 343cc351d57f..5ca320d1d718 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -847,6 +847,19 @@ struct drm_i915_display {
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
+
+ /**
+ * Base address of where the gmbus and gpio blocks are located (either
+ * on PCH or on SoC for platforms without PCH).
+ */
+ u32 gpio_mmio_base;
+
+ struct intel_gmbus gmbus[GMBUS_NUM_PINS];
+
+ /** gmbus_mutex protects against concurrent usage of the single hw gmbus
+ * controller on different i2c buses. */
+ struct mutex gmbus_mutex;
+ wait_queue_head_t gmbus_wait_queue;
};
struct drm_i915_private {
@@ -900,25 +913,11 @@ struct drm_i915_private {
struct intel_dmc dmc;
- struct intel_gmbus gmbus[GMBUS_NUM_PINS];
-
- /** gmbus_mutex protects against concurrent usage of the single hw gmbus
- * controller on different i2c buses. */
- struct mutex gmbus_mutex;
-
- /**
- * Base address of where the gmbus and gpio blocks are located (either
- * on PCH or on SoC for platforms without PCH).
- */
- u32 gpio_mmio_base;
-
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
u32 pps_mmio_base;
- wait_queue_head_t gmbus_wait_queue;
-
struct pci_dev *bridge_dev;
struct rb_root uabi_engines;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0b35ab7b421d..dcc404ca919f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1303,12 +1303,12 @@ static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
{
- wake_up_all(&dev_priv->gmbus_wait_queue);
+ wake_up_all(&dev_priv->display->gmbus_wait_queue);
}
static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
{
- wake_up_all(&dev_priv->gmbus_wait_queue);
+ wake_up_all(&dev_priv->display->gmbus_wait_queue);
}
#if defined(CONFIG_DEBUG_FS)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd63760207b0..a080fe654f8c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3403,7 +3403,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/*
* GPIO regs
*/
-#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
+#define GPIO(gpio) _MMIO(dev_priv->display->gpio_mmio_base + 0x5010 + \
4 * (gpio))
# define GPIO_CLOCK_DIR_MASK (1 << 0)
@@ -3421,7 +3421,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
# define GPIO_DATA_VAL_IN (1 << 12)
# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
-#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
+#define GMBUS0 _MMIO(dev_priv->display->gpio_mmio_base + 0x5100) /* clock/port select */
#define GMBUS_AKSV_SELECT (1 << 11)
#define GMBUS_RATE_100KHZ (0 << 8)
#define GMBUS_RATE_50KHZ (1 << 8)
@@ -3430,7 +3430,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
-#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
+#define GMBUS1 _MMIO(dev_priv->display->gpio_mmio_base + 0x5104) /* command/status */
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
#define GMBUS_ENT (1 << 29) /* enable timeout */
@@ -3445,7 +3445,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GMBUS_SLAVE_ADDR_SHIFT 1
#define GMBUS_SLAVE_READ (1 << 0)
#define GMBUS_SLAVE_WRITE (0 << 0)
-#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
+#define GMBUS2 _MMIO(dev_priv->display->gpio_mmio_base + 0x5108) /* status */
#define GMBUS_INUSE (1 << 15)
#define GMBUS_HW_WAIT_PHASE (1 << 14)
#define GMBUS_STALL_TIMEOUT (1 << 13)
@@ -3453,14 +3453,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GMBUS_HW_RDY (1 << 11)
#define GMBUS_SATOER (1 << 10)
#define GMBUS_ACTIVE (1 << 9)
-#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
-#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
+#define GMBUS3 _MMIO(dev_priv->display->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
+#define GMBUS4 _MMIO(dev_priv->display->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
#define GMBUS_NAK_EN (1 << 3)
#define GMBUS_IDLE_EN (1 << 2)
#define GMBUS_HW_WAIT_EN (1 << 1)
#define GMBUS_HW_RDY_EN (1 << 0)
-#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
+#define GMBUS5 _MMIO(dev_priv->display->gpio_mmio_base + 0x5120) /* byte index */
#define GMBUS_2BYTE_INDEX_EN (1 << 31)
/*
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 05/25] drm/i915/display: move intel_dmc into display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (3 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 04/25] drm/i915/display: move gmbus " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 06/25] drm/i915/display: move mipi_mmio_base to " Dave Airlie
` (22 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/i915/display/intel_display_debugfs.c | 2 +-
.../drm/i915/display/intel_display_power.c | 38 +++++++--------
drivers/gpu/drm/i915/display/intel_dmc.c | 46 +++++++++----------
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
6 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index ca819f9e353d..be0601606aa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -539,7 +539,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
if (!HAS_DMC(dev_priv))
return -ENODEV;
- dmc = &dev_priv->dmc;
+ dmc = &dev_priv->display->dmc;
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 02a321a2efdd..d1db420a8819 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -832,8 +832,8 @@ static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm,
"Resetting DC state tracking from %02x to %02x\n",
- dev_priv->dmc.dc_state, val);
- dev_priv->dmc.dc_state = val;
+ dev_priv->display->dmc.dc_state, val);
+ dev_priv->display->dmc.dc_state = val;
}
/**
@@ -868,8 +868,8 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
return;
if (drm_WARN_ON_ONCE(&dev_priv->drm,
- state & ~dev_priv->dmc.allowed_dc_mask))
- state &= dev_priv->dmc.allowed_dc_mask;
+ state & ~dev_priv->display->dmc.allowed_dc_mask))
+ state &= dev_priv->display->dmc.allowed_dc_mask;
val = intel_de_read(dev_priv, DC_STATE_EN);
mask = gen9_dc_mask(dev_priv);
@@ -877,16 +877,16 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
val & mask, state);
/* Check if DMC is ignoring our DC state requests */
- if ((val & mask) != dev_priv->dmc.dc_state)
+ if ((val & mask) != dev_priv->display->dmc.dc_state)
drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
- dev_priv->dmc.dc_state, val & mask);
+ dev_priv->display->dmc.dc_state, val & mask);
val &= ~mask;
val |= state;
gen9_write_dc_state(dev_priv, val);
- dev_priv->dmc.dc_state = val & mask;
+ dev_priv->display->dmc.dc_state = val & mask;
}
static u32
@@ -905,7 +905,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
if (target_dc_state != states[i])
continue;
- if (dev_priv->dmc.allowed_dc_mask & target_dc_state)
+ if (dev_priv->display->dmc.allowed_dc_mask & target_dc_state)
break;
target_dc_state = states[i + 1];
@@ -965,7 +965,7 @@ static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
!intel_de_read(dev_priv,
- DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+ DMC_PROGRAM(dev_priv->display->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
"DMC program storage start is NULL\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
@@ -1020,7 +1020,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
state = sanitize_target_dc_state(dev_priv, state);
- if (state == dev_priv->dmc.target_dc_state)
+ if (state == dev_priv->display->dmc.target_dc_state)
goto unlock;
dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv,
@@ -1032,7 +1032,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
if (!dc_off_enabled)
power_well->desc->ops->enable(dev_priv, power_well);
- dev_priv->dmc.target_dc_state = state;
+ dev_priv->display->dmc.target_dc_state = state;
if (!dc_off_enabled)
power_well->desc->ops->disable(dev_priv, power_well);
@@ -1185,7 +1185,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_config cdclk_config = {};
- if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
+ if (dev_priv->display->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
tgl_disable_dc3co(dev_priv);
return;
}
@@ -1227,7 +1227,7 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
if (!intel_dmc_has_payload(dev_priv))
return;
- switch (dev_priv->dmc.target_dc_state) {
+ switch (dev_priv->display->dmc.target_dc_state) {
case DC_STATE_EN_DC3CO:
tgl_enable_dc3co(dev_priv);
break;
@@ -5108,10 +5108,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
dev_priv->params.disable_power_well);
- dev_priv->dmc.allowed_dc_mask =
+ dev_priv->display->dmc.allowed_dc_mask =
get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
- dev_priv->dmc.target_dc_state =
+ dev_priv->display->dmc.target_dc_state =
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
@@ -6181,7 +6181,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
* resources as required and also enable deeper system power states
* that would be blocked if the firmware was inactive.
*/
- if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
+ if (!(i915->display->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
intel_dmc_has_payload(i915)) {
intel_display_power_flush_work(i915);
@@ -6372,10 +6372,10 @@ void intel_display_power_resume(struct drm_i915_private *i915)
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
if (intel_dmc_has_payload(i915)) {
- if (i915->dmc.allowed_dc_mask &
+ if (i915->display->dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
- else if (i915->dmc.allowed_dc_mask &
+ else if (i915->display->dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC5)
gen9_enable_dc5(i915);
}
@@ -6383,7 +6383,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
bxt_disable_dc9(i915);
bxt_display_core_init(i915, true);
if (intel_dmc_has_payload(i915) &&
- (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+ (i915->display->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(i915);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_disable_pc8(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 3c3c6cb5c0df..6c028dc6bfeb 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
+ return i915->display->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info *
@@ -281,7 +281,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- struct intel_dmc *dmc = &dev_priv->dmc;
+ struct intel_dmc *dmc = &dev_priv->display->dmc;
u32 id, i;
if (!HAS_DMC(dev_priv)) {
@@ -290,7 +290,7 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
return;
}
- if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
+ if (!dev_priv->display->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
@@ -317,7 +317,7 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
}
}
- dev_priv->dmc.dc_state = 0;
+ dev_priv->display->dmc.dc_state = 0;
gen9_set_dc_state_debugmask(dev_priv);
}
@@ -351,7 +351,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
{
unsigned int i, id;
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), _display.dmc);
for (i = 0; i < num_entries; i++) {
id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
@@ -379,7 +379,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size, u8 dmc_id)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), _display.dmc);
struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
@@ -484,7 +484,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
const struct stepping_info *si,
size_t rem_size)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), _display.dmc);
u32 package_size = sizeof(struct intel_package_header);
u32 num_entries, max_entries;
const struct intel_fw_info *fw_info;
@@ -538,7 +538,7 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
struct intel_css_header *css_header,
size_t rem_size)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), _display.dmc);
if (rem_size < sizeof(struct intel_css_header)) {
drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
@@ -575,7 +575,7 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
struct intel_css_header *css_header;
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
- struct intel_dmc *dmc = &dev_priv->dmc;
+ struct intel_dmc *dmc = &dev_priv->display->dmc;
struct stepping_info display_info = { '*', '*'};
const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info);
u32 readcount = 0;
@@ -602,7 +602,7 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
readcount += r;
for (id = 0; id < DMC_FW_MAX; id++) {
- if (!dev_priv->dmc.dmc_info[id].present)
+ if (!dev_priv->display->dmc.dmc_info[id].present)
continue;
offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
@@ -618,15 +618,15 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
{
- drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
- dev_priv->dmc.wakeref =
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display->dmc.wakeref);
+ dev_priv->display->dmc.wakeref =
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
}
static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv)
{
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&dev_priv->dmc.wakeref);
+ fetch_and_zero(&dev_priv->display->dmc.wakeref);
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
}
@@ -637,10 +637,10 @@ static void dmc_load_work_fn(struct work_struct *work)
struct intel_dmc *dmc;
const struct firmware *fw = NULL;
- dev_priv = container_of(work, typeof(*dev_priv), dmc.work);
- dmc = &dev_priv->dmc;
+ dev_priv = container_of(work, typeof(*dev_priv), _display.dmc.work);
+ dmc = &dev_priv->display->dmc;
- request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
+ request_firmware(&fw, dev_priv->display->dmc.fw_path, dev_priv->drm.dev);
parse_dmc_fw(dev_priv, fw);
if (intel_dmc_has_payload(dev_priv)) {
@@ -649,7 +649,7 @@ static void dmc_load_work_fn(struct work_struct *work)
drm_info(&dev_priv->drm,
"Finished loading DMC firmware %s (v%u.%u)\n",
- dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
+ dev_priv->display->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
DMC_VERSION_MINOR(dmc->version));
} else {
drm_notice(&dev_priv->drm,
@@ -672,9 +672,9 @@ static void dmc_load_work_fn(struct work_struct *work)
*/
void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
{
- struct intel_dmc *dmc = &dev_priv->dmc;
+ struct intel_dmc *dmc = &dev_priv->display->dmc;
- INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn);
+ INIT_WORK(&dev_priv->display->dmc.work, dmc_load_work_fn);
if (!HAS_DMC(dev_priv))
return;
@@ -753,7 +753,7 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
}
drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
- schedule_work(&dev_priv->dmc.work);
+ schedule_work(&dev_priv->display->dmc.work);
}
/**
@@ -769,7 +769,7 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
if (!HAS_DMC(dev_priv))
return;
- flush_work(&dev_priv->dmc.work);
+ flush_work(&dev_priv->display->dmc.work);
/* Drop the reference held in case DMC isn't loaded. */
if (!intel_dmc_has_payload(dev_priv))
@@ -809,7 +809,7 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
return;
intel_dmc_ucode_suspend(dev_priv);
- drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display->dmc.wakeref);
- kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload);
+ kfree(dev_priv->display->dmc.dmc_info[DMC_FW_MAIN].payload);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3f6fb7d67f84..e07b7ee169bd 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -692,7 +692,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
if (crtc_state->enable_psr2_sel_fetch)
return;
- if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
+ if (!(dev_priv->display->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
return;
if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5ca320d1d718..8fc70516737c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -860,6 +860,8 @@ struct drm_i915_display {
* controller on different i2c buses. */
struct mutex gmbus_mutex;
wait_queue_head_t gmbus_wait_queue;
+
+ struct intel_dmc dmc;
};
struct drm_i915_private {
@@ -911,8 +913,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- struct intel_dmc dmc;
-
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9cf6ac575de1..f43aceaf287f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -798,7 +798,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
if (HAS_DMC(m->i915)) {
- struct intel_dmc *dmc = &m->i915->dmc;
+ struct intel_dmc *dmc = &m->i915->display->dmc;
err_printf(m, "DMC loaded: %s\n",
yesno(intel_dmc_has_payload(m->i915) != 0));
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 06/25] drm/i915/display: move mipi_mmio_base to display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (4 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 05/25] drm/i915/display: move intel_dmc " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 07/25] drm/i915/display: move pps_mmio_base " Dave Airlie
` (21 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_reg.h | 188 ++++++++++++-------------
3 files changed, 99 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index b0a2b6b96799..91da69d2f6df 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1843,9 +1843,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
return;
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
+ dev_priv->display->mipi_mmio_base = BXT_MIPI_BASE;
else
- dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
+ dev_priv->display->mipi_mmio_base = VLV_MIPI_BASE;
intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
if (!intel_dsi)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8fc70516737c..68494810ab64 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -854,6 +854,9 @@ struct drm_i915_display {
*/
u32 gpio_mmio_base;
+ /* MMIO base address for MIPI regs */
+ u32 mipi_mmio_base;
+
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
/** gmbus_mutex protects against concurrent usage of the single hw gmbus
@@ -913,9 +916,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- /* MMIO base address for MIPI regs */
- u32 mipi_mmio_base;
-
u32 pps_mmio_base;
struct pci_dev *bridge_dev;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a080fe654f8c..cc109fb81b8e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11731,8 +11731,8 @@ enum skl_power_gate {
/* MIPI DSI Controller and D-PHY registers */
-#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
-#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
+#define _MIPIA_DEVICE_READY (dev_priv->display->mipi_mmio_base + 0xb000)
+#define _MIPIC_DEVICE_READY (dev_priv->display->mipi_mmio_base + 0xb800)
#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
#define ULPS_STATE_MASK (3 << 1)
@@ -11741,11 +11741,11 @@ enum skl_power_gate {
#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
#define DEVICE_READY (1 << 0)
-#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
-#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
+#define _MIPIA_INTR_STAT (dev_priv->display->mipi_mmio_base + 0xb004)
+#define _MIPIC_INTR_STAT (dev_priv->display->mipi_mmio_base + 0xb804)
#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
-#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
-#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
+#define _MIPIA_INTR_EN (dev_priv->display->mipi_mmio_base + 0xb008)
+#define _MIPIC_INTR_EN (dev_priv->display->mipi_mmio_base + 0xb808)
#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
#define TEARING_EFFECT (1 << 31)
#define SPL_PKT_SENT_INTERRUPT (1 << 30)
@@ -11780,8 +11780,8 @@ enum skl_power_gate {
#define RXSOT_SYNC_ERROR (1 << 1)
#define RXSOT_ERROR (1 << 0)
-#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
-#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
+#define _MIPIA_DSI_FUNC_PRG (dev_priv->display->mipi_mmio_base + 0xb00c)
+#define _MIPIC_DSI_FUNC_PRG (dev_priv->display->mipi_mmio_base + 0xb80c)
#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
#define CMD_MODE_NOT_SUPPORTED (0 << 13)
@@ -11803,78 +11803,78 @@ enum skl_power_gate {
#define DATA_LANES_PRG_REG_SHIFT 0
#define DATA_LANES_PRG_REG_MASK (7 << 0)
-#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
-#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
+#define _MIPIA_HS_TX_TIMEOUT (dev_priv->display->mipi_mmio_base + 0xb010)
+#define _MIPIC_HS_TX_TIMEOUT (dev_priv->display->mipi_mmio_base + 0xb810)
#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
-#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
-#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
+#define _MIPIA_LP_RX_TIMEOUT (dev_priv->display->mipi_mmio_base + 0xb014)
+#define _MIPIC_LP_RX_TIMEOUT (dev_priv->display->mipi_mmio_base + 0xb814)
#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
-#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
-#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
+#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->display->mipi_mmio_base + 0xb018)
+#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->display->mipi_mmio_base + 0xb818)
#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
#define TURN_AROUND_TIMEOUT_MASK 0x3f
-#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
-#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
+#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->display->mipi_mmio_base + 0xb01c)
+#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->display->mipi_mmio_base + 0xb81c)
#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
#define DEVICE_RESET_TIMER_MASK 0xffff
-#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
-#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
+#define _MIPIA_DPI_RESOLUTION (dev_priv->display->mipi_mmio_base + 0xb020)
+#define _MIPIC_DPI_RESOLUTION (dev_priv->display->mipi_mmio_base + 0xb820)
#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
#define VERTICAL_ADDRESS_SHIFT 16
#define VERTICAL_ADDRESS_MASK (0xffff << 16)
#define HORIZONTAL_ADDRESS_SHIFT 0
#define HORIZONTAL_ADDRESS_MASK 0xffff
-#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
-#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
+#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->display->mipi_mmio_base + 0xb024)
+#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->display->mipi_mmio_base + 0xb824)
#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
#define DBI_FIFO_EMPTY_HALF (0 << 0)
#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
/* regs below are bits 15:0 */
-#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
-#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
+#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->display->mipi_mmio_base + 0xb028)
+#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->display->mipi_mmio_base + 0xb828)
#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
-#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
-#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
+#define _MIPIA_HBP_COUNT (dev_priv->display->mipi_mmio_base + 0xb02c)
+#define _MIPIC_HBP_COUNT (dev_priv->display->mipi_mmio_base + 0xb82c)
#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
-#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
-#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
+#define _MIPIA_HFP_COUNT (dev_priv->display->mipi_mmio_base + 0xb030)
+#define _MIPIC_HFP_COUNT (dev_priv->display->mipi_mmio_base + 0xb830)
#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
-#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
-#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
+#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->display->mipi_mmio_base + 0xb034)
+#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->display->mipi_mmio_base + 0xb834)
#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
-#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
-#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
+#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->display->mipi_mmio_base + 0xb038)
+#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->display->mipi_mmio_base + 0xb838)
#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
-#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
-#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
+#define _MIPIA_VBP_COUNT (dev_priv->display->mipi_mmio_base + 0xb03c)
+#define _MIPIC_VBP_COUNT (dev_priv->display->mipi_mmio_base + 0xb83c)
#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
-#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
-#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
+#define _MIPIA_VFP_COUNT (dev_priv->display->mipi_mmio_base + 0xb040)
+#define _MIPIC_VFP_COUNT (dev_priv->display->mipi_mmio_base + 0xb840)
#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
-#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
-#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
+#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->display->mipi_mmio_base + 0xb044)
+#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->display->mipi_mmio_base + 0xb844)
#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
/* regs above are bits 15:0 */
-#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
-#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
+#define _MIPIA_DPI_CONTROL (dev_priv->display->mipi_mmio_base + 0xb048)
+#define _MIPIC_DPI_CONTROL (dev_priv->display->mipi_mmio_base + 0xb848)
#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
#define DPI_LP_MODE (1 << 6)
#define BACKLIGHT_OFF (1 << 5)
@@ -11884,27 +11884,27 @@ enum skl_power_gate {
#define TURN_ON (1 << 1)
#define SHUTDOWN (1 << 0)
-#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
-#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
+#define _MIPIA_DPI_DATA (dev_priv->display->mipi_mmio_base + 0xb04c)
+#define _MIPIC_DPI_DATA (dev_priv->display->mipi_mmio_base + 0xb84c)
#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
#define COMMAND_BYTE_SHIFT 0
#define COMMAND_BYTE_MASK (0x3f << 0)
-#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
-#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
+#define _MIPIA_INIT_COUNT (dev_priv->display->mipi_mmio_base + 0xb050)
+#define _MIPIC_INIT_COUNT (dev_priv->display->mipi_mmio_base + 0xb850)
#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
#define MASTER_INIT_TIMER_SHIFT 0
#define MASTER_INIT_TIMER_MASK (0xffff << 0)
-#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
-#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
+#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->display->mipi_mmio_base + 0xb054)
+#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->display->mipi_mmio_base + 0xb854)
#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
#define MAX_RETURN_PKT_SIZE_SHIFT 0
#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
-#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
-#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
+#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->display->mipi_mmio_base + 0xb058)
+#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->display->mipi_mmio_base + 0xb858)
#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
#define DISABLE_VIDEO_BTA (1 << 3)
@@ -11913,8 +11913,8 @@ enum skl_power_gate {
#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
#define VIDEO_MODE_BURST (3 << 0)
-#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
-#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
+#define _MIPIA_EOT_DISABLE (dev_priv->display->mipi_mmio_base + 0xb05c)
+#define _MIPIC_EOT_DISABLE (dev_priv->display->mipi_mmio_base + 0xb85c)
#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
#define BXT_DPHY_DEFEATURE_EN (1 << 8)
@@ -11927,35 +11927,35 @@ enum skl_power_gate {
#define CLOCKSTOP (1 << 1)
#define EOT_DISABLE (1 << 0)
-#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
-#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
+#define _MIPIA_LP_BYTECLK (dev_priv->display->mipi_mmio_base + 0xb060)
+#define _MIPIC_LP_BYTECLK (dev_priv->display->mipi_mmio_base + 0xb860)
#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
#define LP_BYTECLK_SHIFT 0
#define LP_BYTECLK_MASK (0xffff << 0)
-#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
-#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
+#define _MIPIA_TLPX_TIME_COUNT (dev_priv->display->mipi_mmio_base + 0xb0a4)
+#define _MIPIC_TLPX_TIME_COUNT (dev_priv->display->mipi_mmio_base + 0xb8a4)
#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
-#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
-#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
+#define _MIPIA_CLK_LANE_TIMING (dev_priv->display->mipi_mmio_base + 0xb098)
+#define _MIPIC_CLK_LANE_TIMING (dev_priv->display->mipi_mmio_base + 0xb898)
#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
/* bits 31:0 */
-#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
-#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
+#define _MIPIA_LP_GEN_DATA (dev_priv->display->mipi_mmio_base + 0xb064)
+#define _MIPIC_LP_GEN_DATA (dev_priv->display->mipi_mmio_base + 0xb864)
#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
/* bits 31:0 */
-#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
-#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
+#define _MIPIA_HS_GEN_DATA (dev_priv->display->mipi_mmio_base + 0xb068)
+#define _MIPIC_HS_GEN_DATA (dev_priv->display->mipi_mmio_base + 0xb868)
#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
-#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
-#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
+#define _MIPIA_LP_GEN_CTRL (dev_priv->display->mipi_mmio_base + 0xb06c)
+#define _MIPIC_LP_GEN_CTRL (dev_priv->display->mipi_mmio_base + 0xb86c)
#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
-#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
-#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
+#define _MIPIA_HS_GEN_CTRL (dev_priv->display->mipi_mmio_base + 0xb070)
+#define _MIPIC_HS_GEN_CTRL (dev_priv->display->mipi_mmio_base + 0xb870)
#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
#define LONG_PACKET_WORD_COUNT_SHIFT 8
#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
@@ -11965,10 +11965,10 @@ enum skl_power_gate {
#define VIRTUAL_CHANNEL_MASK (3 << 6)
#define DATA_TYPE_SHIFT 0
#define DATA_TYPE_MASK (0x3f << 0)
-/* data type values, see include/video/mipi_display.h */
+/* data type values, see include/video/mipi_display->h */
-#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
-#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
+#define _MIPIA_GEN_FIFO_STAT (dev_priv->display->mipi_mmio_base + 0xb074)
+#define _MIPIC_GEN_FIFO_STAT (dev_priv->display->mipi_mmio_base + 0xb874)
#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
#define DPI_FIFO_EMPTY (1 << 28)
#define DBI_FIFO_EMPTY (1 << 27)
@@ -11985,15 +11985,15 @@ enum skl_power_gate {
#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
#define HS_DATA_FIFO_FULL (1 << 0)
-#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
-#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
+#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->display->mipi_mmio_base + 0xb078)
+#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->display->mipi_mmio_base + 0xb878)
#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
#define DBI_HS_LP_MODE_MASK (1 << 0)
#define DBI_LP_MODE (1 << 0)
#define DBI_HS_MODE (0 << 0)
-#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
-#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
+#define _MIPIA_DPHY_PARAM (dev_priv->display->mipi_mmio_base + 0xb080)
+#define _MIPIC_DPHY_PARAM (dev_priv->display->mipi_mmio_base + 0xb880)
#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
#define EXIT_ZERO_COUNT_SHIFT 24
#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
@@ -12242,34 +12242,34 @@ enum skl_power_gate {
#define TA_TIMEOUT_VALUE(x) ((x) << 0)
/* bits 31:0 */
-#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
-#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
+#define _MIPIA_DBI_BW_CTRL (dev_priv->display->mipi_mmio_base + 0xb084)
+#define _MIPIC_DBI_BW_CTRL (dev_priv->display->mipi_mmio_base + 0xb884)
#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
-#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
-#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
+#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->display->mipi_mmio_base + 0xb088)
+#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->display->mipi_mmio_base + 0xb888)
#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
#define LP_HS_SSW_CNT_SHIFT 16
#define LP_HS_SSW_CNT_MASK (0xffff << 16)
#define HS_LP_PWR_SW_CNT_SHIFT 0
#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
-#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
-#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
+#define _MIPIA_STOP_STATE_STALL (dev_priv->display->mipi_mmio_base + 0xb08c)
+#define _MIPIC_STOP_STATE_STALL (dev_priv->display->mipi_mmio_base + 0xb88c)
#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
#define STOP_STATE_STALL_COUNTER_SHIFT 0
#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
-#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
-#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
+#define _MIPIA_INTR_STAT_REG_1 (dev_priv->display->mipi_mmio_base + 0xb090)
+#define _MIPIC_INTR_STAT_REG_1 (dev_priv->display->mipi_mmio_base + 0xb890)
#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
-#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
-#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
+#define _MIPIA_INTR_EN_REG_1 (dev_priv->display->mipi_mmio_base + 0xb094)
+#define _MIPIC_INTR_EN_REG_1 (dev_priv->display->mipi_mmio_base + 0xb894)
#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
#define RX_CONTENTION_DETECTED (1 << 0)
/* XXX: only pipe A ?!? */
-#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
+#define MIPIA_DBI_TYPEC_CTRL (dev_priv->display->mipi_mmio_base + 0xb100)
#define DBI_TYPEC_ENABLE (1 << 31)
#define DBI_TYPEC_WIP (1 << 30)
#define DBI_TYPEC_OPTION_SHIFT 28
@@ -12283,8 +12283,8 @@ enum skl_power_gate {
/* MIPI adapter registers */
-#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
-#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
+#define _MIPIA_CTRL (dev_priv->display->mipi_mmio_base + 0xb104)
+#define _MIPIC_CTRL (dev_priv->display->mipi_mmio_base + 0xb904)
#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
@@ -12316,21 +12316,21 @@ enum skl_power_gate {
#define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
#define GLK_MIPIIO_ENABLE (1 << 0)
-#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
-#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
+#define _MIPIA_DATA_ADDRESS (dev_priv->display->mipi_mmio_base + 0xb108)
+#define _MIPIC_DATA_ADDRESS (dev_priv->display->mipi_mmio_base + 0xb908)
#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
#define DATA_MEM_ADDRESS_SHIFT 5
#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
#define DATA_VALID (1 << 0)
-#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
-#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
+#define _MIPIA_DATA_LENGTH (dev_priv->display->mipi_mmio_base + 0xb10c)
+#define _MIPIC_DATA_LENGTH (dev_priv->display->mipi_mmio_base + 0xb90c)
#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
#define DATA_LENGTH_SHIFT 0
#define DATA_LENGTH_MASK (0xfffff << 0)
-#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
-#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
+#define _MIPIA_COMMAND_ADDRESS (dev_priv->display->mipi_mmio_base + 0xb110)
+#define _MIPIC_COMMAND_ADDRESS (dev_priv->display->mipi_mmio_base + 0xb910)
#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
#define COMMAND_MEM_ADDRESS_SHIFT 5
#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
@@ -12338,18 +12338,18 @@ enum skl_power_gate {
#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
#define COMMAND_VALID (1 << 0)
-#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
-#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
+#define _MIPIA_COMMAND_LENGTH (dev_priv->display->mipi_mmio_base + 0xb114)
+#define _MIPIC_COMMAND_LENGTH (dev_priv->display->mipi_mmio_base + 0xb914)
#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
-#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
-#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
+#define _MIPIA_READ_DATA_RETURN0 (dev_priv->display->mipi_mmio_base + 0xb118)
+#define _MIPIC_READ_DATA_RETURN0 (dev_priv->display->mipi_mmio_base + 0xb918)
#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
-#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
-#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
+#define _MIPIA_READ_DATA_VALID (dev_priv->display->mipi_mmio_base + 0xb138)
+#define _MIPIC_READ_DATA_VALID (dev_priv->display->mipi_mmio_base + 0xb938)
#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
#define READ_DATA_VALID(n) (1 << (n))
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 07/25] drm/i915/display: move pps_mmio_base to display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (5 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 06/25] drm/i915/display: move mipi_mmio_base to " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 08/25] drm/i915/drrs: just use some local vars to simplify drrs code Dave Airlie
` (20 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_pps.c | 6 +++---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index a36ec4a818ff..0e8d8d0dd51c 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1402,9 +1402,9 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
void intel_pps_setup(struct drm_i915_private *i915)
{
if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- i915->pps_mmio_base = PCH_PPS_BASE;
+ i915->display->pps_mmio_base = PCH_PPS_BASE;
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
- i915->pps_mmio_base = VLV_PPS_BASE;
+ i915->display->pps_mmio_base = VLV_PPS_BASE;
else
- i915->pps_mmio_base = PPS_BASE;
+ i915->display->pps_mmio_base = PPS_BASE;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 68494810ab64..738bb87b1fb8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -857,6 +857,8 @@ struct drm_i915_display {
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
+ u32 pps_mmio_base;
+
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
/** gmbus_mutex protects against concurrent usage of the single hw gmbus
@@ -916,8 +918,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- u32 pps_mmio_base;
-
struct pci_dev *bridge_dev;
struct rb_root uabi_engines;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc109fb81b8e..675fc4fa31b8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5166,7 +5166,7 @@ enum {
#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
#define PCH_PPS_BASE 0xC7200
-#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
+#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display->pps_mmio_base - \
PPS_BASE + (reg) + \
(pps_idx) * 0x100)
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 08/25] drm/i915/drrs: just use some local vars to simplify drrs code
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (6 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 07/25] drm/i915/display: move pps_mmio_base " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 09/25] drm/i915/display: move drrs into display struct Dave Airlie
` (19 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
this makes it easier to move this struct later.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_drrs.c | 90 ++++++++++++-----------
1 file changed, 49 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index a2b65eca1441..670bcd50a56f 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -191,15 +191,16 @@ void intel_drrs_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct i915_drrs *drrs = &dev_priv->drrs;
if (!crtc_state->has_drrs)
return;
drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
- mutex_lock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
- if (dev_priv->drrs.dp) {
+ if (drrs->dp) {
drm_warn(&dev_priv->drm, "DRRS already enabled\n");
goto unlock;
}
@@ -207,7 +208,7 @@ void intel_drrs_enable(struct intel_dp *intel_dp,
intel_drrs_enable_locked(intel_dp);
unlock:
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
}
static void
@@ -215,15 +216,16 @@ intel_drrs_disable_locked(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct i915_drrs *drrs = &dev_priv->drrs;
- if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
+ if (drrs->refresh_rate_type == DRRS_LOW_RR) {
int refresh;
refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
intel_drrs_set_state(dev_priv, crtc_state, refresh);
}
- dev_priv->drrs.dp = NULL;
+ drrs->dp = NULL;
}
/**
@@ -236,20 +238,21 @@ void intel_drrs_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct i915_drrs *drrs = &dev_priv->drrs;
if (!old_crtc_state->has_drrs)
return;
- mutex_lock(&dev_priv->drrs.mutex);
- if (!dev_priv->drrs.dp) {
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
+ if (!drrs->dp) {
+ mutex_unlock(&drrs->mutex);
return;
}
intel_drrs_disable_locked(intel_dp, old_crtc_state);
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
- cancel_delayed_work_sync(&dev_priv->drrs.work);
+ cancel_delayed_work_sync(&drrs->work);
}
/**
@@ -266,14 +269,15 @@ intel_drrs_update(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct i915_drrs *drrs = &dev_priv->drrs;
- if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
+ if (drrs->type != SEAMLESS_DRRS_SUPPORT)
return;
- mutex_lock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
/* New state matches current one? */
- if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
+ if (crtc_state->has_drrs == !!drrs->dp)
goto unlock;
if (crtc_state->has_drrs)
@@ -282,18 +286,19 @@ intel_drrs_update(struct intel_dp *intel_dp,
intel_drrs_disable_locked(intel_dp, crtc_state);
unlock:
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
}
static void intel_drrs_downclock_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv), drrs.work.work);
+ struct i915_drrs *drrs = &dev_priv->drrs;
struct intel_dp *intel_dp;
- mutex_lock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
- intel_dp = dev_priv->drrs.dp;
+ intel_dp = drrs->dp;
if (!intel_dp)
goto unlock;
@@ -303,10 +308,10 @@ static void intel_drrs_downclock_work(struct work_struct *work)
* recheck.
*/
- if (dev_priv->drrs.busy_frontbuffer_bits)
+ if (drrs->busy_frontbuffer_bits)
goto unlock;
- if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
+ if (drrs->refresh_rate_type != DRRS_LOW_RR) {
struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config,
@@ -314,7 +319,7 @@ static void intel_drrs_downclock_work(struct work_struct *work)
}
unlock:
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
}
/**
@@ -330,20 +335,21 @@ static void intel_drrs_downclock_work(struct work_struct *work)
void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits)
{
+ struct i915_drrs *drrs = &dev_priv->drrs;
struct intel_dp *intel_dp;
struct drm_crtc *crtc;
enum pipe pipe;
- if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
+ if (drrs->type == DRRS_NOT_SUPPORTED)
return;
- cancel_delayed_work(&dev_priv->drrs.work);
+ cancel_delayed_work(&drrs->work);
- mutex_lock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
- intel_dp = dev_priv->drrs.dp;
+ intel_dp = drrs->dp;
if (!intel_dp) {
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
return;
}
@@ -351,14 +357,14 @@ void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
pipe = to_intel_crtc(crtc)->pipe;
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
- dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
+ drrs->busy_frontbuffer_bits |= frontbuffer_bits;
/* invalidate means busy screen hence upclock */
- if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
+ if (frontbuffer_bits && drrs->refresh_rate_type == DRRS_LOW_RR)
intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config,
drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
}
/**
@@ -376,20 +382,21 @@ void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
void intel_drrs_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits)
{
+ struct i915_drrs *drrs = &dev_priv->drrs;
struct intel_dp *intel_dp;
struct drm_crtc *crtc;
enum pipe pipe;
- if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
+ if (drrs->type == DRRS_NOT_SUPPORTED)
return;
- cancel_delayed_work(&dev_priv->drrs.work);
+ cancel_delayed_work(&drrs->work);
- mutex_lock(&dev_priv->drrs.mutex);
+ mutex_lock(&drrs->mutex);
- intel_dp = dev_priv->drrs.dp;
+ intel_dp = drrs->dp;
if (!intel_dp) {
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
return;
}
@@ -397,10 +404,10 @@ void intel_drrs_flush(struct drm_i915_private *dev_priv,
pipe = to_intel_crtc(crtc)->pipe;
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
- dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
+ drrs->busy_frontbuffer_bits &= ~frontbuffer_bits;
/* flush means busy screen hence upclock */
- if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
+ if (frontbuffer_bits && drrs->refresh_rate_type == DRRS_LOW_RR)
intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config,
drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
@@ -408,10 +415,10 @@ void intel_drrs_flush(struct drm_i915_private *dev_priv,
* flush also means no more activity hence schedule downclock, if all
* other fbs are quiescent too
*/
- if (!dev_priv->drrs.busy_frontbuffer_bits)
- schedule_delayed_work(&dev_priv->drrs.work,
+ if (!drrs->busy_frontbuffer_bits)
+ schedule_delayed_work(&drrs->work,
msecs_to_jiffies(1000));
- mutex_unlock(&dev_priv->drrs.mutex);
+ mutex_unlock(&drrs->mutex);
}
/**
@@ -432,10 +439,11 @@ intel_drrs_init(struct intel_connector *connector,
struct drm_display_mode *fixed_mode)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct i915_drrs *drrs = &dev_priv->drrs;
struct drm_display_mode *downclock_mode = NULL;
- INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_drrs_downclock_work);
- mutex_init(&dev_priv->drrs.mutex);
+ INIT_DELAYED_WORK(&drrs->work, intel_drrs_downclock_work);
+ mutex_init(&drrs->mutex);
if (DISPLAY_VER(dev_priv) <= 6) {
drm_dbg_kms(&dev_priv->drm,
@@ -455,9 +463,9 @@ intel_drrs_init(struct intel_connector *connector,
return NULL;
}
- dev_priv->drrs.type = dev_priv->vbt.drrs_type;
+ drrs->type = dev_priv->vbt.drrs_type;
- dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
+ drrs->refresh_rate_type = DRRS_HIGH_RR;
drm_dbg_kms(&dev_priv->drm,
"seamless DRRS supported for eDP panel.\n");
return downclock_mode;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 09/25] drm/i915/display: move drrs into display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (7 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 08/25] drm/i915/drrs: just use some local vars to simplify drrs code Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 10/25] drm/i915/display: move fbc " Dave Airlie
` (18 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_drrs.c | 32 +++++++++----------
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index be0601606aa1..472cd21fc788 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1234,7 +1234,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display->drrs;
int vrefresh = 0;
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 670bcd50a56f..1de93b1654ee 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -69,7 +69,7 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
return;
if (!intel_connector->panel.downclock_mode ||
- dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
+ dev_priv->display->drrs.type != SEAMLESS_DRRS_SUPPORT)
return;
pipe_config->has_drrs = true;
@@ -91,7 +91,7 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
int refresh_rate)
{
- struct intel_dp *intel_dp = dev_priv->drrs.dp;
+ struct intel_dp *intel_dp = dev_priv->display->drrs.dp;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
@@ -112,7 +112,7 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
return;
}
- if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
+ if (dev_priv->display->drrs.type < SEAMLESS_DRRS_SUPPORT) {
drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
return;
}
@@ -121,7 +121,7 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
refresh_rate)
index = DRRS_LOW_RR;
- if (index == dev_priv->drrs.refresh_rate_type) {
+ if (index == dev_priv->display->drrs.refresh_rate_type) {
drm_dbg_kms(&dev_priv->drm,
"DRRS requested for previously set RR...ignoring\n");
return;
@@ -165,7 +165,7 @@ static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, reg, val);
}
- dev_priv->drrs.refresh_rate_type = index;
+ dev_priv->display->drrs.refresh_rate_type = index;
drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
refresh_rate);
@@ -176,8 +176,8 @@ intel_drrs_enable_locked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- dev_priv->drrs.busy_frontbuffer_bits = 0;
- dev_priv->drrs.dp = intel_dp;
+ dev_priv->display->drrs.busy_frontbuffer_bits = 0;
+ dev_priv->display->drrs.dp = intel_dp;
}
/**
@@ -191,7 +191,7 @@ void intel_drrs_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display->drrs;
if (!crtc_state->has_drrs)
return;
@@ -216,7 +216,7 @@ intel_drrs_disable_locked(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display->drrs;
if (drrs->refresh_rate_type == DRRS_LOW_RR) {
int refresh;
@@ -238,7 +238,7 @@ void intel_drrs_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display->drrs;
if (!old_crtc_state->has_drrs)
return;
@@ -269,7 +269,7 @@ intel_drrs_update(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display->drrs;
if (drrs->type != SEAMLESS_DRRS_SUPPORT)
return;
@@ -292,8 +292,8 @@ intel_drrs_update(struct intel_dp *intel_dp,
static void intel_drrs_downclock_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), drrs.work.work);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ container_of(work, typeof(*dev_priv), _display.drrs.work.work);
+ struct i915_drrs *drrs = &dev_priv->display->drrs;
struct intel_dp *intel_dp;
mutex_lock(&drrs->mutex);
@@ -335,7 +335,7 @@ static void intel_drrs_downclock_work(struct work_struct *work)
void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits)
{
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display->drrs;
struct intel_dp *intel_dp;
struct drm_crtc *crtc;
enum pipe pipe;
@@ -382,7 +382,7 @@ void intel_drrs_invalidate(struct drm_i915_private *dev_priv,
void intel_drrs_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits)
{
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display->drrs;
struct intel_dp *intel_dp;
struct drm_crtc *crtc;
enum pipe pipe;
@@ -439,7 +439,7 @@ intel_drrs_init(struct intel_connector *connector,
struct drm_display_mode *fixed_mode)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct i915_drrs *drrs = &dev_priv->drrs;
+ struct i915_drrs *drrs = &dev_priv->display->drrs;
struct drm_display_mode *downclock_mode = NULL;
INIT_DELAYED_WORK(&drrs->work, intel_drrs_downclock_work);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e07b7ee169bd..2be2e83d636c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1225,7 +1225,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
if (!crtc_state->has_psr)
return;
- drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display->drrs.dp);
mutex_lock(&intel_dp->psr.lock);
intel_psr_enable_locked(intel_dp, crtc_state, conn_state);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 738bb87b1fb8..8daa5a24782f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -867,6 +867,7 @@ struct drm_i915_display {
wait_queue_head_t gmbus_wait_queue;
struct intel_dmc dmc;
+ struct i915_drrs drrs;
};
struct drm_i915_private {
@@ -942,7 +943,6 @@ struct drm_i915_private {
struct i915_hotplug hotplug;
struct intel_fbc fbc;
- struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 10/25] drm/i915/display: move fbc into display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (8 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 09/25] drm/i915/display: move drrs into display struct Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 11/25] drm/i915/display: move pipe/plane mappings to " Dave Airlie
` (17 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
.../drm/i915/display/intel_display_debugfs.c | 10 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 98 +++++++++----------
.../drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
5 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1439ba78f67..7dd9aa592a45 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -791,7 +791,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane);
if (plane->has_fbc) {
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 472cd21fc788..5cd93ca2aaa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -43,7 +43,7 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
static int i915_fbc_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
intel_wakeref_t wakeref;
if (!HAS_FBC(dev_priv))
@@ -88,7 +88,7 @@ static int i915_fbc_false_color_get(void *data, u64 *val)
if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv))
return -ENODEV;
- *val = dev_priv->fbc.false_color;
+ *val = dev_priv->display->fbc.false_color;
return 0;
}
@@ -101,15 +101,15 @@ static int i915_fbc_false_color_set(void *data, u64 val)
if (DISPLAY_VER(dev_priv) < 7 || !HAS_FBC(dev_priv))
return -ENODEV;
- mutex_lock(&dev_priv->fbc.lock);
+ mutex_lock(&dev_priv->display->fbc.lock);
reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
- dev_priv->fbc.false_color = val;
+ dev_priv->display->fbc.false_color = val;
intel_de_write(dev_priv, ILK_DPFC_CONTROL,
val ? (reg | FBC_CTL_FALSE_COLOR) : (reg & ~FBC_CTL_FALSE_COLOR));
- mutex_unlock(&dev_priv->fbc.lock);
+ mutex_unlock(&dev_priv->display->fbc.lock);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index b3f47a6308f6..ed559c0fdcc5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -99,7 +99,7 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display->fbc.params;
int cfb_pitch;
int i;
u32 fbc_ctl;
@@ -150,8 +150,8 @@ static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915)
{
- const struct intel_fbc_reg_params *params = &i915->fbc.params;
- int limit = i915->fbc.limit;
+ const struct intel_fbc_reg_params *params = &i915->display->fbc.params;
+ int limit = i915->display->fbc.limit;
if (params->fb.format->cpp[0] == 2)
limit <<= 1;
@@ -171,7 +171,7 @@ static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915)
static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display->fbc.params;
u32 dpfc_ctl;
dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
@@ -209,7 +209,7 @@ static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display->fbc.params;
enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
spin_lock_irq(&dev_priv->uncore.lock);
@@ -220,7 +220,7 @@ static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display->fbc.params;
enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
spin_lock_irq(&dev_priv->uncore.lock);
@@ -238,7 +238,7 @@ static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
trace_intel_fbc_nuke(fbc->crtc);
@@ -252,7 +252,7 @@ static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display->fbc.params;
u32 dpfc_ctl;
dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
@@ -301,7 +301,7 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_reg_params *params = &dev_priv->display->fbc.params;
u32 dpfc_ctl;
/* Display WA #0529: skl, kbl, bxt. */
@@ -334,7 +334,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
}
- if (dev_priv->fbc.false_color)
+ if (dev_priv->display->fbc.false_color)
dpfc_ctl |= FBC_CTL_FALSE_COLOR;
intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
@@ -352,7 +352,7 @@ static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
trace_intel_fbc_activate(fbc->crtc);
@@ -371,7 +371,7 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
trace_intel_fbc_deactivate(fbc->crtc);
@@ -396,7 +396,7 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
*/
bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
{
- return dev_priv->fbc.active;
+ return dev_priv->display->fbc.active;
}
static void intel_fbc_activate(struct drm_i915_private *dev_priv)
@@ -408,7 +408,7 @@ static void intel_fbc_activate(struct drm_i915_private *dev_priv)
static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
const char *reason)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
@@ -464,7 +464,7 @@ static int find_compression_limit(struct drm_i915_private *dev_priv,
unsigned int size,
unsigned int fb_cpp)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
u64 end = intel_fbc_stolen_end(dev_priv);
int ret, limit = 1;
@@ -487,7 +487,7 @@ static int find_compression_limit(struct drm_i915_private *dev_priv,
static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
unsigned int size, unsigned int fb_cpp)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
int ret;
drm_WARN_ON(&dev_priv->drm,
@@ -529,7 +529,7 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
static void intel_fbc_program_cfb(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
if (DISPLAY_VER(dev_priv) >= 5) {
intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
@@ -554,7 +554,7 @@ static void intel_fbc_program_cfb(struct drm_i915_private *dev_priv)
static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
return;
@@ -567,7 +567,7 @@ static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
if (!HAS_FBC(dev_priv))
return;
@@ -648,7 +648,7 @@ static bool rotation_is_valid(struct drm_i915_private *dev_priv,
static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
unsigned int effective_w, effective_h, max_w, max_h;
if (DISPLAY_VER(dev_priv) >= 10) {
@@ -692,7 +692,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
struct drm_framebuffer *fb = plane_state->hw.fb;
@@ -744,7 +744,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
fbc->compressed_fb.size * fbc->limit;
@@ -752,7 +752,7 @@ static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
if ((DISPLAY_VER(dev_priv) == 9) &&
@@ -764,14 +764,14 @@ static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
static bool intel_fbc_override_cfb_stride_changed(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
return fbc->params.override_cfb_stride != intel_fbc_override_cfb_stride(dev_priv);
}
static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
if (intel_vgpu_active(dev_priv)) {
fbc->no_fbc_reason = "VGPU is active";
@@ -794,7 +794,7 @@ static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
static bool intel_fbc_can_activate(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
if (!intel_fbc_can_enable(dev_priv))
@@ -929,7 +929,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
struct intel_fbc_reg_params *params)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
/* Since all our fields are integer types, use memset here so the
@@ -960,7 +960,7 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct intel_fbc *fbc = &dev_priv->fbc;
+ const struct intel_fbc *fbc = &dev_priv->display->fbc;
const struct intel_fbc_state_cache *cache = &fbc->state_cache;
const struct intel_fbc_reg_params *params = &fbc->params;
@@ -1000,7 +1000,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
const char *reason = "update pending";
bool need_vblank_wait = false;
@@ -1051,7 +1051,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
*/
static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
struct intel_crtc *crtc = fbc->crtc;
drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
@@ -1069,7 +1069,7 @@ static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
static void __intel_fbc_post_update(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
@@ -1103,7 +1103,7 @@ void intel_fbc_post_update(struct intel_atomic_state *state,
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
if (!plane->has_fbc || !plane_state)
return;
@@ -1125,7 +1125,7 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits,
enum fb_op_origin origin)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
if (!HAS_FBC(dev_priv))
return;
@@ -1146,7 +1146,7 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
void intel_fbc_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits, enum fb_op_origin origin)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
if (!HAS_FBC(dev_priv))
return;
@@ -1180,12 +1180,12 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv,
* true.
*
* Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
- * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
+ * enable FBC for the chosen CRTC. If it does, it will set dev_priv->display->fbc.crtc.
*/
void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
struct intel_atomic_state *state)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
struct intel_plane *plane;
struct intel_plane_state *plane_state;
bool crtc_chosen = false;
@@ -1248,7 +1248,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
if (!plane->has_fbc || !plane_state)
@@ -1304,7 +1304,7 @@ void intel_fbc_disable(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
if (!plane->has_fbc)
return;
@@ -1345,7 +1345,7 @@ void intel_fbc_update(struct intel_atomic_state *state,
*/
void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
if (!HAS_FBC(dev_priv))
return;
@@ -1361,8 +1361,8 @@ void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
static void intel_fbc_underrun_work_fn(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, struct drm_i915_private, fbc.underrun_work);
- struct intel_fbc *fbc = &dev_priv->fbc;
+ container_of(work, struct drm_i915_private, _display.fbc.underrun_work);
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
mutex_lock(&fbc->lock);
@@ -1389,20 +1389,20 @@ int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
{
int ret;
- cancel_work_sync(&dev_priv->fbc.underrun_work);
+ cancel_work_sync(&dev_priv->display->fbc.underrun_work);
- ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
+ ret = mutex_lock_interruptible(&dev_priv->display->fbc.lock);
if (ret)
return ret;
- if (dev_priv->fbc.underrun_detected) {
+ if (dev_priv->display->fbc.underrun_detected) {
drm_dbg_kms(&dev_priv->drm,
"Re-allowing FBC after fifo underrun\n");
- dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
+ dev_priv->display->fbc.no_fbc_reason = "FIFO underrun cleared";
}
- dev_priv->fbc.underrun_detected = false;
- mutex_unlock(&dev_priv->fbc.lock);
+ dev_priv->display->fbc.underrun_detected = false;
+ mutex_unlock(&dev_priv->display->fbc.lock);
return 0;
}
@@ -1423,7 +1423,7 @@ int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
*/
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
if (!HAS_FBC(dev_priv))
return;
@@ -1484,7 +1484,7 @@ static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
*/
void intel_fbc_init(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
mutex_init(&fbc->lock);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 724e7b04f3b6..510eaa7f68c8 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2067,7 +2067,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id);
if (plane->has_fbc) {
- struct intel_fbc *fbc = &dev_priv->fbc;
+ struct intel_fbc *fbc = &dev_priv->display->fbc;
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8daa5a24782f..b94f25eb6ce5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -868,6 +868,7 @@ struct drm_i915_display {
struct intel_dmc dmc;
struct i915_drrs drrs;
+ struct intel_fbc fbc;
};
struct drm_i915_private {
@@ -942,7 +943,6 @@ struct drm_i915_private {
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct i915_hotplug hotplug;
- struct intel_fbc fbc;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 11/25] drm/i915/display: move pipe/plane mappings to display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (9 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 10/25] drm/i915/display: move fbc " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 12/25] drm/i915/display: move properties into " Dave Airlie
` (16 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_display_types.h | 8 ++++----
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 254e67141a77..2b7dd0c69e74 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -323,16 +323,16 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
if (ret)
goto fail;
- BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||
- dev_priv->pipe_to_crtc_mapping[pipe] != NULL);
- dev_priv->pipe_to_crtc_mapping[pipe] = crtc;
+ BUG_ON(pipe >= ARRAY_SIZE(dev_priv->display->pipe_to_crtc_mapping) ||
+ dev_priv->display->pipe_to_crtc_mapping[pipe] != NULL);
+ dev_priv->display->pipe_to_crtc_mapping[pipe] = crtc;
if (DISPLAY_VER(dev_priv) < 9) {
enum i9xx_plane_id i9xx_plane = primary->i9xx_plane;
- BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
- dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL);
- dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
+ BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->display->plane_to_crtc_mapping) ||
+ dev_priv->display->plane_to_crtc_mapping[i9xx_plane] != NULL);
+ dev_priv->display->plane_to_crtc_mapping[i9xx_plane] = crtc;
}
if (DISPLAY_VER(dev_priv) >= 11)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c7bcf9183447..8df06b6233b8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1754,9 +1754,9 @@ vlv_pipe_to_channel(enum pipe pipe)
static inline bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe pipe)
{
return (pipe >= 0 &&
- pipe < ARRAY_SIZE(i915->pipe_to_crtc_mapping) &&
+ pipe < ARRAY_SIZE(i915->display->pipe_to_crtc_mapping) &&
INTEL_INFO(i915)->pipe_mask & BIT(pipe) &&
- i915->pipe_to_crtc_mapping[pipe]);
+ i915->display->pipe_to_crtc_mapping[pipe]);
}
static inline struct intel_crtc *
@@ -1771,13 +1771,13 @@ intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
/* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
drm_WARN_ON(&dev_priv->drm,
!(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
- return dev_priv->pipe_to_crtc_mapping[pipe];
+ return dev_priv->display->pipe_to_crtc_mapping[pipe];
}
static inline struct intel_crtc *
intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
{
- return dev_priv->plane_to_crtc_mapping[plane];
+ return dev_priv->display->plane_to_crtc_mapping[plane];
}
struct intel_load_detect_pipe {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b94f25eb6ce5..1abeda306d05 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -869,6 +869,9 @@ struct drm_i915_display {
struct intel_dmc dmc;
struct i915_drrs drrs;
struct intel_fbc fbc;
+
+ struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
+ struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
};
struct drm_i915_private {
@@ -995,9 +998,6 @@ struct drm_i915_private {
/* Kernel Modesetting */
- struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
- struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
-
/**
* dpll and cdclk state is protected by connection_mutex
* dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 12/25] drm/i915/display: move properties into display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (10 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 11/25] drm/i915/display: move pipe/plane mappings to " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 13/25] drm/i915/display: move audio related members " Dave Airlie
` (15 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_connector.c | 8 ++++----
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index b4e7ac51aa31..ee6c088f84f5 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -61,9 +61,9 @@ int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(state);
- if (property == dev_priv->force_audio_property)
+ if (property == dev_priv->display->force_audio_property)
*val = intel_conn_state->force_audio;
- else if (property == dev_priv->broadcast_rgb_property)
+ else if (property == dev_priv->display->broadcast_rgb_property)
*val = intel_conn_state->broadcast_rgb;
else {
drm_dbg_atomic(&dev_priv->drm,
@@ -94,12 +94,12 @@ int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(state);
- if (property == dev_priv->force_audio_property) {
+ if (property == dev_priv->display->force_audio_property) {
intel_conn_state->force_audio = val;
return 0;
}
- if (property == dev_priv->broadcast_rgb_property) {
+ if (property == dev_priv->display->broadcast_rgb_property) {
intel_conn_state->broadcast_rgb = val;
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c
index 4f49d782eca2..233a2df9e2c0 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -227,7 +227,7 @@ intel_attach_force_audio_property(struct drm_connector *connector)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_property *prop;
- prop = dev_priv->force_audio_property;
+ prop = dev_priv->display->force_audio_property;
if (prop == NULL) {
prop = drm_property_create_enum(dev, 0,
"audio",
@@ -236,7 +236,7 @@ intel_attach_force_audio_property(struct drm_connector *connector)
if (prop == NULL)
return;
- dev_priv->force_audio_property = prop;
+ dev_priv->display->force_audio_property = prop;
}
drm_object_attach_property(&connector->base, prop, 0);
}
@@ -254,7 +254,7 @@ intel_attach_broadcast_rgb_property(struct drm_connector *connector)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_property *prop;
- prop = dev_priv->broadcast_rgb_property;
+ prop = dev_priv->display->broadcast_rgb_property;
if (prop == NULL) {
prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
"Broadcast RGB",
@@ -263,7 +263,7 @@ intel_attach_broadcast_rgb_property(struct drm_connector *connector)
if (prop == NULL)
return;
- dev_priv->broadcast_rgb_property = prop;
+ dev_priv->display->broadcast_rgb_property = prop;
}
drm_object_attach_property(&connector->base, prop, 0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1abeda306d05..3c2308a0c861 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -872,6 +872,9 @@ struct drm_i915_display {
struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
+
+ struct drm_property *broadcast_rgb_property;
+ struct drm_property *force_audio_property;
};
struct drm_i915_private {
@@ -1056,9 +1059,6 @@ struct drm_i915_private {
struct intel_fbdev *fbdev;
struct work_struct fbdev_suspend_work;
- struct drm_property *broadcast_rgb_property;
- struct drm_property *force_audio_property;
-
/* hda/i915 audio component */
struct i915_audio_component *audio_component;
bool audio_component_registered;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 13/25] drm/i915/display: move audio related members into display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (11 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 12/25] drm/i915/display: move properties into " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 14/25] drm/i915/display: move HDCP related items " Dave Airlie
` (14 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 72 +++++++++----------
.../gpu/drm/i915/display/intel_lpe_audio.c | 42 +++++------
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 38 +++++-----
4 files changed, 76 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 671af864fe0b..7a94f12ae842 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -388,7 +388,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio_component;
+ struct i915_audio_component *acomp = dev_priv->display->audio_component;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
const struct dp_aud_n_m *nm;
@@ -436,7 +436,7 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio_component;
+ struct i915_audio_component *acomp = dev_priv->display->audio_component;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
int n, rate;
@@ -494,7 +494,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder,
drm_dbg_kms(&dev_priv->drm, "Disable audio codec on transcoder %s\n",
transcoder_name(cpu_transcoder));
- mutex_lock(&dev_priv->av_mutex);
+ mutex_lock(&dev_priv->display->av_mutex);
/* Disable timestamps */
tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
@@ -512,7 +512,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder,
tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
- mutex_unlock(&dev_priv->av_mutex);
+ mutex_unlock(&dev_priv->display->av_mutex);
}
static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
@@ -641,7 +641,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
"Enable audio codec on transcoder %s, %u bytes ELD\n",
transcoder_name(cpu_transcoder), drm_eld_size(eld));
- mutex_lock(&dev_priv->av_mutex);
+ mutex_lock(&dev_priv->display->av_mutex);
/* Enable Audio WA for 4k DSC usecases */
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
@@ -679,7 +679,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
/* Enable timestamps */
hsw_audio_config_update(encoder, crtc_state);
- mutex_unlock(&dev_priv->av_mutex);
+ mutex_unlock(&dev_priv->display->av_mutex);
}
static void ilk_audio_codec_disable(struct intel_encoder *encoder,
@@ -826,7 +826,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio_component;
+ struct i915_audio_component *acomp = dev_priv->display->audio_component;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_connector *connector = conn_state->connector;
const struct drm_display_mode *adjusted_mode =
@@ -853,12 +853,12 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
crtc_state,
conn_state);
- mutex_lock(&dev_priv->av_mutex);
+ mutex_lock(&dev_priv->display->av_mutex);
encoder->audio_connector = connector;
/* referred in audio callbacks */
- dev_priv->av_enc_map[pipe] = encoder;
- mutex_unlock(&dev_priv->av_mutex);
+ dev_priv->display->av_enc_map[pipe] = encoder;
+ mutex_unlock(&dev_priv->display->av_mutex);
if (acomp && acomp->base.audio_ops &&
acomp->base.audio_ops->pin_eld_notify) {
@@ -888,7 +888,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
const struct drm_connector_state *old_conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio_component;
+ struct i915_audio_component *acomp = dev_priv->display->audio_component;
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
@@ -898,10 +898,10 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
old_crtc_state,
old_conn_state);
- mutex_lock(&dev_priv->av_mutex);
+ mutex_lock(&dev_priv->display->av_mutex);
encoder->audio_connector = NULL;
- dev_priv->av_enc_map[pipe] = NULL;
- mutex_unlock(&dev_priv->av_mutex);
+ dev_priv->display->av_enc_map[pipe] = NULL;
+ mutex_unlock(&dev_priv->display->av_mutex);
if (acomp && acomp->base.audio_ops &&
acomp->base.audio_ops->pin_eld_notify) {
@@ -1003,13 +1003,13 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK);
- if (dev_priv->audio_power_refcount++ == 0) {
+ if (dev_priv->display->audio_power_refcount++ == 0) {
if (DISPLAY_VER(dev_priv) >= 9) {
intel_de_write(dev_priv, AUD_FREQ_CNTRL,
- dev_priv->audio_freq_cntrl);
+ dev_priv->display->audio_freq_cntrl);
drm_dbg_kms(&dev_priv->drm,
"restored AUD_FREQ_CNTRL to 0x%x\n",
- dev_priv->audio_freq_cntrl);
+ dev_priv->display->audio_freq_cntrl);
}
/* Force CDCLK to 2*BCLK as long as we need audio powered. */
@@ -1030,7 +1030,7 @@ static void i915_audio_component_put_power(struct device *kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
- if (--dev_priv->audio_power_refcount == 0)
+ if (--dev_priv->display->audio_power_refcount == 0)
if (IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, false);
@@ -1097,10 +1097,10 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
/* MST */
if (pipe >= 0) {
if (drm_WARN_ON(&dev_priv->drm,
- pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
+ pipe >= ARRAY_SIZE(dev_priv->display->av_enc_map)))
return NULL;
- encoder = dev_priv->av_enc_map[pipe];
+ encoder = dev_priv->display->av_enc_map[pipe];
/*
* when bootup, audio driver may not know it is
* MST or not. So it will poll all the port & pipe
@@ -1116,7 +1116,7 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
return NULL;
for_each_pipe(dev_priv, pipe) {
- encoder = dev_priv->av_enc_map[pipe];
+ encoder = dev_priv->display->av_enc_map[pipe];
if (encoder == NULL)
continue;
@@ -1134,7 +1134,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
int pipe, int rate)
{
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
- struct i915_audio_component *acomp = dev_priv->audio_component;
+ struct i915_audio_component *acomp = dev_priv->display->audio_component;
struct intel_encoder *encoder;
struct intel_crtc *crtc;
unsigned long cookie;
@@ -1144,7 +1144,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
return 0;
cookie = i915_audio_component_get_power(kdev);
- mutex_lock(&dev_priv->av_mutex);
+ mutex_lock(&dev_priv->display->av_mutex);
/* 1. get the pipe */
encoder = get_saved_enc(dev_priv, port, pipe);
@@ -1163,7 +1163,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
hsw_audio_config_update(encoder, crtc->config);
unlock:
- mutex_unlock(&dev_priv->av_mutex);
+ mutex_unlock(&dev_priv->display->av_mutex);
i915_audio_component_put_power(kdev, cookie);
return err;
}
@@ -1177,13 +1177,13 @@ static int i915_audio_component_get_eld(struct device *kdev, int port,
const u8 *eld;
int ret = -EINVAL;
- mutex_lock(&dev_priv->av_mutex);
+ mutex_lock(&dev_priv->display->av_mutex);
intel_encoder = get_saved_enc(dev_priv, port, pipe);
if (!intel_encoder) {
drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
port_name(port));
- mutex_unlock(&dev_priv->av_mutex);
+ mutex_unlock(&dev_priv->display->av_mutex);
return ret;
}
@@ -1195,7 +1195,7 @@ static int i915_audio_component_get_eld(struct device *kdev, int port,
memcpy(buf, eld, min(max_bytes, ret));
}
- mutex_unlock(&dev_priv->av_mutex);
+ mutex_unlock(&dev_priv->display->av_mutex);
return ret;
}
@@ -1230,7 +1230,7 @@ static int i915_audio_component_bind(struct device *i915_kdev,
BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
acomp->aud_sample_rate[i] = 0;
- dev_priv->audio_component = acomp;
+ dev_priv->display->audio_component = acomp;
drm_modeset_unlock_all(&dev_priv->drm);
return 0;
@@ -1245,14 +1245,14 @@ static void i915_audio_component_unbind(struct device *i915_kdev,
drm_modeset_lock_all(&dev_priv->drm);
acomp->base.ops = NULL;
acomp->base.dev = NULL;
- dev_priv->audio_component = NULL;
+ dev_priv->display->audio_component = NULL;
drm_modeset_unlock_all(&dev_priv->drm);
device_link_remove(hda_kdev, i915_kdev);
- if (dev_priv->audio_power_refcount)
+ if (dev_priv->display->audio_power_refcount)
drm_err(&dev_priv->drm, "audio power refcount %d after unbind\n",
- dev_priv->audio_power_refcount);
+ dev_priv->display->audio_power_refcount);
}
static const struct component_ops i915_audio_component_bind_ops = {
@@ -1315,10 +1315,10 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",
aud_freq, aud_freq_init);
- dev_priv->audio_freq_cntrl = aud_freq;
+ dev_priv->display->audio_freq_cntrl = aud_freq;
}
- dev_priv->audio_component_registered = true;
+ dev_priv->display->audio_component_registered = true;
}
/**
@@ -1330,11 +1330,11 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
*/
static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
{
- if (!dev_priv->audio_component_registered)
+ if (!dev_priv->display->audio_component_registered)
return;
component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
- dev_priv->audio_component_registered = false;
+ dev_priv->display->audio_component_registered = false;
}
/**
@@ -1356,7 +1356,7 @@ void intel_audio_init(struct drm_i915_private *dev_priv)
*/
void intel_audio_deinit(struct drm_i915_private *dev_priv)
{
- if ((dev_priv)->lpe_audio.platdev != NULL)
+ if ((dev_priv)->display->lpe_audio.platdev != NULL)
intel_lpe_audio_teardown(dev_priv);
else
i915_audio_component_cleanup(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
index 7f3c638c8950..ba1b6c049c43 100644
--- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
@@ -74,7 +74,7 @@
#include "intel_de.h"
#include "intel_lpe_audio.h"
-#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->lpe_audio.platdev != NULL)
+#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display->lpe_audio.platdev != NULL)
static struct platform_device *
lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
@@ -96,7 +96,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
return ERR_PTR(-ENOMEM);
}
- rsc[0].start = rsc[0].end = dev_priv->lpe_audio.irq;
+ rsc[0].start = rsc[0].end = dev_priv->display->lpe_audio.irq;
rsc[0].flags = IORESOURCE_IRQ;
rsc[0].name = "hdmi-lpe-audio-irq";
@@ -148,7 +148,7 @@ static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv)
* than us fiddle with its internals.
*/
- platform_device_unregister(dev_priv->lpe_audio.platdev);
+ platform_device_unregister(dev_priv->display->lpe_audio.platdev);
}
static void lpe_audio_irq_unmask(struct irq_data *d)
@@ -167,7 +167,7 @@ static struct irq_chip lpe_audio_irqchip = {
static int lpe_audio_irq_init(struct drm_i915_private *dev_priv)
{
- int irq = dev_priv->lpe_audio.irq;
+ int irq = dev_priv->display->lpe_audio.irq;
drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
irq_set_chip_and_handler_name(irq,
@@ -204,15 +204,15 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv)
{
int ret;
- dev_priv->lpe_audio.irq = irq_alloc_desc(0);
- if (dev_priv->lpe_audio.irq < 0) {
+ dev_priv->display->lpe_audio.irq = irq_alloc_desc(0);
+ if (dev_priv->display->lpe_audio.irq < 0) {
drm_err(&dev_priv->drm, "Failed to allocate IRQ desc: %d\n",
- dev_priv->lpe_audio.irq);
- ret = dev_priv->lpe_audio.irq;
+ dev_priv->display->lpe_audio.irq);
+ ret = dev_priv->display->lpe_audio.irq;
goto err;
}
- drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->lpe_audio.irq);
+ drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->display->lpe_audio.irq);
ret = lpe_audio_irq_init(dev_priv);
@@ -223,10 +223,10 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv)
goto err_free_irq;
}
- dev_priv->lpe_audio.platdev = lpe_audio_platdev_create(dev_priv);
+ dev_priv->display->lpe_audio.platdev = lpe_audio_platdev_create(dev_priv);
- if (IS_ERR(dev_priv->lpe_audio.platdev)) {
- ret = PTR_ERR(dev_priv->lpe_audio.platdev);
+ if (IS_ERR(dev_priv->display->lpe_audio.platdev)) {
+ ret = PTR_ERR(dev_priv->display->lpe_audio.platdev);
drm_err(&dev_priv->drm,
"Failed to create lpe audio platform device: %d\n",
ret);
@@ -241,10 +241,10 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv)
return 0;
err_free_irq:
- irq_free_desc(dev_priv->lpe_audio.irq);
+ irq_free_desc(dev_priv->display->lpe_audio.irq);
err:
- dev_priv->lpe_audio.irq = -1;
- dev_priv->lpe_audio.platdev = NULL;
+ dev_priv->display->lpe_audio.irq = -1;
+ dev_priv->display->lpe_audio.platdev = NULL;
return ret;
}
@@ -262,7 +262,7 @@ void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv)
if (!HAS_LPE_AUDIO(dev_priv))
return;
- ret = generic_handle_irq(dev_priv->lpe_audio.irq);
+ ret = generic_handle_irq(dev_priv->display->lpe_audio.irq);
if (ret)
drm_err_ratelimited(&dev_priv->drm,
"error handling LPE audio irq: %d\n", ret);
@@ -303,10 +303,10 @@ void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv)
lpe_audio_platdev_destroy(dev_priv);
- irq_free_desc(dev_priv->lpe_audio.irq);
+ irq_free_desc(dev_priv->display->lpe_audio.irq);
- dev_priv->lpe_audio.irq = -1;
- dev_priv->lpe_audio.platdev = NULL;
+ dev_priv->display->lpe_audio.irq = -1;
+ dev_priv->display->lpe_audio.platdev = NULL;
}
/**
@@ -333,7 +333,7 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
if (!HAS_LPE_AUDIO(dev_priv))
return;
- pdata = dev_get_platdata(&dev_priv->lpe_audio.platdev->dev);
+ pdata = dev_get_platdata(&dev_priv->display->lpe_audio.platdev->dev);
ppdata = &pdata->port[port - PORT_B];
spin_lock_irqsave(&pdata->lpe_audio_slock, irqflags);
@@ -361,7 +361,7 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
}
if (pdata->notify_audio_lpe)
- pdata->notify_audio_lpe(dev_priv->lpe_audio.platdev, port - PORT_B);
+ pdata->notify_audio_lpe(dev_priv->display->lpe_audio.platdev, port - PORT_B);
spin_unlock_irqrestore(&pdata->lpe_audio_slock, irqflags);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 87c3db974c4c..d0d97a6d37ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -320,7 +320,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->sb_lock);
cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
- mutex_init(&dev_priv->av_mutex);
+ mutex_init(&dev_priv->display->av_mutex);
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3c2308a0c861..be496ec4917a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -873,6 +873,24 @@ struct drm_i915_display {
struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
+ /* hda/i915 audio component */
+ struct i915_audio_component *audio_component;
+ bool audio_component_registered;
+ /**
+ * av_mutex - mutex for audio/video sync
+ *
+ */
+ struct mutex av_mutex;
+ int audio_power_refcount;
+ u32 audio_freq_cntrl;
+ /* Used to save the pipe-to-encoder mapping for audio */
+ struct intel_encoder *av_enc_map[I915_MAX_PIPES];
+ /* necessary resource sharing with HDMI LPE audio driver. */
+ struct {
+ struct platform_device *platdev;
+ int irq;
+ } lpe_audio;
+
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
};
@@ -1059,17 +1077,6 @@ struct drm_i915_private {
struct intel_fbdev *fbdev;
struct work_struct fbdev_suspend_work;
- /* hda/i915 audio component */
- struct i915_audio_component *audio_component;
- bool audio_component_registered;
- /**
- * av_mutex - mutex for audio/video sync
- *
- */
- struct mutex av_mutex;
- int audio_power_refcount;
- u32 audio_freq_cntrl;
-
u32 fdi_rx_config;
/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
@@ -1202,15 +1209,6 @@ struct drm_i915_private {
bool ipc_enabled;
- /* Used to save the pipe-to-encoder mapping for audio */
- struct intel_encoder *av_enc_map[I915_MAX_PIPES];
-
- /* necessary resource sharing with HDMI LPE audio driver. */
- struct {
- struct platform_device *platdev;
- int irq;
- } lpe_audio;
-
struct i915_pmu pmu;
struct i915_hdcp_comp_master *hdcp_master;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 14/25] drm/i915/display: move HDCP related items into display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (12 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 13/25] drm/i915/display: move audio related members " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 15/25] drm/i915/display: move hotplug struct to " Dave Airlie
` (13 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 134 +++++++++++-----------
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 12 +-
3 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index ebc2e32aec0b..db073065a968 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -182,12 +182,12 @@ bool intel_hdcp2_capable(struct intel_connector *connector)
return false;
/* MEI interface is solid */
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- if (!dev_priv->hdcp_comp_added || !dev_priv->hdcp_master) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ if (!dev_priv->display->hdcp_comp_added || !dev_priv->display->hdcp_master) {
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return false;
}
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
/* Sink's capability for HDCP2.2 */
hdcp->shim->hdcp_2_2_capable(dig_port, &capable);
@@ -1119,11 +1119,11 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
@@ -1131,7 +1131,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
if (ret)
drm_dbg_kms(&dev_priv->drm, "Prepare_ake_init failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -1149,11 +1149,11 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
@@ -1163,7 +1163,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify rx_cert failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -1177,18 +1177,18 @@ static int hdcp2_verify_hprime(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime);
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify hprime failed. %d\n", ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -1203,11 +1203,11 @@ hdcp2_store_pairing_info(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
@@ -1215,7 +1215,7 @@ hdcp2_store_pairing_info(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Store pairing info failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -1230,11 +1230,11 @@ hdcp2_prepare_lc_init(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
@@ -1242,7 +1242,7 @@ hdcp2_prepare_lc_init(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Prepare lc_init failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -1257,11 +1257,11 @@ hdcp2_verify_lprime(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
@@ -1269,7 +1269,7 @@ hdcp2_verify_lprime(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify L_Prime failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -1283,11 +1283,11 @@ static int hdcp2_prepare_skey(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
@@ -1295,7 +1295,7 @@ static int hdcp2_prepare_skey(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Get session key failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -1312,11 +1312,11 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
@@ -1326,7 +1326,7 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm,
"Verify rep topology failed. %d\n", ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -1341,18 +1341,18 @@ hdcp2_verify_mprime(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
ret = comp->ops->verify_mprime(comp->mei_dev, data, stream_ready);
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify mprime failed. %d\n", ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -1365,11 +1365,11 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
@@ -1377,7 +1377,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Enable hdcp auth failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -1389,17 +1389,17 @@ static int hdcp2_close_mei_session(struct intel_connector *connector)
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ comp = dev_priv->display->hdcp_master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return -EINVAL;
}
ret = comp->ops->close_hdcp_session(comp->mei_dev,
&dig_port->hdcp_port_data);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return ret;
}
@@ -2113,10 +2113,10 @@ static int i915_hdcp_component_bind(struct device *i915_kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
drm_dbg(&dev_priv->drm, "I915 HDCP comp bind\n");
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- dev_priv->hdcp_master = (struct i915_hdcp_comp_master *)data;
- dev_priv->hdcp_master->mei_dev = mei_kdev;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ dev_priv->display->hdcp_master = (struct i915_hdcp_comp_master *)data;
+ dev_priv->display->hdcp_master->mei_dev = mei_kdev;
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return 0;
}
@@ -2127,9 +2127,9 @@ static void i915_hdcp_component_unbind(struct device *i915_kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
drm_dbg(&dev_priv->drm, "I915 HDCP comp unbind\n");
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- dev_priv->hdcp_master = NULL;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ dev_priv->display->hdcp_master = NULL;
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
}
static const struct component_ops i915_hdcp_component_ops = {
@@ -2220,19 +2220,19 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
if (!is_hdcp2_supported(dev_priv))
return;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- drm_WARN_ON(&dev_priv->drm, dev_priv->hdcp_comp_added);
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display->hdcp_comp_added);
- dev_priv->hdcp_comp_added = true;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ dev_priv->display->hdcp_comp_added = true;
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops,
I915_COMPONENT_HDCP);
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm, "Failed at component add(%d)\n",
ret);
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- dev_priv->hdcp_comp_added = false;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ dev_priv->display->hdcp_comp_added = false;
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return;
}
}
@@ -2445,14 +2445,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
void intel_hdcp_component_fini(struct drm_i915_private *dev_priv)
{
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- if (!dev_priv->hdcp_comp_added) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display->hdcp_comp_mutex);
+ if (!dev_priv->display->hdcp_comp_added) {
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
return;
}
- dev_priv->hdcp_comp_added = false;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ dev_priv->display->hdcp_comp_added = false;
+ mutex_unlock(&dev_priv->display->hdcp_comp_mutex);
component_del(dev_priv->drm.dev, &i915_hdcp_component_ops);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d0d97a6d37ba..ddc183b7711c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -323,7 +323,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->display->av_mutex);
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
- mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->display->hdcp_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be496ec4917a..3f9bebb8478f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -893,6 +893,12 @@ struct drm_i915_display {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+
+ struct i915_hdcp_comp_master *hdcp_master;
+ bool hdcp_comp_added;
+
+ /* Mutex to protect the above hdcp component related values. */
+ struct mutex hdcp_comp_mutex;
};
struct drm_i915_private {
@@ -1211,12 +1217,6 @@ struct drm_i915_private {
struct i915_pmu pmu;
- struct i915_hdcp_comp_master *hdcp_master;
- bool hdcp_comp_added;
-
- /* Mutex to protect the above hdcp component related values. */
- struct mutex hdcp_comp_mutex;
-
/* The TTM device structure. */
struct ttm_device bdev;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 15/25] drm/i915/display: move hotplug struct to display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (13 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 14/25] drm/i915/display: move HDCP related items " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 16/25] drm/i915/display: move overlay into " Dave Airlie
` (12 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
I've left some _display around the workqueue stuff, since
that will need reworking maybe if we split display out, so
best to fail early.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
.../drm/i915/display/intel_display_debugfs.c | 16 +--
drivers/gpu/drm/i915/display/intel_hotplug.c | 117 +++++++++---------
drivers/gpu/drm/i915/display/intel_tc.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_irq.c | 52 ++++----
8 files changed, 105 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 9577f6843f79..f7c3eaa96509 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -1198,7 +1198,7 @@ intel_dp_hotplug(struct intel_encoder *encoder,
static bool ibx_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display->hotplug.pch_hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, SDEISR) & bit;
}
@@ -1252,7 +1252,7 @@ static bool gm45_digital_port_connected(struct intel_encoder *encoder)
static bool ilk_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display->hotplug.hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, DEISR) & bit;
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 23ef291f7b30..c9567b1dcb71 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4233,7 +4233,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
static bool lpt_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display->hotplug.pch_hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, SDEISR) & bit;
}
@@ -4241,7 +4241,7 @@ static bool lpt_digital_port_connected(struct intel_encoder *encoder)
static bool hsw_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display->hotplug.hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, DEISR) & bit;
}
@@ -4249,7 +4249,7 @@ static bool hsw_digital_port_connected(struct intel_encoder *encoder)
static bool bdw_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display->hotplug.hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 5cd93ca2aaa1..4504f5730712 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1840,14 +1840,14 @@ static const struct file_operations i915_cur_wm_latency_fops = {
static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = m->private;
- struct i915_hotplug *hotplug = &dev_priv->hotplug;
+ struct i915_hotplug *hotplug = &dev_priv->display->hotplug;
/* Synchronize with everything first in case there's been an HPD
* storm, but we haven't finished handling it in the kernel yet
*/
intel_synchronize_irq(dev_priv);
- flush_work(&dev_priv->hotplug.dig_port_work);
- flush_delayed_work(&dev_priv->hotplug.hotplug_work);
+ flush_work(&dev_priv->_display.hotplug.dig_port_work);
+ flush_delayed_work(&dev_priv->_display.hotplug.hotplug_work);
seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
seq_printf(m, "Detected: %s\n",
@@ -1862,7 +1862,7 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
- struct i915_hotplug *hotplug = &dev_priv->hotplug;
+ struct i915_hotplug *hotplug = &dev_priv->display->hotplug;
unsigned int new_threshold;
int i;
char *newline;
@@ -1901,7 +1901,7 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
spin_unlock_irq(&dev_priv->irq_lock);
/* Re-enable hpd immediately if we were in an irq storm */
- flush_delayed_work(&dev_priv->hotplug.reenable_work);
+ flush_delayed_work(&dev_priv->display->hotplug.reenable_work);
return len;
}
@@ -1925,7 +1925,7 @@ static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = m->private;
seq_printf(m, "Enabled: %s\n",
- yesno(dev_priv->hotplug.hpd_short_storm_enabled));
+ yesno(dev_priv->display->hotplug.hpd_short_storm_enabled));
return 0;
}
@@ -1943,7 +1943,7 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
- struct i915_hotplug *hotplug = &dev_priv->hotplug;
+ struct i915_hotplug *hotplug = &dev_priv->display->hotplug;
char *newline;
char tmp[16];
int i;
@@ -1979,7 +1979,7 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
spin_unlock_irq(&dev_priv->irq_lock);
/* Re-enable hpd immediately if we were in an irq storm */
- flush_delayed_work(&dev_priv->hotplug.reenable_work);
+ flush_delayed_work(&dev_priv->display->hotplug.reenable_work);
return len;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 425da9f9c735..ffbca89ff51b 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -118,13 +118,13 @@ intel_connector_hpd_pin(struct intel_connector *connector)
* responsible for further action.
*
* The number of IRQs that are allowed within @HPD_STORM_DETECT_PERIOD is
- * stored in @dev_priv->hotplug.hpd_storm_threshold which defaults to
+ * stored in @dev_priv->display->hotplug.hpd_storm_threshold which defaults to
* @HPD_STORM_DEFAULT_THRESHOLD. Long IRQs count as +10 to this threshold, and
* short IRQs count as +1. If this threshold is exceeded, it's considered an
* IRQ storm and the IRQ state is set to @HPD_MARK_DISABLED.
*
* By default, most systems will only count long IRQs towards
- * &dev_priv->hotplug.hpd_storm_threshold. However, some older systems also
+ * &dev_priv->display->hotplug.hpd_storm_threshold. However, some older systems also
* suffer from short IRQ storms and must also track these. Because short IRQ
* storms are naturally caused by sideband interactions with DP MST devices,
* short IRQ detection is only enabled for systems without DP MST support.
@@ -139,7 +139,7 @@ intel_connector_hpd_pin(struct intel_connector *connector)
static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
enum hpd_pin pin, bool long_hpd)
{
- struct i915_hotplug *hpd = &dev_priv->hotplug;
+ struct i915_hotplug *hpd = &dev_priv->display->hotplug;
unsigned long start = hpd->stats[pin].last_jiffies;
unsigned long end = start + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
const int increment = long_hpd ? 10 : 1;
@@ -147,7 +147,7 @@ static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
bool storm = false;
if (!threshold ||
- (!long_hpd && !dev_priv->hotplug.hpd_short_storm_enabled))
+ (!long_hpd && !dev_priv->display->hotplug.hpd_short_storm_enabled))
return false;
if (!time_in_range(jiffies, start, end)) {
@@ -190,7 +190,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
pin = intel_connector_hpd_pin(connector);
if (pin == HPD_NONE ||
- dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED)
+ dev_priv->display->hotplug.stats[pin].state != HPD_MARK_DISABLED)
continue;
drm_info(&dev_priv->drm,
@@ -198,7 +198,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
"switching from hotplug detection to polling\n",
connector->base.name);
- dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
+ dev_priv->display->hotplug.stats[pin].state = HPD_DISABLED;
connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
DRM_CONNECTOR_POLL_DISCONNECT;
hpd_disabled = true;
@@ -208,7 +208,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
/* Enable polling and queue hotplug re-enabling. */
if (hpd_disabled) {
drm_kms_helper_poll_enable(dev);
- mod_delayed_work(system_wq, &dev_priv->hotplug.reenable_work,
+ mod_delayed_work(system_wq, &dev_priv->display->hotplug.reenable_work,
msecs_to_jiffies(HPD_STORM_REENABLE_DELAY));
}
}
@@ -223,7 +223,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv),
- hotplug.reenable_work.work);
+ _display.hotplug.reenable_work.work);
struct drm_device *dev = &dev_priv->drm;
struct drm_connector_list_iter conn_iter;
struct intel_connector *connector;
@@ -238,7 +238,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
for_each_intel_connector_iter(connector, &conn_iter) {
pin = intel_connector_hpd_pin(connector);
if (pin == HPD_NONE ||
- dev_priv->hotplug.stats[pin].state != HPD_DISABLED)
+ dev_priv->display->hotplug.stats[pin].state != HPD_DISABLED)
continue;
if (connector->base.polled != connector->polled)
@@ -250,8 +250,8 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
drm_connector_list_iter_end(&conn_iter);
for_each_hpd_pin(pin) {
- if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED)
- dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
+ if (dev_priv->display->hotplug.stats[pin].state == HPD_DISABLED)
+ dev_priv->display->hotplug.stats[pin].state = HPD_ENABLED;
}
intel_hpd_irq_setup(dev_priv);
@@ -302,16 +302,17 @@ static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
static void i915_digport_work_func(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, struct drm_i915_private, hotplug.dig_port_work);
+ container_of(work, struct drm_i915_private,
+ _display.hotplug.dig_port_work);
u32 long_port_mask, short_port_mask;
struct intel_encoder *encoder;
u32 old_bits = 0;
spin_lock_irq(&dev_priv->irq_lock);
- long_port_mask = dev_priv->hotplug.long_port_mask;
- dev_priv->hotplug.long_port_mask = 0;
- short_port_mask = dev_priv->hotplug.short_port_mask;
- dev_priv->hotplug.short_port_mask = 0;
+ long_port_mask = dev_priv->display->hotplug.long_port_mask;
+ dev_priv->display->hotplug.long_port_mask = 0;
+ short_port_mask = dev_priv->display->hotplug.short_port_mask;
+ dev_priv->display->hotplug.short_port_mask = 0;
spin_unlock_irq(&dev_priv->irq_lock);
for_each_intel_encoder(&dev_priv->drm, encoder) {
@@ -340,9 +341,9 @@ static void i915_digport_work_func(struct work_struct *work)
if (old_bits) {
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->hotplug.event_bits |= old_bits;
+ dev_priv->display->hotplug.event_bits |= old_bits;
spin_unlock_irq(&dev_priv->irq_lock);
- queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
+ queue_delayed_work(system_wq, &dev_priv->_display.hotplug.hotplug_work, 0);
}
}
@@ -358,10 +359,10 @@ void intel_hpd_trigger_irq(struct intel_digital_port *dig_port)
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
spin_lock_irq(&i915->irq_lock);
- i915->hotplug.short_port_mask |= BIT(dig_port->base.port);
+ i915->display->hotplug.short_port_mask |= BIT(dig_port->base.port);
spin_unlock_irq(&i915->irq_lock);
- queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work);
+ queue_work(i915->display->hotplug.dp_wq, &i915->_display.hotplug.dig_port_work);
}
/*
@@ -371,7 +372,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, struct drm_i915_private,
- hotplug.hotplug_work.work);
+ _display.hotplug.hotplug_work.work);
struct drm_device *dev = &dev_priv->drm;
struct drm_connector_list_iter conn_iter;
struct intel_connector *connector;
@@ -384,10 +385,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
spin_lock_irq(&dev_priv->irq_lock);
- hpd_event_bits = dev_priv->hotplug.event_bits;
- dev_priv->hotplug.event_bits = 0;
- hpd_retry_bits = dev_priv->hotplug.retry_bits;
- dev_priv->hotplug.retry_bits = 0;
+ hpd_event_bits = dev_priv->display->hotplug.event_bits;
+ dev_priv->display->hotplug.event_bits = 0;
+ hpd_retry_bits = dev_priv->display->hotplug.retry_bits;
+ dev_priv->display->hotplug.retry_bits = 0;
/* Enable polling for connectors which had HPD IRQ storms */
intel_hpd_irq_storm_switch_to_polling(dev_priv);
@@ -440,10 +441,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
retry &= ~changed;
if (retry) {
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->hotplug.retry_bits |= retry;
+ dev_priv->display->hotplug.retry_bits |= retry;
spin_unlock_irq(&dev_priv->irq_lock);
- mod_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work,
+ mod_delayed_work(system_wq, &dev_priv->_display.hotplug.hotplug_work,
msecs_to_jiffies(HPD_RETRY_DELAY));
}
}
@@ -507,10 +508,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (long_hpd) {
long_hpd_pulse_mask |= BIT(pin);
- dev_priv->hotplug.long_port_mask |= BIT(port);
+ dev_priv->display->hotplug.long_port_mask |= BIT(port);
} else {
short_hpd_pulse_mask |= BIT(pin);
- dev_priv->hotplug.short_port_mask |= BIT(port);
+ dev_priv->display->hotplug.short_port_mask |= BIT(port);
}
}
@@ -521,7 +522,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (!(BIT(pin) & pin_mask))
continue;
- if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) {
+ if (dev_priv->display->hotplug.stats[pin].state == HPD_DISABLED) {
/*
* On GMCH platforms the interrupt mask bits only
* prevent irq generation, not the setting of the
@@ -534,7 +535,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
continue;
}
- if (dev_priv->hotplug.stats[pin].state != HPD_ENABLED)
+ if (dev_priv->display->hotplug.stats[pin].state != HPD_ENABLED)
continue;
/*
@@ -545,13 +546,13 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
long_hpd = long_hpd_pulse_mask & BIT(pin);
} else {
- dev_priv->hotplug.event_bits |= BIT(pin);
+ dev_priv->display->hotplug.event_bits |= BIT(pin);
long_hpd = true;
queue_hp = true;
}
if (intel_hpd_irq_storm_detect(dev_priv, pin, long_hpd)) {
- dev_priv->hotplug.event_bits &= ~BIT(pin);
+ dev_priv->display->hotplug.event_bits &= ~BIT(pin);
storm_detected = true;
queue_hp = true;
}
@@ -572,9 +573,9 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
* deadlock.
*/
if (queue_dig)
- queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work);
+ queue_work(dev_priv->_display.hotplug.dp_wq, &dev_priv->_display.hotplug.dig_port_work);
if (queue_hp)
- queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
+ queue_delayed_work(system_wq, &dev_priv->_display.hotplug.hotplug_work, 0);
}
/**
@@ -599,8 +600,8 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
return;
for_each_hpd_pin(i) {
- dev_priv->hotplug.stats[i].count = 0;
- dev_priv->hotplug.stats[i].state = HPD_ENABLED;
+ dev_priv->display->hotplug.stats[i].count = 0;
+ dev_priv->display->hotplug.stats[i].state = HPD_ENABLED;
}
/*
@@ -616,7 +617,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, struct drm_i915_private,
- hotplug.poll_init_work);
+ _display.hotplug.poll_init_work);
struct drm_device *dev = &dev_priv->drm;
struct drm_connector_list_iter conn_iter;
struct intel_connector *connector;
@@ -624,7 +625,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
mutex_lock(&dev->mode_config.mutex);
- enabled = READ_ONCE(dev_priv->hotplug.poll_enabled);
+ enabled = READ_ONCE(dev_priv->display->hotplug.poll_enabled);
drm_connector_list_iter_begin(dev, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
@@ -676,7 +677,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- WRITE_ONCE(dev_priv->hotplug.poll_enabled, true);
+ WRITE_ONCE(dev_priv->display->hotplug.poll_enabled, true);
/*
* We might already be holding dev->mode_config.mutex, so do this in a
@@ -684,7 +685,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
* As well, there's no issue if we race here since we always reschedule
* this worker anyway
*/
- schedule_work(&dev_priv->hotplug.poll_init_work);
+ schedule_work(&dev_priv->_display.hotplug.poll_init_work);
}
/**
@@ -711,17 +712,17 @@ void intel_hpd_poll_disable(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- WRITE_ONCE(dev_priv->hotplug.poll_enabled, false);
- schedule_work(&dev_priv->hotplug.poll_init_work);
+ WRITE_ONCE(dev_priv->display->hotplug.poll_enabled, false);
+ schedule_work(&dev_priv->_display.hotplug.poll_init_work);
}
void intel_hpd_init_work(struct drm_i915_private *dev_priv)
{
- INIT_DELAYED_WORK(&dev_priv->hotplug.hotplug_work,
+ INIT_DELAYED_WORK(&dev_priv->_display.hotplug.hotplug_work,
i915_hotplug_work_func);
- INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func);
- INIT_WORK(&dev_priv->hotplug.poll_init_work, i915_hpd_poll_init_work);
- INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work,
+ INIT_WORK(&dev_priv->_display.hotplug.dig_port_work, i915_digport_work_func);
+ INIT_WORK(&dev_priv->_display.hotplug.poll_init_work, i915_hpd_poll_init_work);
+ INIT_DELAYED_WORK(&dev_priv->_display.hotplug.reenable_work,
intel_hpd_irq_storm_reenable_work);
}
@@ -732,17 +733,17 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->hotplug.long_port_mask = 0;
- dev_priv->hotplug.short_port_mask = 0;
- dev_priv->hotplug.event_bits = 0;
- dev_priv->hotplug.retry_bits = 0;
+ dev_priv->display->hotplug.long_port_mask = 0;
+ dev_priv->display->hotplug.short_port_mask = 0;
+ dev_priv->display->hotplug.event_bits = 0;
+ dev_priv->display->hotplug.retry_bits = 0;
spin_unlock_irq(&dev_priv->irq_lock);
- cancel_work_sync(&dev_priv->hotplug.dig_port_work);
- cancel_delayed_work_sync(&dev_priv->hotplug.hotplug_work);
- cancel_work_sync(&dev_priv->hotplug.poll_init_work);
- cancel_delayed_work_sync(&dev_priv->hotplug.reenable_work);
+ cancel_work_sync(&dev_priv->_display.hotplug.dig_port_work);
+ cancel_delayed_work_sync(&dev_priv->_display.hotplug.hotplug_work);
+ cancel_work_sync(&dev_priv->_display.hotplug.poll_init_work);
+ cancel_delayed_work_sync(&dev_priv->_display.hotplug.reenable_work);
}
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
@@ -753,8 +754,8 @@ bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
return false;
spin_lock_irq(&dev_priv->irq_lock);
- if (dev_priv->hotplug.stats[pin].state == HPD_ENABLED) {
- dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
+ if (dev_priv->display->hotplug.stats[pin].state == HPD_ENABLED) {
+ dev_priv->display->hotplug.stats[pin].state = HPD_DISABLED;
ret = true;
}
spin_unlock_irq(&dev_priv->irq_lock);
@@ -768,6 +769,6 @@ void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
return;
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
+ dev_priv->display->hotplug.stats[pin].state = HPD_ENABLED;
spin_unlock_irq(&dev_priv->irq_lock);
}
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 3ffece568ed9..a3b3136059a6 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -207,7 +207,7 @@ static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
- u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
+ u32 isr_bit = i915->display->hotplug.pch_hpd[dig_port->base.hpd_pin];
u32 mask = 0;
u32 val;
@@ -240,7 +240,7 @@ static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
- u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
+ u32 isr_bit = i915->display->hotplug.pch_hpd[dig_port->base.hpd_pin];
struct intel_uncore *uncore = &i915->uncore;
u32 val, mask = 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ddc183b7711c..8878bfcee0ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -236,8 +236,8 @@ static int i915_workqueues_init(struct drm_i915_private *dev_priv)
if (dev_priv->wq == NULL)
goto out_err;
- dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
- if (dev_priv->hotplug.dp_wq == NULL)
+ dev_priv->display->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
+ if (dev_priv->display->hotplug.dp_wq == NULL)
goto out_free_wq;
return 0;
@@ -252,7 +252,7 @@ static int i915_workqueues_init(struct drm_i915_private *dev_priv)
static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
{
- destroy_workqueue(dev_priv->hotplug.dp_wq);
+ destroy_workqueue(dev_priv->display->hotplug.dp_wq);
destroy_workqueue(dev_priv->wq);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3f9bebb8478f..25a17808dcee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -899,6 +899,8 @@ struct drm_i915_display {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+
+ struct i915_hotplug hotplug;
};
struct drm_i915_private {
@@ -972,7 +974,6 @@ struct drm_i915_private {
};
u32 pipestat_irq_mask[I915_MAX_PIPES];
- struct i915_hotplug hotplug;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dcc404ca919f..260024445d68 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -181,7 +181,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
{
- struct i915_hotplug *hpd = &dev_priv->hotplug;
+ struct i915_hotplug *hpd = &dev_priv->display->hotplug;
if (HAS_GMCH(dev_priv)) {
if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
@@ -1271,7 +1271,7 @@ static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
u32 enabled_irqs = 0;
for_each_intel_encoder(&dev_priv->drm, encoder)
- if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
+ if (dev_priv->display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
enabled_irqs |= hpd[encoder->hpd_pin];
return enabled_irqs;
@@ -1636,7 +1636,7 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (hotplug_trigger) {
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, hotplug_trigger,
- dev_priv->hotplug.hpd,
+ dev_priv->display->hotplug.hpd,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -1840,7 +1840,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.pch_hpd,
+ dev_priv->display->hotplug.pch_hpd,
pch_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -1985,7 +1985,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
ddi_hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.pch_hpd,
+ dev_priv->display->hotplug.pch_hpd,
icp_ddi_port_hotplug_long_detect);
}
@@ -1997,7 +1997,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
tc_hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.pch_hpd,
+ dev_priv->display->hotplug.pch_hpd,
icp_tc_port_hotplug_long_detect);
}
@@ -2023,7 +2023,7 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.pch_hpd,
+ dev_priv->display->hotplug.pch_hpd,
spt_port_hotplug_long_detect);
}
@@ -2035,7 +2035,7 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug2_trigger, dig_hotplug_reg,
- dev_priv->hotplug.pch_hpd,
+ dev_priv->display->hotplug.pch_hpd,
spt_port_hotplug2_long_detect);
}
@@ -2056,7 +2056,7 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.hpd,
+ dev_priv->display->hotplug.hpd,
ilk_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -2236,7 +2236,7 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.hpd,
+ dev_priv->display->hotplug.hpd,
bxt_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -2256,7 +2256,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
trigger_tc, dig_hotplug_reg,
- dev_priv->hotplug.hpd,
+ dev_priv->display->hotplug.hpd,
gen11_port_hotplug_long_detect);
}
@@ -2268,7 +2268,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
trigger_tbt, dig_hotplug_reg,
- dev_priv->hotplug.hpd,
+ dev_priv->display->hotplug.hpd,
gen11_port_hotplug_long_detect);
}
@@ -3310,8 +3310,8 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display->hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display->hotplug.pch_hpd);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
@@ -3380,8 +3380,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display->hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display->hotplug.pch_hpd);
if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
@@ -3457,8 +3457,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
u32 hotplug_irqs, enabled_irqs;
u32 val;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display->hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display->hotplug.hpd);
val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
val &= ~hotplug_irqs;
@@ -3535,8 +3535,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display->hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display->hotplug.pch_hpd);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
@@ -3575,8 +3575,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display->hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display->hotplug.hpd);
if (DISPLAY_VER(dev_priv) >= 8)
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
@@ -3633,8 +3633,8 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display->hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display->hotplug.hpd);
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
@@ -4384,14 +4384,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
dev_priv->display_irqs_enabled = false;
- dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
+ dev_priv->display->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
/* If we have MST support, we want to avoid doing short HPD IRQ storm
* detection, as short HPD storms will occur as a natural part of
* sideband messaging with MST.
* On older platforms however, IRQ storms can occur with both long and
* short pulses, as seen on some G4x systems.
*/
- dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
+ dev_priv->display->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 16/25] drm/i915/display: move overlay into display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (14 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 15/25] drm/i915/display: move hotplug struct to " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 17/25] drm/i915/display: move fbdev info to " Dave Airlie
` (11 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_overlay.c | 12 ++++++------
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 7e3f5c6ca484..5e8c273cf318 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -485,7 +485,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
void intel_overlay_reset(struct drm_i915_private *dev_priv)
{
- struct intel_overlay *overlay = dev_priv->overlay;
+ struct intel_overlay *overlay = dev_priv->display->overlay;
if (!overlay)
return;
@@ -1106,7 +1106,7 @@ int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
struct drm_i915_gem_object *new_bo;
int ret;
- overlay = dev_priv->overlay;
+ overlay = dev_priv->display->overlay;
if (!overlay) {
drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
return -ENODEV;
@@ -1266,7 +1266,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
struct intel_overlay *overlay;
int ret;
- overlay = dev_priv->overlay;
+ overlay = dev_priv->display->overlay;
if (!overlay) {
drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
return -ENODEV;
@@ -1411,7 +1411,7 @@ void intel_overlay_setup(struct drm_i915_private *dev_priv)
update_polyphase_filter(overlay->regs);
update_reg_attrs(overlay, overlay->regs);
- dev_priv->overlay = overlay;
+ dev_priv->display->overlay = overlay;
drm_info(&dev_priv->drm, "Initialized overlay support.\n");
return;
@@ -1423,7 +1423,7 @@ void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
{
struct intel_overlay *overlay;
- overlay = fetch_and_zero(&dev_priv->overlay);
+ overlay = fetch_and_zero(&dev_priv->display->overlay);
if (!overlay)
return;
@@ -1452,7 +1452,7 @@ struct intel_overlay_error_state {
struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
{
- struct intel_overlay *overlay = dev_priv->overlay;
+ struct intel_overlay *overlay = dev_priv->display->overlay;
struct intel_overlay_error_state *error;
if (!overlay || !overlay->active)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 25a17808dcee..19be9b84cb19 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -901,6 +901,9 @@ struct drm_i915_display {
struct mutex hdcp_comp_mutex;
struct i915_hotplug hotplug;
+
+ /* overlay */
+ struct intel_overlay *overlay;
};
struct drm_i915_private {
@@ -979,9 +982,6 @@ struct drm_i915_private {
bool preserve_bios_swizzle;
- /* overlay */
- struct intel_overlay *overlay;
-
/* backlight registers and fields in struct intel_panel */
struct mutex backlight_lock;
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 77490cb5ff9c..7ee387203a16 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -34,7 +34,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = i915->ggtt.num_fences;
break;
case I915_PARAM_HAS_OVERLAY:
- value = !!i915->overlay;
+ value = !!i915->display->overlay;
break;
case I915_PARAM_HAS_BSD:
value = !!intel_engine_lookup_user(i915,
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 17/25] drm/i915/display: move fbdev info to display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (15 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 16/25] drm/i915/display: move overlay into " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 18/25] drm/i915/display: move fb_tracking " Dave Airlie
` (10 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/i915/display/intel_display_debugfs.c | 4 +--
drivers/gpu/drm/i915/display/intel_fbdev.c | 26 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 8 +++---
3 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 4504f5730712..1d38007106d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -201,8 +201,8 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
struct drm_framebuffer *drm_fb;
#ifdef CONFIG_DRM_FBDEV_EMULATION
- if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) {
- fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
+ if (dev_priv->display->fbdev && dev_priv->display->fbdev->helper.fb) {
+ fbdev_fb = to_intel_framebuffer(dev_priv->display->fbdev->helper.fb);
seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
fbdev_fb->base.width,
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 60d3ded27047..8af2b3088af4 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -484,7 +484,7 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
{
intel_fbdev_set_suspend(&container_of(work,
struct drm_i915_private,
- fbdev_suspend_work)->drm,
+ _display.fbdev_suspend_work)->drm,
FBINFO_STATE_RUNNING,
true);
}
@@ -514,8 +514,8 @@ int intel_fbdev_init(struct drm_device *dev)
return ret;
}
- dev_priv->fbdev = ifbdev;
- INIT_WORK(&dev_priv->fbdev_suspend_work, intel_fbdev_suspend_worker);
+ dev_priv->display->fbdev = ifbdev;
+ INIT_WORK(&dev_priv->display->fbdev_suspend_work, intel_fbdev_suspend_worker);
return 0;
}
@@ -532,7 +532,7 @@ static void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
void intel_fbdev_initial_config_async(struct drm_device *dev)
{
- struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
+ struct intel_fbdev *ifbdev = to_i915(dev)->display->fbdev;
if (!ifbdev)
return;
@@ -552,12 +552,12 @@ static void intel_fbdev_sync(struct intel_fbdev *ifbdev)
void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
{
- struct intel_fbdev *ifbdev = dev_priv->fbdev;
+ struct intel_fbdev *ifbdev = dev_priv->display->fbdev;
if (!ifbdev)
return;
- cancel_work_sync(&dev_priv->fbdev_suspend_work);
+ cancel_work_sync(&dev_priv->display->fbdev_suspend_work);
if (!current_is_async())
intel_fbdev_sync(ifbdev);
@@ -566,7 +566,7 @@ void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
void intel_fbdev_fini(struct drm_i915_private *dev_priv)
{
- struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->fbdev);
+ struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->display->fbdev);
if (!ifbdev)
return;
@@ -580,7 +580,7 @@ void intel_fbdev_fini(struct drm_i915_private *dev_priv)
*/
static void intel_fbdev_hpd_set_suspend(struct drm_i915_private *i915, int state)
{
- struct intel_fbdev *ifbdev = i915->fbdev;
+ struct intel_fbdev *ifbdev = i915->display->fbdev;
bool send_hpd = false;
mutex_lock(&ifbdev->hpd_lock);
@@ -598,7 +598,7 @@ static void intel_fbdev_hpd_set_suspend(struct drm_i915_private *i915, int state
void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_fbdev *ifbdev = dev_priv->fbdev;
+ struct intel_fbdev *ifbdev = dev_priv->display->fbdev;
struct fb_info *info;
if (!ifbdev || !ifbdev->vma)
@@ -615,7 +615,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
* ourselves, so only flush outstanding work upon suspend!
*/
if (state != FBINFO_STATE_RUNNING)
- flush_work(&dev_priv->fbdev_suspend_work);
+ flush_work(&dev_priv->display->fbdev_suspend_work);
console_lock();
} else {
@@ -629,7 +629,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
/* Don't block our own workqueue as this can
* be run in parallel with other i915.ko tasks.
*/
- schedule_work(&dev_priv->fbdev_suspend_work);
+ schedule_work(&dev_priv->display->fbdev_suspend_work);
return;
}
}
@@ -650,7 +650,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
void intel_fbdev_output_poll_changed(struct drm_device *dev)
{
- struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
+ struct intel_fbdev *ifbdev = to_i915(dev)->display->fbdev;
bool send_hpd;
if (!ifbdev)
@@ -669,7 +669,7 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev)
void intel_fbdev_restore_mode(struct drm_device *dev)
{
- struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
+ struct intel_fbdev *ifbdev = to_i915(dev)->display->fbdev;
if (!ifbdev)
return;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 19be9b84cb19..5eaa06c98244 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -904,6 +904,10 @@ struct drm_i915_display {
/* overlay */
struct intel_overlay *overlay;
+
+ /* list of fbdev register on this device */
+ struct intel_fbdev *fbdev;
+ struct work_struct fbdev_suspend_work;
};
struct drm_i915_private {
@@ -1080,10 +1084,6 @@ struct drm_i915_private {
struct drm_i915_gem_object *vlv_pctx;
- /* list of fbdev register on this device */
- struct intel_fbdev *fbdev;
- struct work_struct fbdev_suspend_work;
-
u32 fdi_rx_config;
/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 18/25] drm/i915/display: move fb_tracking to display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (16 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 17/25] drm/i915/display: move fbdev info to " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 19/25] drm/i915/display: move delay and pch values " Dave Airlie
` (9 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
the spinlock init in gem code seems wildly out of place
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../gpu/drm/i915/display/intel_frontbuffer.c | 54 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
4 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 1d38007106d9..784ce209add9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -32,10 +32,10 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
seq_printf(m, "FB tracking busy bits: 0x%08x\n",
- dev_priv->fb_tracking.busy_bits);
+ dev_priv->display->fb_tracking.busy_bits);
seq_printf(m, "FB tracking flip bits: 0x%08x\n",
- dev_priv->fb_tracking.flip_bits);
+ dev_priv->display->fb_tracking.flip_bits);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 0492446cd04a..1d9f86de3c91 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -82,9 +82,9 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
enum fb_op_origin origin)
{
/* Delay flushing when rings are still busy.*/
- spin_lock(&i915->fb_tracking.lock);
- frontbuffer_bits &= ~i915->fb_tracking.busy_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display->fb_tracking.lock);
+ frontbuffer_bits &= ~i915->display->fb_tracking.busy_bits;
+ spin_unlock(&i915->display->fb_tracking.lock);
if (!frontbuffer_bits)
return;
@@ -112,11 +112,11 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
- i915->fb_tracking.flip_bits |= frontbuffer_bits;
+ spin_lock(&i915->display->fb_tracking.lock);
+ i915->display->fb_tracking.flip_bits |= frontbuffer_bits;
/* Remove stale busy bits due to the old buffer. */
- i915->fb_tracking.busy_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ i915->display->fb_tracking.busy_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display->fb_tracking.lock);
}
/**
@@ -132,11 +132,11 @@ void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915,
void intel_frontbuffer_flip_complete(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display->fb_tracking.lock);
/* Mask any cancelled flips. */
- frontbuffer_bits &= i915->fb_tracking.flip_bits;
- i915->fb_tracking.flip_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ frontbuffer_bits &= i915->display->fb_tracking.flip_bits;
+ i915->display->fb_tracking.flip_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display->fb_tracking.lock);
if (frontbuffer_bits)
frontbuffer_flush(i915, frontbuffer_bits, ORIGIN_FLIP);
@@ -156,10 +156,10 @@ void intel_frontbuffer_flip_complete(struct drm_i915_private *i915,
void intel_frontbuffer_flip(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display->fb_tracking.lock);
/* Remove stale busy bits due to the old buffer. */
- i915->fb_tracking.busy_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ i915->display->fb_tracking.busy_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display->fb_tracking.lock);
frontbuffer_flush(i915, frontbuffer_bits, ORIGIN_FLIP);
}
@@ -171,10 +171,10 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front,
struct drm_i915_private *i915 = to_i915(front->obj->base.dev);
if (origin == ORIGIN_CS) {
- spin_lock(&i915->fb_tracking.lock);
- i915->fb_tracking.busy_bits |= frontbuffer_bits;
- i915->fb_tracking.flip_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display->fb_tracking.lock);
+ i915->display->fb_tracking.busy_bits |= frontbuffer_bits;
+ i915->display->fb_tracking.flip_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display->fb_tracking.lock);
}
trace_intel_frontbuffer_invalidate(frontbuffer_bits, origin);
@@ -192,11 +192,11 @@ void __intel_fb_flush(struct intel_frontbuffer *front,
struct drm_i915_private *i915 = to_i915(front->obj->base.dev);
if (origin == ORIGIN_CS) {
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display->fb_tracking.lock);
/* Filter out new bits since rendering started. */
- frontbuffer_bits &= i915->fb_tracking.busy_bits;
- i915->fb_tracking.busy_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ frontbuffer_bits &= i915->display->fb_tracking.busy_bits;
+ i915->display->fb_tracking.busy_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display->fb_tracking.lock);
}
if (frontbuffer_bits)
@@ -222,7 +222,7 @@ static void frontbuffer_retire(struct i915_active *ref)
}
static void frontbuffer_release(struct kref *ref)
- __releases(&to_i915(front->obj->base.dev)->fb_tracking.lock)
+ __releases(&to_i915(front->obj->base.dev)->display->fb_tracking.lock)
{
struct intel_frontbuffer *front =
container_of(ref, typeof(*front), ref);
@@ -239,7 +239,7 @@ static void frontbuffer_release(struct kref *ref)
spin_unlock(&obj->vma.lock);
RCU_INIT_POINTER(obj->frontbuffer, NULL);
- spin_unlock(&to_i915(obj->base.dev)->fb_tracking.lock);
+ spin_unlock(&to_i915(obj->base.dev)->display->fb_tracking.lock);
i915_active_fini(&front->write);
@@ -269,7 +269,7 @@ intel_frontbuffer_get(struct drm_i915_gem_object *obj)
frontbuffer_retire,
I915_ACTIVE_RETIRE_SLEEPS);
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display->fb_tracking.lock);
if (rcu_access_pointer(obj->frontbuffer)) {
kfree(front);
front = rcu_dereference_protected(obj->frontbuffer, true);
@@ -278,7 +278,7 @@ intel_frontbuffer_get(struct drm_i915_gem_object *obj)
i915_gem_object_get(obj);
rcu_assign_pointer(obj->frontbuffer, front);
}
- spin_unlock(&i915->fb_tracking.lock);
+ spin_unlock(&i915->display->fb_tracking.lock);
return front;
}
@@ -287,7 +287,7 @@ void intel_frontbuffer_put(struct intel_frontbuffer *front)
{
kref_put_lock(&front->ref,
frontbuffer_release,
- &to_i915(front->obj->base.dev)->fb_tracking.lock);
+ &to_i915(front->obj->base.dev)->display->fb_tracking.lock);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5eaa06c98244..a487686b1b71 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -908,6 +908,8 @@ struct drm_i915_display {
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
struct work_struct fbdev_suspend_work;
+
+ struct i915_frontbuffer_tracking fb_tracking;
};
struct drm_i915_private {
@@ -1053,8 +1055,6 @@ struct drm_i915_private {
struct i915_wa_list gt_wa_list;
- struct i915_frontbuffer_tracking fb_tracking;
-
struct intel_atomic_helper {
struct llist_head free_list;
struct work_struct free_work;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 590efc8b0265..f01607461678 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1165,7 +1165,7 @@ void i915_gem_init_early(struct drm_i915_private *dev_priv)
i915_gem_init__mm(dev_priv);
i915_gem_init__contexts(dev_priv);
- spin_lock_init(&dev_priv->fb_tracking.lock);
+ spin_lock_init(&dev_priv->display->fb_tracking.lock);
}
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 19/25] drm/i915/display: move delay and pch values to display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (17 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 18/25] drm/i915/display: move fb_tracking " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 20/25] drm/intel/display: move atomic related things to display Dave Airlie
` (8 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +--
drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++--
drivers/gpu/drm/i915/i915_drv.h | 14 ++++----
4 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 60ef938aed0e..7a4100a58b48 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -632,7 +632,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
/* Configure frame start delay to match the CPU */
val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
- val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
intel_de_write(dev_priv, reg, val);
}
@@ -643,7 +643,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
if (HAS_PCH_IBX(dev_priv)) {
/* Configure frame start delay to match the CPU */
val &= ~TRANS_FRAME_START_DELAY_MASK;
- val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ val |= TRANS_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
/*
* Make the BPC in transcoder be consistent with
@@ -688,7 +688,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
/* Configure frame start delay to match the CPU */
val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
- val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
val = TRANS_ENABLE;
@@ -2991,7 +2991,7 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
val = intel_de_read(dev_priv, reg);
val &= ~HSW_FRAME_START_DELAY_MASK;
- val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ val |= HSW_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
intel_de_write(dev_priv, reg, val);
}
@@ -4463,7 +4463,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
- pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ pipeconf |= PIPECONF_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
@@ -5096,24 +5096,24 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
* clock hierarchy. That would also allow us to do
* clock bending finally.
*/
- dev_priv->pch_ssc_use = 0;
+ dev_priv->display->pch_ssc_use = 0;
if (spll_uses_pch_ssc(dev_priv)) {
drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
- dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
+ dev_priv->display->pch_ssc_use |= BIT(DPLL_ID_SPLL);
}
if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
- dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
+ dev_priv->display->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
}
if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
- dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
+ dev_priv->display->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
}
- if (dev_priv->pch_ssc_use)
+ if (dev_priv->display->pch_ssc_use)
return;
if (has_fdi) {
@@ -5186,7 +5186,7 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
- val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ val |= PIPECONF_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
intel_de_write(dev_priv, PIPECONF(pipe), val);
intel_de_posting_read(dev_priv, PIPECONF(pipe));
@@ -11573,9 +11573,9 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
- i915->framestart_delay = 1; /* 1-4 */
+ i915->display->framestart_delay = 1; /* 1-4 */
- i915->window2_delay = 0; /* No DSB so no window2 delay */
+ i915->display->window2_delay = 0; /* No DSB so no window2 delay */
intel_mode_config_init(i915);
@@ -11915,7 +11915,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
val = intel_de_read(dev_priv, reg);
val &= ~HSW_FRAME_START_DELAY_MASK;
- val |= HSW_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ val |= HSW_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
intel_de_write(dev_priv, reg, val);
} else {
i915_reg_t reg = PIPECONF(cpu_transcoder);
@@ -11923,7 +11923,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
val = intel_de_read(dev_priv, reg);
val &= ~PIPECONF_FRAME_START_DELAY_MASK;
- val |= PIPECONF_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ val |= PIPECONF_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
intel_de_write(dev_priv, reg, val);
}
@@ -11936,7 +11936,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
val = intel_de_read(dev_priv, reg);
val &= ~TRANS_FRAME_START_DELAY_MASK;
- val |= TRANS_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ val |= TRANS_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
intel_de_write(dev_priv, reg, val);
} else {
enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
@@ -11945,7 +11945,7 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
val = intel_de_read(dev_priv, reg);
val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
- val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->framestart_delay - 1);
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(dev_priv->display->framestart_delay - 1);
intel_de_write(dev_priv, reg, val);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 11fefa6de27e..47036316fbf9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -574,7 +574,7 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
* Try to set up the PCH reference clock once all DPLLs
* that depend on it have been shut down.
*/
- if (dev_priv->pch_ssc_use & BIT(id))
+ if (dev_priv->display->pch_ssc_use & BIT(id))
intel_init_pch_refclk(dev_priv);
}
@@ -592,7 +592,7 @@ static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
* Try to set up the PCH reference clock once all DPLLs
* that depend on it have been shut down.
*/
- if (dev_priv->pch_ssc_use & BIT(id))
+ if (dev_priv->display->pch_ssc_use & BIT(id))
intel_init_pch_refclk(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c335b1dbafcf..ce4419ee11f2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -69,9 +69,9 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
/* The hw imposes the extra scanline before frame start */
if (DISPLAY_VER(i915) >= 13)
- return crtc_state->vrr.guardband + i915->framestart_delay + 1;
+ return crtc_state->vrr.guardband + i915->display->framestart_delay + 1;
else
- return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
+ return crtc_state->vrr.pipeline_full + i915->display->framestart_delay + 1;
}
int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
@@ -135,7 +135,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
if (DISPLAY_VER(i915) >= 13)
crtc_state->vrr.guardband =
crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
- i915->window2_delay;
+ i915->display->window2_delay;
else
/*
* FIXME: s/4/framestart_delay+1/ to get consistent
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a487686b1b71..6eba551396fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -848,6 +848,13 @@ struct drm_i915_display {
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
+ u8 framestart_delay;
+
+ /* Window2 specifies time required to program DSB (Window2) in number of scan lines */
+ u8 window2_delay;
+
+ u8 pch_ssc_use;
+
/**
* Base address of where the gmbus and gpio blocks are located (either
* on PCH or on SoC for platforms without PCH).
@@ -1199,13 +1206,6 @@ struct drm_i915_private {
struct file *mmap_singleton;
} gem;
- u8 framestart_delay;
-
- /* Window2 specifies time required to program DSB (Window2) in number of scan lines */
- u8 window2_delay;
-
- u8 pch_ssc_use;
-
/* For i915gm/i945gm vblank irq workaround */
u8 vblank_enabled;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 20/25] drm/intel/display: move atomic related things to display
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (18 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 19/25] drm/i915/display: move delay and pch values " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 21/25] drm/i915/display: move a bunch of platform misc regs " Dave Airlie
` (7 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 16 +++++------
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7a4100a58b48..117c2ad9d266 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1661,7 +1661,7 @@ static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
- struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
+ struct drm_modeset_acquire_ctx *ctx = &dev_priv->display->reset_ctx;
struct drm_atomic_state *state;
int ret;
@@ -1717,14 +1717,14 @@ void intel_display_prepare_reset(struct drm_i915_private *dev_priv)
return;
}
- dev_priv->modeset_restore_state = state;
+ dev_priv->display->modeset_restore_state = state;
state->acquire_ctx = ctx;
}
void intel_display_finish_reset(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
- struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
+ struct drm_modeset_acquire_ctx *ctx = &dev_priv->display->reset_ctx;
struct drm_atomic_state *state;
int ret;
@@ -1735,7 +1735,7 @@ void intel_display_finish_reset(struct drm_i915_private *dev_priv)
if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
return;
- state = fetch_and_zero(&dev_priv->modeset_restore_state);
+ state = fetch_and_zero(&dev_priv->display->modeset_restore_state);
if (!state)
goto unlock;
@@ -3753,7 +3753,7 @@ int intel_display_suspend(struct drm_device *dev)
drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",
ret);
else
- dev_priv->modeset_restore_state = state;
+ dev_priv->display->modeset_restore_state = state;
return ret;
}
@@ -10033,7 +10033,7 @@ static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
struct intel_atomic_state *state, *next;
struct llist_node *freed;
- freed = llist_del_all(&dev_priv->atomic_helper.free_list);
+ freed = llist_del_all(&dev_priv->display->atomic_helper.free_list);
llist_for_each_entry_safe(state, next, freed, freed)
drm_atomic_state_put(&state->base);
}
@@ -10041,7 +10041,7 @@ static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
static void intel_atomic_helper_free_state_worker(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), atomic_helper.free_work);
+ container_of(work, typeof(*dev_priv), _display.atomic_helper.free_work);
intel_atomic_helper_free_state(dev_priv);
}
@@ -10335,7 +10335,7 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence,
case FENCE_FREE:
{
struct intel_atomic_helper *helper =
- &to_i915(state->base.dev)->atomic_helper;
+ &to_i915(state->base.dev)->display->atomic_helper;
if (llist_add(&state->freed, &helper->free_list))
schedule_work(&helper->free_work);
@@ -11591,8 +11591,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
- init_llist_head(&i915->atomic_helper.free_list);
- INIT_WORK(&i915->atomic_helper.free_work,
+ init_llist_head(&i915->display->atomic_helper.free_list);
+ INIT_WORK(&i915->display->atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
intel_init_quirks(i915);
@@ -12568,14 +12568,14 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
void intel_display_resume(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_atomic_state *state = dev_priv->modeset_restore_state;
+ struct drm_atomic_state *state = dev_priv->display->modeset_restore_state;
struct drm_modeset_acquire_ctx ctx;
int ret;
if (!HAS_DISPLAY(dev_priv))
return;
- dev_priv->modeset_restore_state = NULL;
+ dev_priv->display->modeset_restore_state = NULL;
if (state)
state->acquire_ctx = &ctx;
@@ -12630,8 +12630,8 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
flush_workqueue(i915->flip_wq);
flush_workqueue(i915->modeset_wq);
- flush_work(&i915->atomic_helper.free_work);
- drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
+ flush_work(&i915->display->atomic_helper.free_work);
+ drm_WARN_ON(&i915->drm, !llist_empty(&i915->display->atomic_helper.free_list));
}
/* part #2: call after irq uninstall */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6eba551396fc..550efc29b54f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -917,6 +917,14 @@ struct drm_i915_display {
struct work_struct fbdev_suspend_work;
struct i915_frontbuffer_tracking fb_tracking;
+
+ struct drm_atomic_state *modeset_restore_state;
+ struct drm_modeset_acquire_ctx reset_ctx;
+
+ struct intel_atomic_helper {
+ struct llist_head free_list;
+ struct work_struct free_work;
+ } atomic_helper;
};
struct drm_i915_private {
@@ -1030,9 +1038,6 @@ struct drm_i915_private {
unsigned long quirks;
- struct drm_atomic_state *modeset_restore_state;
- struct drm_modeset_acquire_ctx reset_ctx;
-
struct i915_ggtt ggtt; /* VM representing the global address space */
struct i915_gem_mm mm;
@@ -1062,11 +1067,6 @@ struct drm_i915_private {
struct i915_wa_list gt_wa_list;
- struct intel_atomic_helper {
- struct llist_head free_list;
- struct work_struct free_work;
- } atomic_helper;
-
bool mchbar_need_disable;
struct intel_l3_parity l3_parity;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 21/25] drm/i915/display: move a bunch of platform misc regs to display
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (19 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 20/25] drm/intel/display: move atomic related things to display Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 22/25] drm/i915/display: move dpll struct into display Dave Airlie
` (6 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../drm/i915/display/intel_display_power.c | 76 +++++++++----------
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 6 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 42 +++++-----
7 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c9567b1dcb71..73c7f8e3ea3b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4324,8 +4324,8 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port)
static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
{
- return i915->hti_state & HDPORT_ENABLED &&
- i915->hti_state & HDPORT_DDI_USED(phy);
+ return i915->display->hti_state & HDPORT_ENABLED &&
+ i915->display->hti_state & HDPORT_DDI_USED(phy);
}
static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 117c2ad9d266..606242b876b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4671,7 +4671,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
if (DISPLAY_VER(dev_priv) >= 4) {
/* No way to read it out on pipes B and C */
if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
- tmp = dev_priv->chv_dpll_md[crtc->pipe];
+ tmp = dev_priv->display->chv_dpll_md[crtc->pipe];
else
tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
pipe_config->pixel_multiplier =
@@ -11660,7 +11660,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
* any display resources before we create our display outputs.
*/
if (INTEL_INFO(i915)->display.has_hti)
- i915->hti_state = intel_de_read(i915, HDPORT_STATE);
+ i915->display->hti_state = intel_de_read(i915, HDPORT_STATE);
/* Just disable it once at startup */
intel_vga_disable(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d1db420a8819..7ea86d2cf74a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1531,7 +1531,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
- u32 phy_control = dev_priv->chv_phy_control;
+ u32 phy_control = dev_priv->display->chv_phy_control;
u32 phy_status = 0;
u32 phy_status_mask = 0xffffffff;
@@ -1542,7 +1542,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
* reset (ie. the power well has been disabled at
* least once).
*/
- if (!dev_priv->chv_phy_assert[DPIO_PHY0])
+ if (!dev_priv->display->chv_phy_assert[DPIO_PHY0])
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
@@ -1550,7 +1550,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
- if (!dev_priv->chv_phy_assert[DPIO_PHY1])
+ if (!dev_priv->display->chv_phy_assert[DPIO_PHY1])
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
@@ -1626,7 +1626,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
drm_err(&dev_priv->drm,
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
- phy_status, dev_priv->chv_phy_control);
+ phy_status, dev_priv->display->chv_phy_control);
}
#undef BITS_SET
@@ -1685,13 +1685,13 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
vlv_dpio_put(dev_priv);
- dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
+ dev_priv->display->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display->chv_phy_control);
drm_dbg_kms(&dev_priv->drm,
"Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->chv_phy_control);
+ phy, dev_priv->display->chv_phy_control);
assert_chv_phy_status(dev_priv);
}
@@ -1714,18 +1714,18 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
assert_pll_disabled(dev_priv, PIPE_C);
}
- dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
+ dev_priv->display->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display->chv_phy_control);
vlv_set_power_well(dev_priv, power_well, false);
drm_dbg_kms(&dev_priv->drm,
"Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->chv_phy_control);
+ phy, dev_priv->display->chv_phy_control);
/* PHY is fully reset now, so we can enable the PHY state asserts */
- dev_priv->chv_phy_assert[phy] = true;
+ dev_priv->display->chv_phy_assert[phy] = true;
assert_chv_phy_status(dev_priv);
}
@@ -1743,7 +1743,7 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
* reset (ie. the power well has been disabled at
* least once).
*/
- if (!dev_priv->chv_phy_assert[phy])
+ if (!dev_priv->display->chv_phy_assert[phy])
return;
if (ch == DPIO_CH0)
@@ -1802,22 +1802,22 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
mutex_lock(&power_domains->lock);
- was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ was_override = dev_priv->display->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
if (override == was_override)
goto out;
if (override)
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
else
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display->chv_phy_control);
drm_dbg_kms(&dev_priv->drm,
"Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
- phy, ch, dev_priv->chv_phy_control);
+ phy, ch, dev_priv->display->chv_phy_control);
assert_chv_phy_status(dev_priv);
@@ -1837,20 +1837,20 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
mutex_lock(&power_domains->lock);
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
+ dev_priv->display->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
+ dev_priv->display->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
if (override)
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
else
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display->chv_phy_control);
drm_dbg_kms(&dev_priv->drm,
"Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
- phy, ch, mask, dev_priv->chv_phy_control);
+ phy, ch, mask, dev_priv->display->chv_phy_control);
assert_chv_phy_status(dev_priv);
@@ -1928,7 +1928,7 @@ static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display->chv_phy_control);
}
static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
@@ -5885,7 +5885,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* power well state and lane status to reconstruct the
* expected initial value.
*/
- dev_priv->chv_phy_control =
+ dev_priv->display->chv_phy_control =
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
@@ -5907,27 +5907,27 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->chv_phy_control |=
+ dev_priv->display->chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
- dev_priv->chv_phy_control |=
+ dev_priv->display->chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
mask = (status & DPLL_PORTC_READY_MASK) >> 4;
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->chv_phy_control |=
+ dev_priv->display->chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
- dev_priv->chv_phy_control |=
+ dev_priv->display->chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
- dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
+ dev_priv->display->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
- dev_priv->chv_phy_assert[DPIO_PHY0] = false;
+ dev_priv->display->chv_phy_assert[DPIO_PHY0] = false;
} else {
- dev_priv->chv_phy_assert[DPIO_PHY0] = true;
+ dev_priv->display->chv_phy_assert[DPIO_PHY0] = true;
}
if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) {
@@ -5939,21 +5939,21 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->chv_phy_control |=
+ dev_priv->display->chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
- dev_priv->chv_phy_control |=
+ dev_priv->display->chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
- dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
+ dev_priv->display->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
- dev_priv->chv_phy_assert[DPIO_PHY1] = false;
+ dev_priv->display->chv_phy_assert[DPIO_PHY1] = false;
} else {
- dev_priv->chv_phy_assert[DPIO_PHY1] = true;
+ dev_priv->display->chv_phy_assert[DPIO_PHY1] = true;
}
drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n",
- dev_priv->chv_phy_control);
+ dev_priv->display->chv_phy_control);
/* Defer application of initial phy_control to enabling the powerwell */
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 48507ed79950..6e1ae5eadacd 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -365,7 +365,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
/* Still read out the GRC value for state verification */
if (phy_info->rcomp_phy != -1)
- dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
+ dev_priv->display->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
@@ -431,7 +431,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
* the corresponding calibrated value from PHY1, and disable
* the automatic calibration on PHY0.
*/
- val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
+ val = dev_priv->display->bxt_phy_grc = bxt_get_grc(dev_priv,
phy_info->rcomp_phy);
grc_code = val << GRC_CODE_FAST_SHIFT |
val << GRC_CODE_SLOW_SHIFT |
@@ -557,7 +557,7 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
"BXT_PORT_CL2CM_DW6(%d)", phy);
if (phy_info->rcomp_phy != -1) {
- u32 grc_code = dev_priv->bxt_phy_grc;
+ u32 grc_code = dev_priv->display->bxt_phy_grc;
grc_code = grc_code << GRC_CODE_FAST_SHIFT |
grc_code << GRC_CODE_SLOW_SHIFT |
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7b1dfb00d1b3..76c833b6e326 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1757,7 +1757,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, DPLL_MD(PIPE_B),
crtc_state->dpll_hw_state.dpll_md);
intel_de_write(dev_priv, CBR4_VLV, 0);
- dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;
+ dev_priv->display->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;
/*
* DPLLB VGA mode also seems to cause problems.
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 47036316fbf9..e9871560e0e5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3110,10 +3110,10 @@ static void icl_update_active_dpll(struct intel_atomic_state *state,
static u32 intel_get_hti_plls(struct drm_i915_private *i915)
{
- if (!(i915->hti_state & HDPORT_ENABLED))
+ if (!(i915->display->hti_state & HDPORT_ENABLED))
return 0;
- return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
+ return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->display->hti_state);
}
static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 550efc29b54f..b3a48221b0fa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -925,6 +925,27 @@ struct drm_i915_display {
struct llist_head free_list;
struct work_struct free_work;
} atomic_helper;
+
+ /*
+ * HTI (aka HDPORT) state read during initial hw readout. Most
+ * platforms don't have HTI, so this will just stay 0. Those that do
+ * will use this later to figure out which PLLs and PHYs are unavailable
+ * for driver usage.
+ */
+ u32 hti_state;
+
+ /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
+ u32 chv_phy_control;
+ /*
+ * Shadows for CHV DPLL_MD regs to keep the state
+ * checker somewhat working in the presence hardware
+ * crappiness (can't read out DPLL_MD for pipes B & C).
+ */
+ u32 chv_dpll_md[I915_MAX_PIPES];
+ /* perform PHY state sanity checks? */
+ bool chv_phy_assert[2];
+
+ u32 bxt_phy_grc;
};
struct drm_i915_private {
@@ -1071,14 +1092,6 @@ struct drm_i915_private {
struct intel_l3_parity l3_parity;
- /*
- * HTI (aka HDPORT) state read during initial hw readout. Most
- * platforms don't have HTI, so this will just stay 0. Those that do
- * will use this later to figure out which PLLs and PHYs are unavailable
- * for driver usage.
- */
- u32 hti_state;
-
/*
* edram size in MB.
* Cannot be determined by PCIID. You must always read a register.
@@ -1093,16 +1106,6 @@ struct drm_i915_private {
u32 fdi_rx_config;
- /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
- u32 chv_phy_control;
- /*
- * Shadows for CHV DPLL_MD regs to keep the state
- * checker somewhat working in the presence hardware
- * crappiness (can't read out DPLL_MD for pipes B & C).
- */
- u32 chv_dpll_md[I915_MAX_PIPES];
- u32 bxt_phy_grc;
-
u32 suspend_count;
bool power_domains_suspended;
struct i915_suspend_saved_registers regfile;
@@ -1211,9 +1214,6 @@ struct drm_i915_private {
bool irq_enabled;
- /* perform PHY state sanity checks? */
- bool chv_phy_assert[2];
-
bool ipc_enabled;
struct i915_pmu pmu;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 22/25] drm/i915/display: move dpll struct into display
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (20 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 21/25] drm/i915/display: move a bunch of platform misc regs " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 23/25] drm/i915/display: move fdi_rx_config into display struct Dave Airlie
` (5 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 24 ++--
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
.../drm/i915/display/intel_display_debugfs.c | 8 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 104 +++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 40 ++++---
6 files changed, 98 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index a1e35180d5dd..4979b183408f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -650,13 +650,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display->dpll.lock);
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display->dpll.lock);
}
static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
@@ -666,13 +666,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display->dpll.lock);
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display->dpll.lock);
}
static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
@@ -702,7 +702,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
enum phy phy;
u32 val;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display->dpll.lock);
val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys) {
@@ -721,7 +721,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display->dpll.lock);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 73c7f8e3ea3b..8b0cf4f8ac63 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1450,7 +1450,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp,
static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
{
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display->dpll.lock);
intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
@@ -1460,17 +1460,17 @@ static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
*/
intel_de_rmw(i915, reg, clk_off, 0);
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display->dpll.lock);
}
static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
u32 clk_off)
{
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display->dpll.lock);
intel_de_rmw(i915, reg, 0, clk_off);
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display->dpll.lock);
}
static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
@@ -1745,12 +1745,12 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
intel_de_write(i915, DDI_CLK_SEL(port),
icl_pll_to_ddi_clk_sel(encoder, crtc_state));
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display->dpll.lock);
intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display->dpll.lock);
}
static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
@@ -1759,12 +1759,12 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
enum port port = encoder->port;
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display->dpll.lock);
intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display->dpll.lock);
intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
}
@@ -1849,7 +1849,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
if (drm_WARN_ON(&i915->drm, !pll))
return;
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display->dpll.lock);
intel_de_rmw(i915, DPLL_CTRL2,
DPLL_CTRL2_DDI_CLK_OFF(port) |
@@ -1857,7 +1857,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display->dpll.lock);
}
static void skl_ddi_disable_clock(struct intel_encoder *encoder)
@@ -1865,12 +1865,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum port port = encoder->port;
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display->dpll.lock);
intel_de_rmw(i915, DPLL_CTRL2,
0, DPLL_CTRL2_DDI_CLK_OFF(port));
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display->dpll.lock);
}
static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 606242b876b1..8e77bf7262df 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4765,7 +4765,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
}
/* Check if any DPLLs are using the SSC source */
- for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
+ for (i = 0; i < dev_priv->display->dpll.num_shared_dpll; i++) {
u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
if (!(temp & DPLL_VCO_ENABLE))
@@ -8093,11 +8093,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(double_wide);
- if (dev_priv->dpll.mgr)
+ if (dev_priv->display->dpll.mgr)
PIPE_CONF_CHECK_P(shared_dpll);
/* FIXME do the readout properly and get rid of this quirk */
- if (dev_priv->dpll.mgr && !PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
+ if (dev_priv->display->dpll.mgr && !PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE)) {
PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
@@ -8645,9 +8645,9 @@ verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
{
int i;
- for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
+ for (i = 0; i < dev_priv->display->dpll.num_shared_dpll; i++)
verify_single_dpll_state(dev_priv,
- &dev_priv->dpll.shared_dplls[i],
+ &dev_priv->display->dpll.shared_dplls[i],
NULL, NULL);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 784ce209add9..2841a67a9605 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1093,11 +1093,11 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
drm_modeset_lock_all(dev);
seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
- dev_priv->dpll.ref_clks.nssc,
- dev_priv->dpll.ref_clks.ssc);
+ dev_priv->display->dpll.ref_clks.nssc,
+ dev_priv->display->dpll.ref_clks.ssc);
- for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
+ for (i = 0; i < dev_priv->display->dpll.num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dev_priv->display->dpll.shared_dplls[i];
seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
pll->info->id);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e9871560e0e5..db3d676227a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -70,8 +70,8 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
enum intel_dpll_id i;
/* Copy shared dpll state */
- for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
+ for (i = 0; i < dev_priv->display->dpll.num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dev_priv->display->dpll.shared_dplls[i];
shared_dpll[i] = pll->state;
}
@@ -106,7 +106,7 @@ struct intel_shared_dpll *
intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
enum intel_dpll_id id)
{
- return &dev_priv->dpll.shared_dplls[id];
+ return &dev_priv->display->dpll.shared_dplls[id];
}
/**
@@ -121,11 +121,11 @@ enum intel_dpll_id
intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- long pll_idx = pll - dev_priv->dpll.shared_dplls;
+ long pll_idx = pll - dev_priv->display->dpll.shared_dplls;
if (drm_WARN_ON(&dev_priv->drm,
pll_idx < 0 ||
- pll_idx >= dev_priv->dpll.num_shared_dpll))
+ pll_idx >= dev_priv->display->dpll.num_shared_dpll))
return -1;
return pll_idx;
@@ -201,7 +201,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
if (drm_WARN_ON(&dev_priv->drm, pll == NULL))
return;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display->dpll.lock);
old_mask = pll->active_mask;
if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) ||
@@ -227,7 +227,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->on = true;
out:
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display->dpll.lock);
}
/**
@@ -250,7 +250,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
if (pll == NULL)
return;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display->dpll.lock);
if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask),
"%s not used by [CRTC:%d:%s]\n", pll->info->name,
crtc->base.base.id, crtc->base.name))
@@ -273,7 +273,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->on = false;
out:
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display->dpll.lock);
}
static struct intel_shared_dpll *
@@ -292,7 +292,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
- pll = &dev_priv->dpll.shared_dplls[i];
+ pll = &dev_priv->display->dpll.shared_dplls[i];
/* Only want to check enabled timings first */
if (shared_dpll[i].pipe_mask == 0) {
@@ -392,9 +392,9 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
if (!state->dpll_set)
return;
- for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
+ for (i = 0; i < dev_priv->display->dpll.num_shared_dpll; i++) {
struct intel_shared_dpll *pll =
- &dev_priv->dpll.shared_dplls[i];
+ &dev_priv->display->dpll.shared_dplls[i];
swap(pll->state, shared_dpll[i]);
}
@@ -486,7 +486,7 @@ static bool ibx_get_dpll(struct intel_atomic_state *state,
if (HAS_PCH_IBX(dev_priv)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
i = (enum intel_dpll_id) crtc->pipe;
- pll = &dev_priv->dpll.shared_dplls[i];
+ pll = &dev_priv->display->dpll.shared_dplls[i];
drm_dbg_kms(&dev_priv->drm,
"[CRTC:%d:%s] using pre-allocated %s\n",
@@ -894,7 +894,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
case WRPLL_REF_SPECIAL_HSW:
/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
- refclk = dev_priv->dpll.ref_clks.nssc;
+ refclk = dev_priv->display->dpll.ref_clks.nssc;
break;
}
fallthrough;
@@ -904,7 +904,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
* code only cares about 5% accuracy, and spread is a max of
* 0.5% downspread.
*/
- refclk = dev_priv->dpll.ref_clks.ssc;
+ refclk = dev_priv->display->dpll.ref_clks.ssc;
break;
case WRPLL_REF_LCPLL:
refclk = 2700000;
@@ -1052,12 +1052,12 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
{
- i915->dpll.ref_clks.ssc = 135000;
+ i915->display->dpll.ref_clks.ssc = 135000;
/* Non-SSC is only used on non-ULT HSW. */
if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
- i915->dpll.ref_clks.nssc = 24000;
+ i915->display->dpll.ref_clks.nssc = 24000;
else
- i915->dpll.ref_clks.nssc = 135000;
+ i915->display->dpll.ref_clks.nssc = 135000;
}
static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -1548,7 +1548,7 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
- i915->dpll.ref_clks.nssc,
+ i915->display->dpll.ref_clks.nssc,
&wrpll_params))
return false;
@@ -1575,7 +1575,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *pll_state)
{
- int ref_clock = i915->dpll.ref_clks.nssc;
+ int ref_clock = i915->display->dpll.ref_clks.nssc;
u32 p0, p1, p2, dco_freq;
p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
@@ -1782,7 +1782,7 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->dpll.ref_clks.nssc = i915->display->cdclk.hw.ref;
+ i915->display->dpll.ref_clks.nssc = i915->display->cdclk.hw.ref;
}
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -2227,7 +2227,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
- return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
+ return chv_calc_dpll_params(i915->display->dpll.ref_clks.nssc, &clock);
}
static bool bxt_get_dpll(struct intel_atomic_state *state,
@@ -2265,8 +2265,8 @@ static bool bxt_get_dpll(struct intel_atomic_state *state,
static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
{
- i915->dpll.ref_clks.ssc = 100000;
- i915->dpll.ref_clks.nssc = 100000;
+ i915->display->dpll.ref_clks.ssc = 100000;
+ i915->display->dpll.ref_clks.nssc = 100000;
/* DSI non-SSC ref 19.2MHz */
}
@@ -2408,7 +2408,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
- i915->dpll.ref_clks.nssc == 38400;
+ i915->display->dpll.ref_clks.nssc == 38400;
}
struct icl_combo_pll_params {
@@ -2502,7 +2502,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
const struct icl_combo_pll_params *params =
- dev_priv->dpll.ref_clks.nssc == 24000 ?
+ dev_priv->display->dpll.ref_clks.nssc == 24000 ?
icl_dp_combo_pll_24MHz_values :
icl_dp_combo_pll_19_2MHz_values;
int clock = crtc_state->port_clock;
@@ -2525,9 +2525,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
if (DISPLAY_VER(dev_priv) >= 12) {
- switch (dev_priv->dpll.ref_clks.nssc) {
+ switch (dev_priv->display->dpll.ref_clks.nssc) {
default:
- MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
+ MISSING_CASE(dev_priv->display->dpll.ref_clks.nssc);
fallthrough;
case 19200:
case 38400:
@@ -2538,9 +2538,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
break;
}
} else {
- switch (dev_priv->dpll.ref_clks.nssc) {
+ switch (dev_priv->display->dpll.ref_clks.nssc) {
default:
- MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
+ MISSING_CASE(dev_priv->display->dpll.ref_clks.nssc);
fallthrough;
case 19200:
case 38400:
@@ -2570,7 +2570,7 @@ static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
{
- int ref_clock = i915->dpll.ref_clks.nssc;
+ int ref_clock = i915->display->dpll.ref_clks.nssc;
/*
* For ICL+, the spec states: if reference frequency is 38.4,
@@ -2796,7 +2796,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
struct intel_dpll_hw_state *pll_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- int refclk_khz = dev_priv->dpll.ref_clks.nssc;
+ int refclk_khz = dev_priv->display->dpll.ref_clks.nssc;
int clock = crtc_state->port_clock;
u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
u32 iref_ndiv, iref_trim, iref_pulse_w;
@@ -3004,7 +3004,7 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
- ref_clock = dev_priv->dpll.ref_clks.nssc;
+ ref_clock = dev_priv->display->dpll.ref_clks.nssc;
if (DISPLAY_VER(dev_priv) >= 12) {
m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
@@ -3349,7 +3349,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->mg_pll_tdc_coldst_bias =
intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
- if (dev_priv->dpll.ref_clks.nssc == 38400) {
+ if (dev_priv->display->dpll.ref_clks.nssc == 38400) {
hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
hw_state->mg_pll_bias_mask = 0;
} else {
@@ -3867,7 +3867,7 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->dpll.ref_clks.nssc = i915->display->cdclk.hw.ref;
+ i915->display->dpll.ref_clks.nssc = i915->display->cdclk.hw.ref;
}
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -4085,7 +4085,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
dpll_mgr = &pch_pll_mgr;
if (!dpll_mgr) {
- dev_priv->dpll.num_shared_dpll = 0;
+ dev_priv->display->dpll.num_shared_dpll = 0;
return;
}
@@ -4093,14 +4093,14 @@ void intel_shared_dpll_init(struct drm_device *dev)
for (i = 0; dpll_info[i].name; i++) {
drm_WARN_ON(dev, i != dpll_info[i].id);
- dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];
+ dev_priv->display->dpll.shared_dplls[i].info = &dpll_info[i];
}
- dev_priv->dpll.mgr = dpll_mgr;
- dev_priv->dpll.num_shared_dpll = i;
- mutex_init(&dev_priv->dpll.lock);
+ dev_priv->display->dpll.mgr = dpll_mgr;
+ dev_priv->display->dpll.num_shared_dpll = i;
+ mutex_init(&dev_priv->display->dpll.lock);
- BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
+ BUG_ON(dev_priv->display->dpll.num_shared_dpll > I915_NUM_PLLS);
}
/**
@@ -4127,7 +4127,7 @@ bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->display->dpll.mgr;
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
return false;
@@ -4150,7 +4150,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->display->dpll.mgr;
/*
* FIXME: this function is called for every platform having a
@@ -4179,7 +4179,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->display->dpll.mgr;
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
return;
@@ -4250,16 +4250,16 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
{
- if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
- i915->dpll.mgr->update_ref_clks(i915);
+ if (i915->display->dpll.mgr && i915->display->dpll.mgr->update_ref_clks)
+ i915->display->dpll.mgr->update_ref_clks(i915);
}
void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
{
int i;
- for (i = 0; i < i915->dpll.num_shared_dpll; i++)
- readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
+ for (i = 0; i < i915->display->dpll.num_shared_dpll; i++)
+ readout_dpll_hw_state(i915, &i915->display->dpll.shared_dplls[i]);
}
static void sanitize_dpll_state(struct drm_i915_private *i915,
@@ -4285,8 +4285,8 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
{
int i;
- for (i = 0; i < i915->dpll.num_shared_dpll; i++)
- sanitize_dpll_state(i915, &i915->dpll.shared_dplls[i]);
+ for (i = 0; i < i915->display->dpll.num_shared_dpll; i++)
+ sanitize_dpll_state(i915, &i915->display->dpll.shared_dplls[i]);
}
/**
@@ -4299,8 +4299,8 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
- if (dev_priv->dpll.mgr) {
- dev_priv->dpll.mgr->dump_hw_state(dev_priv, hw_state);
+ if (dev_priv->display->dpll.mgr) {
+ dev_priv->display->dpll.mgr->dump_hw_state(dev_priv, hw_state);
} else {
/* fallback for platforms that don't use the shared dpll
* infrastructure
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b3a48221b0fa..c73140ccdb44 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -946,6 +946,25 @@ struct drm_i915_display {
bool chv_phy_assert[2];
u32 bxt_phy_grc;
+
+ /**
+ * dpll and cdclk state is protected by connection_mutex
+ * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
+ * Must be global rather than per dpll, because on some platforms plls
+ * share registers.
+ */
+ struct {
+ struct mutex lock;
+
+ int num_shared_dpll;
+ struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
+ const struct intel_dpll_mgr *mgr;
+
+ struct {
+ int nssc;
+ int ssc;
+ } ref_clks;
+ } dpll;
};
struct drm_i915_private {
@@ -1063,27 +1082,6 @@ struct drm_i915_private {
struct i915_gem_mm mm;
- /* Kernel Modesetting */
-
- /**
- * dpll and cdclk state is protected by connection_mutex
- * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
- * Must be global rather than per dpll, because on some platforms plls
- * share registers.
- */
- struct {
- struct mutex lock;
-
- int num_shared_dpll;
- struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
- const struct intel_dpll_mgr *mgr;
-
- struct {
- int nssc;
- int ssc;
- } ref_clks;
- } dpll;
-
struct list_head global_obj_list;
struct i915_wa_list gt_wa_list;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 23/25] drm/i915/display: move fdi_rx_config into display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (21 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 22/25] drm/i915/display: move dpll struct into display Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 24/25] drm/i915/display: move workqueues to " Dave Airlie
` (4 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 97a274f0a38d..5caa4e2c6b3d 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -1111,7 +1111,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
FDI_RX_LINK_REVERSAL_OVERRIDE;
- dev_priv->fdi_rx_config = intel_de_read(dev_priv,
+ dev_priv->display->fdi_rx_config = intel_de_read(dev_priv,
FDI_RX_CTL(PIPE_A)) & fdi_config;
}
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index fc92c7f5d4c9..4f018021d115 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -683,7 +683,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
/* Enable the PCH Receiver FDI PLL */
- rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
+ rx_ctl_val = dev_priv->display->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
FDI_RX_PLL_ENABLE |
FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c73140ccdb44..248fe12aa62d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -965,6 +965,8 @@ struct drm_i915_display {
int ssc;
} ref_clks;
} dpll;
+
+ u32 fdi_rx_config;
};
struct drm_i915_private {
@@ -1102,8 +1104,6 @@ struct drm_i915_private {
struct drm_i915_gem_object *vlv_pctx;
- u32 fdi_rx_config;
-
u32 suspend_count;
bool power_domains_suspended;
struct i915_suspend_saved_registers regfile;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 24/25] drm/i915/display: move workqueues to display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (22 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 23/25] drm/i915/display: move fdi_rx_config into display struct Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 25/25] drm/i915/display: move pps/backlight mutexes into display Dave Airlie
` (3 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 10 +++++-----
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8e77bf7262df..374ca94785fa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10438,12 +10438,12 @@ static int intel_atomic_commit(struct drm_device *dev,
i915_sw_fence_commit(&state->commit_ready);
if (nonblock && state->modeset) {
- queue_work(dev_priv->modeset_wq, &state->base.commit_work);
+ queue_work(dev_priv->display->modeset_wq, &state->base.commit_work);
} else if (nonblock) {
- queue_work(dev_priv->flip_wq, &state->base.commit_work);
+ queue_work(dev_priv->display->flip_wq, &state->base.commit_work);
} else {
if (state->modeset)
- flush_workqueue(dev_priv->modeset_wq);
+ flush_workqueue(dev_priv->display->modeset_wq);
intel_atomic_commit_tail(state);
}
@@ -11569,8 +11569,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
intel_dmc_ucode_init(i915);
- i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
- i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
+ i915->display->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
+ i915->display->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
i915->display->framestart_delay = 1; /* 1-4 */
@@ -12627,8 +12627,8 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return;
- flush_workqueue(i915->flip_wq);
- flush_workqueue(i915->modeset_wq);
+ flush_workqueue(i915->display->flip_wq);
+ flush_workqueue(i915->display->modeset_wq);
flush_work(&i915->display->atomic_helper.free_work);
drm_WARN_ON(&i915->drm, !llist_empty(&i915->display->atomic_helper.free_list));
@@ -12671,8 +12671,8 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
intel_gmbus_teardown(i915);
- destroy_workqueue(i915->flip_wq);
- destroy_workqueue(i915->modeset_wq);
+ destroy_workqueue(i915->display->flip_wq);
+ destroy_workqueue(i915->display->modeset_wq);
intel_fbc_cleanup_cfb(i915);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 248fe12aa62d..e142feb5bc9c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -967,6 +967,11 @@ struct drm_i915_display {
} dpll;
u32 fdi_rx_config;
+
+ /* ordered wq for modesets */
+ struct workqueue_struct *modeset_wq;
+ /* unbound hipri wq for page flips/plane updates */
+ struct workqueue_struct *flip_wq;
};
struct drm_i915_private {
@@ -1069,11 +1074,6 @@ struct drm_i915_private {
*/
struct workqueue_struct *wq;
- /* ordered wq for modesets */
- struct workqueue_struct *modeset_wq;
- /* unbound hipri wq for page flips/plane updates */
- struct workqueue_struct *flip_wq;
-
/* PCH chipset type */
enum intel_pch pch_type;
unsigned short pch_id;
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH 25/25] drm/i915/display: move pps/backlight mutexes into display
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (23 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 24/25] drm/i915/display: move workqueues to " Dave Airlie
@ 2021-09-07 7:25 ` Dave Airlie
2021-09-07 7:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for refactor display struct Patchwork
` (2 subsequent siblings)
27 siblings, 0 replies; 29+ messages in thread
From: Dave Airlie @ 2021-09-07 7:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Dave Airlie
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/i915/display/intel_backlight.c | 28 +++++++-------
drivers/gpu/drm/i915/display/intel_pps.c | 38 +++++++++----------
drivers/gpu/drm/i915/i915_drv.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 12 +++---
4 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 41e10d1afe72..04bf4a67d56f 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -300,7 +300,7 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state,
if (!panel->backlight.present || !conn_state->crtc)
return;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display->backlight_lock);
drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0);
@@ -316,7 +316,7 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state,
if (panel->backlight.enabled)
intel_panel_actually_set_backlight(conn_state, hw_level);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display->backlight_lock);
}
static void lpt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 level)
@@ -458,14 +458,14 @@ void intel_backlight_disable(const struct drm_connector_state *old_conn_state)
return;
}
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display->backlight_lock);
if (panel->backlight.device)
panel->backlight.device->props.power = FB_BLANK_POWERDOWN;
panel->backlight.enabled = false;
panel->backlight.funcs->disable(old_conn_state, 0);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display->backlight_lock);
}
static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state,
@@ -808,11 +808,11 @@ void intel_backlight_enable(const struct intel_crtc_state *crtc_state,
drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(pipe));
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display->backlight_lock);
__intel_backlight_enable(crtc_state, conn_state);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display->backlight_lock);
}
#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
@@ -822,12 +822,12 @@ static u32 intel_panel_get_backlight(struct intel_connector *connector)
struct intel_panel *panel = &connector->panel;
u32 val = 0;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display->backlight_lock);
if (panel->backlight.enabled)
val = panel->backlight.funcs->get(connector, intel_connector_get_pipe(connector));
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display->backlight_lock);
drm_dbg_kms(&dev_priv->drm, "get backlight PWM = %d\n", val);
return val;
@@ -855,7 +855,7 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta
if (!panel->backlight.present)
return;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display->backlight_lock);
drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0);
@@ -865,7 +865,7 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta
if (panel->backlight.enabled)
intel_panel_actually_set_backlight(conn_state, hw_level);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display->backlight_lock);
}
static int intel_backlight_device_update_status(struct backlight_device *bd)
@@ -1585,11 +1585,11 @@ void intel_backlight_update(struct intel_atomic_state *state,
if (!panel->backlight.present)
return;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display->backlight_lock);
if (!panel->backlight.enabled)
__intel_backlight_enable(crtc_state, conn_state);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display->backlight_lock);
}
int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)
@@ -1614,9 +1614,9 @@ int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)
return -ENODEV;
/* set level and max in panel struct */
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display->backlight_lock);
ret = panel->backlight.funcs->setup(connector, pipe);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display->backlight_lock);
if (ret) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 0e8d8d0dd51c..42d13b3f7479 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -26,7 +26,7 @@ intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
* See intel_pps_reset_all() why we need a power domain reference here.
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
- mutex_lock(&dev_priv->pps_mutex);
+ mutex_lock(&dev_priv->display->pps_mutex);
return wakeref;
}
@@ -36,7 +36,7 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- mutex_unlock(&dev_priv->pps_mutex);
+ mutex_unlock(&dev_priv->display->pps_mutex);
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
return 0;
@@ -161,7 +161,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum pipe pipe;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
@@ -209,7 +209,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
int backlight_controller = dev_priv->vbt.backlight.controller;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
@@ -279,7 +279,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum port port = dig_port->base.port;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
/* try to find a pipe with this port selected */
/* first pick one where the panel is on */
@@ -404,7 +404,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_dp->pps.pps_pipe == INVALID_PIPE)
@@ -417,7 +417,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_dp->pps.pps_pipe == INVALID_PIPE)
@@ -460,7 +460,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t pp_stat_reg, pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
intel_pps_verify_state(intel_dp);
@@ -553,7 +553,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 control;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
@@ -577,7 +577,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
i915_reg_t pp_stat_reg, pp_ctrl_reg;
bool need_to_disable = !intel_dp->pps.want_panel_vdd;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
if (!intel_dp_is_edp(intel_dp))
return false;
@@ -654,7 +654,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
u32 pp;
i915_reg_t pp_stat_reg, pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
@@ -738,7 +738,7 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
if (!intel_dp_is_edp(intel_dp))
return;
@@ -761,7 +761,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
u32 pp;
i915_reg_t pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
if (!intel_dp_is_edp(intel_dp))
return;
@@ -822,7 +822,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
u32 pp;
i915_reg_t pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
if (!intel_dp_is_edp(intel_dp))
return;
@@ -981,7 +981,7 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
{
struct intel_encoder *encoder;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -1011,7 +1011,7 @@ void vlv_pps_init(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
@@ -1054,7 +1054,7 @@ static void intel_pps_vdd_sanitize(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
if (!edp_have_panel_vdd(intel_dp))
return;
@@ -1159,7 +1159,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
struct edp_power_seq cur, vbt, spec,
*final = &intel_dp->pps.pps_delays;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
/* already initialized? */
if (final->t11_t12 != 0)
@@ -1257,7 +1257,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
enum port port = dp_to_dig_port(intel_dp)->base.port;
const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display->pps_mutex);
intel_pps_get_registers(intel_dp, ®s);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8878bfcee0ca..7ea2be06b980 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -315,14 +315,14 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
- mutex_init(&dev_priv->backlight_lock);
+ mutex_init(&dev_priv->display->backlight_lock);
mutex_init(&dev_priv->sb_lock);
cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
mutex_init(&dev_priv->display->av_mutex);
mutex_init(&dev_priv->wm.wm_mutex);
- mutex_init(&dev_priv->pps_mutex);
+ mutex_init(&dev_priv->display->pps_mutex);
mutex_init(&dev_priv->display->hdcp_comp_mutex);
i915_memcpy_init_early(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e142feb5bc9c..89eb06dd3a30 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -972,6 +972,12 @@ struct drm_i915_display {
struct workqueue_struct *modeset_wq;
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
+
+ /* backlight registers and fields in struct intel_panel */
+ struct mutex backlight_lock;
+
+ /* protects panel power sequencer state */
+ struct mutex pps_mutex;
};
struct drm_i915_private {
@@ -1050,12 +1056,6 @@ struct drm_i915_private {
bool preserve_bios_swizzle;
- /* backlight registers and fields in struct intel_panel */
- struct mutex backlight_lock;
-
- /* protects panel power sequencer state */
- struct mutex pps_mutex;
-
unsigned int fsb_freq, mem_freq, is_ddr3;
struct {
--
2.31.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for refactor display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (24 preceding siblings ...)
2021-09-07 7:25 ` [Intel-gfx] [PATCH 25/25] drm/i915/display: move pps/backlight mutexes into display Dave Airlie
@ 2021-09-07 7:57 ` Patchwork
2021-09-07 8:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-07 10:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
27 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2021-09-07 7:57 UTC (permalink / raw)
To: Dave Airlie; +Cc: intel-gfx
== Series Details ==
Series: refactor display struct
URL : https://patchwork.freedesktop.org/series/94413/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
191aa552f294 drm/i915: move display funcs into a display struct. (v3)
675cb420d0d5 drm/i915/display: move cdclk info into display
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:662: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#662: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:77:
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display->cdclk.obj))
-:665: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#665: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:79:
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display->cdclk.obj))
-:711: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#711: FILE: drivers/gpu/drm/i915/display/intel_display.c:11273:
+ cdclk_state->logical = cdclk_state->actual = i915->display->cdclk.hw;
total: 0 errors, 3 warnings, 1 checks, 782 lines checked
e3baf407701c drm/i915: move more pll/clocks into display struct.
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:149: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#149: FILE: drivers/gpu/drm/i915/display/intel_display.c:179:
+ dev_priv->display->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
CCK_CZ_CLOCK_CONTROL);
total: 0 errors, 1 warnings, 1 checks, 302 lines checked
5040a27ce12a drm/i915/display: move gmbus into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:231: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#231: FILE: drivers/gpu/drm/i915/i915_drv.h:860:
+ * controller on different i2c buses. */
-:300: WARNING:LONG_LINE_COMMENT: line length of 105 exceeds 100 columns
#300: FILE: drivers/gpu/drm/i915/i915_reg.h:3453:
+#define GMBUS0 _MMIO(dev_priv->display->gpio_mmio_base + 0x5100) /* clock/port select */
-:309: WARNING:LONG_LINE_COMMENT: line length of 102 exceeds 100 columns
#309: FILE: drivers/gpu/drm/i915/i915_reg.h:3462:
+#define GMBUS1 _MMIO(dev_priv->display->gpio_mmio_base + 0x5104) /* command/status */
-:328: WARNING:LONG_LINE_COMMENT: line length of 109 exceeds 100 columns
#328: FILE: drivers/gpu/drm/i915/i915_reg.h:3485:
+#define GMBUS3 _MMIO(dev_priv->display->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
-:329: WARNING:LONG_LINE_COMMENT: line length of 114 exceeds 100 columns
#329: FILE: drivers/gpu/drm/i915/i915_reg.h:3486:
+#define GMBUS4 _MMIO(dev_priv->display->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
total: 0 errors, 6 warnings, 0 checks, 282 lines checked
d8649e4e0a68 drm/i915/display: move intel_dmc into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:81: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#81: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:968:
+ DMC_PROGRAM(dev_priv->display->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
total: 0 errors, 2 warnings, 0 checks, 322 lines checked
35bbd187afd0 drm/i915/display: move mipi_mmio_base to display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 404 lines checked
25c356adc849 drm/i915/display: move pps_mmio_base to display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 36 lines checked
e4f81d31c1d5 drm/i915/drrs: just use some local vars to simplify drrs code
0e0a6ffa4329 drm/i915/display: move drrs into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 146 lines checked
cc85ebb38f7a drm/i915/display: move fbc into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 420 lines checked
1a85a7c162f2 drm/i915/display: move pipe/plane mappings to display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:19: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#19: FILE: drivers/gpu/drm/i915/display/intel_crtc.c:326:
+ BUG_ON(pipe >= ARRAY_SIZE(dev_priv->display->pipe_to_crtc_mapping) ||
-:20: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "dev_priv->display->pipe_to_crtc_mapping[pipe]"
#20: FILE: drivers/gpu/drm/i915/display/intel_crtc.c:327:
+ dev_priv->display->pipe_to_crtc_mapping[pipe] != NULL);
-:29: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#29: FILE: drivers/gpu/drm/i915/display/intel_crtc.c:333:
+ BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->display->plane_to_crtc_mapping) ||
-:30: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "dev_priv->display->plane_to_crtc_mapping[i9xx_plane]"
#30: FILE: drivers/gpu/drm/i915/display/intel_crtc.c:334:
+ dev_priv->display->plane_to_crtc_mapping[i9xx_plane] != NULL);
total: 0 errors, 3 warnings, 2 checks, 66 lines checked
5172cf469738 drm/i915/display: move properties into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 75 lines checked
cbb25f490c34 drm/i915/display: move audio related members into display struct
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:274: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "display->lpe_audio.platdev"
#274: FILE: drivers/gpu/drm/i915/display/intel_audio.c:1359:
+ if ((dev_priv)->display->lpe_audio.platdev != NULL)
-:287: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "display->lpe_audio.platdev"
#287: FILE: drivers/gpu/drm/i915/display/intel_lpe_audio.c:77:
+#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display->lpe_audio.platdev != NULL)
-:296: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#296: FILE: drivers/gpu/drm/i915/display/intel_lpe_audio.c:99:
+ rsc[0].start = rsc[0].end = dev_priv->display->lpe_audio.irq;
total: 0 errors, 1 warnings, 3 checks, 420 lines checked
adaf555cdd95 drm/i915/display: move HDCP related items into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 360 lines checked
ef7e716d5ec3 drm/i915/display: move hotplug struct to display struct
-:363: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#363: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:576:
+ queue_work(dev_priv->_display.hotplug.dp_wq, &dev_priv->_display.hotplug.dig_port_work);
-:519: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!dev_priv->display->hotplug.dp_wq"
#519: FILE: drivers/gpu/drm/i915/i915_drv.c:240:
+ if (dev_priv->display->hotplug.dp_wq == NULL)
total: 0 errors, 1 warnings, 1 checks, 639 lines checked
d9b07b132b95 drm/i915/display: move overlay into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 74 lines checked
5ed9b4591952 drm/i915/display: move fbdev info to display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 126 lines checked
03a98bbdc906 drm/i915/display: move fb_tracking to display struct
bc5e519534b7 drm/i915/display: move delay and pch values to display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 181 lines checked
4205bb4cb2ac drm/intel/display: move atomic related things to display
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 134 lines checked
cc5ba8e76b3a drm/i915/display: move a bunch of platform misc regs to display
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:289: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#289: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:434:
+ val = dev_priv->display->bxt_phy_grc = bxt_get_grc(dev_priv,
total: 0 errors, 1 warnings, 1 checks, 344 lines checked
78d513b8e7f4 drm/i915/display: move dpll struct into display
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:515: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#515: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:4103:
+ BUG_ON(dev_priv->display->dpll.num_shared_dpll > I915_NUM_PLLS);
-:605: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#605: FILE: drivers/gpu/drm/i915/i915_drv.h:957:
+ struct mutex lock;
total: 0 errors, 2 warnings, 1 checks, 563 lines checked
d51c54a76b1c drm/i915/display: move fdi_rx_config into display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:18: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#18: FILE: drivers/gpu/drm/i915/display/intel_crt.c:1115:
+ dev_priv->display->fdi_rx_config = intel_de_read(dev_priv,
FDI_RX_CTL(PIPE_A)) & fdi_config;
total: 0 errors, 1 warnings, 1 checks, 32 lines checked
af49c401bbaa drm/i915/display: move workqueues to display struct
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 67 lines checked
7773cefe49b1 drm/i915/display: move pps/backlight mutexes into display
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 291 lines checked
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for refactor display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (25 preceding siblings ...)
2021-09-07 7:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for refactor display struct Patchwork
@ 2021-09-07 8:28 ` Patchwork
2021-09-07 10:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
27 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2021-09-07 8:28 UTC (permalink / raw)
To: Dave Airlie; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5720 bytes --]
== Series Details ==
Series: refactor display struct
URL : https://patchwork.freedesktop.org/series/94413/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10555 -> Patchwork_20972
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/index.html
Known issues
------------
Here are the changes found in Patchwork_20972 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: NOTRUN -> [DMESG-WARN][3] ([i915#3958])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_timelines:
- fi-rkl-guc: [INCOMPLETE][4] ([i915#4034]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][6] ([i915#3303]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [INCOMPLETE][8] ([i915#3921]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [SKIP][10] ([fdo#109271]) -> [FAIL][11] ([i915#579])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#3057]: https://gitlab.freedesktop.org/drm/intel/issues/3057
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3958]: https://gitlab.freedesktop.org/drm/intel/issues/3958
[i915#3970]: https://gitlab.freedesktop.org/drm/intel/issues/3970
[i915#4034]: https://gitlab.freedesktop.org/drm/intel/issues/4034
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Participating hosts (43 -> 38)
------------------------------
Missing (5): bat-adls-5 bat-dg1-6 fi-bsw-cyan bat-adlp-4 fi-tgl-y
Build changes
-------------
* Linux: CI_DRM_10555 -> Patchwork_20972
CI-20190529: 20190529
CI_DRM_10555: f922237c0f7e4d8f98bdc7a3d6fc4ae4bfd5e3e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6197: 40888f97a6ad219f4ed48a1830d0ef3c9617d006 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20972: 7773cefe49b1d79074164381427fd19b7d10e2c3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7773cefe49b1 drm/i915/display: move pps/backlight mutexes into display
af49c401bbaa drm/i915/display: move workqueues to display struct
d51c54a76b1c drm/i915/display: move fdi_rx_config into display struct
78d513b8e7f4 drm/i915/display: move dpll struct into display
cc5ba8e76b3a drm/i915/display: move a bunch of platform misc regs to display
4205bb4cb2ac drm/intel/display: move atomic related things to display
bc5e519534b7 drm/i915/display: move delay and pch values to display struct
03a98bbdc906 drm/i915/display: move fb_tracking to display struct
5ed9b4591952 drm/i915/display: move fbdev info to display struct
d9b07b132b95 drm/i915/display: move overlay into display struct
ef7e716d5ec3 drm/i915/display: move hotplug struct to display struct
adaf555cdd95 drm/i915/display: move HDCP related items into display struct
cbb25f490c34 drm/i915/display: move audio related members into display struct
5172cf469738 drm/i915/display: move properties into display struct
1a85a7c162f2 drm/i915/display: move pipe/plane mappings to display struct
cc85ebb38f7a drm/i915/display: move fbc into display struct
0e0a6ffa4329 drm/i915/display: move drrs into display struct
e4f81d31c1d5 drm/i915/drrs: just use some local vars to simplify drrs code
25c356adc849 drm/i915/display: move pps_mmio_base to display struct
35bbd187afd0 drm/i915/display: move mipi_mmio_base to display struct
d8649e4e0a68 drm/i915/display: move intel_dmc into display struct
5040a27ce12a drm/i915/display: move gmbus into display struct
e3baf407701c drm/i915: move more pll/clocks into display struct.
675cb420d0d5 drm/i915/display: move cdclk info into display
191aa552f294 drm/i915: move display funcs into a display struct. (v3)
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/index.html
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^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for refactor display struct
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
` (26 preceding siblings ...)
2021-09-07 8:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-09-07 10:19 ` Patchwork
27 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2021-09-07 10:19 UTC (permalink / raw)
To: Dave Airlie; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30246 bytes --]
== Series Details ==
Series: refactor display struct
URL : https://patchwork.freedesktop.org/series/94413/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10555_full -> Patchwork_20972_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20972_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20972_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20972_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-snb: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-snb5/igt@gem_ppgtt@blt-vs-render-ctxn.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-snb7/igt@gem_ppgtt@blt-vs-render-ctxn.html
Known issues
------------
Here are the changes found in Patchwork_20972_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-queued:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-snb5/igt@gem_ctx_persistence@engines-queued.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2410])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#146] / [i915#198])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-skl10/igt@gem_eio@in-flight-suspend.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl4/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][8] ([i915#2846])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
- shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_whisper@basic-queues-priority:
- shard-iclb: NOTRUN -> [INCOMPLETE][16] ([i915#1895])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb6/igt@gem_exec_whisper@basic-queues-priority.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][17] -> [SKIP][18] ([i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-tglb3/igt@gem_huc_copy@huc-copy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#307]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb3/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][21] ([i915#2658])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-snb5/igt@gem_pread@exhaustion.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271]) +8 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl10/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-glk: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3323])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk6/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-iclb: NOTRUN -> [SKIP][24] ([i915#3297])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gem_userptr_blits@vma-merge:
- shard-glk: NOTRUN -> [FAIL][25] ([i915#3318])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk6/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-snb: NOTRUN -> [SKIP][26] ([fdo#109271]) +475 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-snb2/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][27] -> [INCOMPLETE][28] ([i915#146] / [i915#151])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-skl7/igt@i915_pm_rpm@system-suspend-execbuf.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl6/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3777]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-iclb: [PASS][30] -> [DMESG-WARN][31] ([i915#3621])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271]) +218 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl10/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109278] / [i915#3886]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +10 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109278]) +12 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-edid-read:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109284] / [fdo#111827]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@kms_chamelium@dp-edid-read.html
* igt@kms_color@pipe-c-ctm-0-75:
- shard-skl: [PASS][39] -> [DMESG-WARN][40] ([i915#1982])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-skl10/igt@kms_color@pipe-c-ctm-0-75.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl4/igt@kms_color@pipe-c-ctm-0-75.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +25 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-snb6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-glk: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +3 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk6/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +17 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl6/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl10/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][46] ([i915#1319]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-sliding:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109278] / [fdo#109279]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@kms_cursor_crc@pipe-c-cursor-512x170-sliding.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109274] / [fdo#109278])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb5/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-glk: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#533])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk6/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#111825])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-tglb2/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109274])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
- shard-kbl: [PASS][52] -> [FAIL][53] ([i915#79])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-kbl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-kbl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][54] -> [INCOMPLETE][55] ([i915#636])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip@plain-flip-ts-check@b-hdmi-a2:
- shard-glk: [PASS][56] -> [FAIL][57] ([i915#2122])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-glk9/igt@kms_flip@plain-flip-ts-check@b-hdmi-a2.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk8/igt@kms_flip@plain-flip-ts-check@b-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-iclb: NOTRUN -> [SKIP][58] ([i915#3701])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt:
- shard-glk: NOTRUN -> [SKIP][59] ([fdo#109271]) +38 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +10 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch:
- shard-skl: NOTRUN -> [FAIL][61] ([i915#1188])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl10/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#533]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-glk: NOTRUN -> [FAIL][63] ([fdo#108145] / [i915#265])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][64] ([fdo#108145] / [i915#265]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][65] ([i915#265])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][66] -> [FAIL][67] ([fdo#108145] / [i915#265])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-b-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#112054])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-tglb2/igt@kms_plane_lowres@pipe-b-tiling-yf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#658]) +5 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#2920])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_su@page_flip:
- shard-glk: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk6/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [PASS][72] -> [SKIP][73] ([fdo#109441]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-snb: NOTRUN -> [FAIL][74] ([i915#31])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-snb5/igt@kms_setmode@basic.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][75] ([IGT#2])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl3/igt@kms_sysfs_edid_timing.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2437])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl1/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-b-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][77] ([i915#2530])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@nouveau_crc@pipe-b-source-outp-inactive.html
* igt@prime_nv_test@nv_write_i915_cpu_mmap_read:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109291])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb5/igt@prime_nv_test@nv_write_i915_cpu_mmap_read.html
* igt@prime_vgem@fence-write-hang:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109295])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@prime_vgem@fence-write-hang.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2994]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl3/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@recycle-many:
- shard-glk: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2994]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk6/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][82] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb1/igt@gem_eio@unwedge-stress.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][84] ([i915#2846]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [FAIL][86] ([i915#2842]) -> [PASS][87] +3 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-kbl4/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][88] ([i915#2849]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-skl: [INCOMPLETE][90] ([i915#146] / [i915#198]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-skl8/igt@gem_exec_suspend@basic-s3.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl10/igt@gem_exec_suspend@basic-s3.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][92] ([i915#180]) -> [PASS][93] +4 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-apl2/igt@gem_workarounds@suspend-resume-context.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl2/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][94] ([i915#3921]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-snb2/igt@i915_selftest@live@hangcheck.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][96] ([i915#2346] / [i915#533]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [FAIL][98] ([i915#79]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@plain-flip-ts-check@a-hdmi-a2:
- shard-glk: [FAIL][100] ([i915#2122]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-glk9/igt@kms_flip@plain-flip-ts-check@a-hdmi-a2.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-glk8/igt@kms_flip@plain-flip-ts-check@a-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-iclb: [SKIP][102] ([i915#3701]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-iclb: [INCOMPLETE][104] -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][106] ([fdo#108145] / [i915#265]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][108] ([fdo#109441]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb1/igt@kms_psr@psr2_suspend.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@kms_psr@psr2_suspend.html
#### Warnings ####
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][110] ([i915#2920]) -> [SKIP][111] ([i915#658]) +2 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@runner@aborted:
- shard-iclb: ([FAIL][112], [FAIL][113]) ([i915#3002]) -> ([FAIL][114], [FAIL][115], [FAIL][116]) ([i915#1814] / [i915#3002])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb4/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-iclb1/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb2/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb1/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-iclb3/igt@runner@aborted.html
- shard-apl: ([FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> [FAIL][123] ([i915#3002] / [i915#3363])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-apl6/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-apl3/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-apl6/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-apl2/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-apl8/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10555/shard-apl6/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/shard-apl8/igt@runner@aborted.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1895]: https://gitlab.freedesktop.org/drm/intel/issues/1895
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2481]: https://gitlab.freedesktop.org/drm/intel/issues/2481
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3621]: https://gitlab.freedesktop.org/drm/intel/issues/3621
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3777]: https://gitlab.freedesktop.org/drm/intel/issues/3777
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_10555 -> Patchwork_20972
CI-20190529: 20190529
CI_DRM_10555: f922237c0f7e4d8f98bdc7a3d6fc4ae
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20972/index.html
[-- Attachment #2: Type: text/html, Size: 37707 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2021-09-07 10:19 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-07 7:25 [Intel-gfx] [RFC PATCH 00/25] refactor display struct Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 01/25] drm/i915: move display funcs into a display struct. (v3) Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 02/25] drm/i915/display: move cdclk info into display Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 03/25] drm/i915: move more pll/clocks into display struct Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 04/25] drm/i915/display: move gmbus " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 05/25] drm/i915/display: move intel_dmc " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 06/25] drm/i915/display: move mipi_mmio_base to " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 07/25] drm/i915/display: move pps_mmio_base " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 08/25] drm/i915/drrs: just use some local vars to simplify drrs code Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 09/25] drm/i915/display: move drrs into display struct Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 10/25] drm/i915/display: move fbc " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 11/25] drm/i915/display: move pipe/plane mappings to " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 12/25] drm/i915/display: move properties into " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 13/25] drm/i915/display: move audio related members " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 14/25] drm/i915/display: move HDCP related items " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 15/25] drm/i915/display: move hotplug struct to " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 16/25] drm/i915/display: move overlay into " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 17/25] drm/i915/display: move fbdev info to " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 18/25] drm/i915/display: move fb_tracking " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 19/25] drm/i915/display: move delay and pch values " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 20/25] drm/intel/display: move atomic related things to display Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 21/25] drm/i915/display: move a bunch of platform misc regs " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 22/25] drm/i915/display: move dpll struct into display Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 23/25] drm/i915/display: move fdi_rx_config into display struct Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 24/25] drm/i915/display: move workqueues to " Dave Airlie
2021-09-07 7:25 ` [Intel-gfx] [PATCH 25/25] drm/i915/display: move pps/backlight mutexes into display Dave Airlie
2021-09-07 7:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for refactor display struct Patchwork
2021-09-07 8:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-07 10:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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