From: Eric Anholt <eric@anholt.net>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level
Date: Thu, 31 Mar 2011 13:10:22 -0700 [thread overview]
Message-ID: <87mxkbt5jl.fsf@pollan.anholt.net> (raw)
In-Reply-To: <b7da2f$qu1e42@fmsmga001.fm.intel.com>
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On Thu, 31 Mar 2011 08:29:31 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Wed, 30 Mar 2011 14:45:11 -0700, Eric Anholt <eric@anholt.net> wrote:
> > On Wed, 30 Mar 2011 18:16:11 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > > On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt <eric@anholt.net> wrote:
> > > > And what about a CPU write through the GTT?
> > >
> > > Even on SNB these are still UC. And we should try hard not to, as the
> > > specs give dire warnings about writing to snooped PTEs through the GTT.
> > > (Since we will bypass the caches with the write, aiui, and cause
> > > confusion.)
> >
> > Oh, wow. That's really bad. Reject this series if so.
>
> I plucked that tidbit out of the specs for the BLT engine, which has not
> been rigorously updated since gen2... Though don't we also encounter a few
> subtleties with movnta (__copy_from_user_nocache_nozero from pwrite) and
> data in cachelines?
The only tricky correctness bit for those was how to flush the little
tiny movnt cache when you're done, which is "mfence". As far as other
interesting notes about movnt, it doesn't mean that the destination is
not in cache after the instruction -- if it was already in cache, it
will likely be in cache afterwards. I don't think that has any impact
on how we do our code.
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next prev parent reply other threads:[~2011-03-31 20:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-29 23:59 reduced LLC caching series Eric Anholt
2011-03-29 23:59 ` [PATCH 1/6] drm/i915: Rename agp_type to cache_level Eric Anholt
2011-03-29 23:59 ` [PATCH 2/6] drm/i915: Mark the cursor and the overlay as being part of the display planes Eric Anholt
2011-03-29 23:59 ` [PATCH 3/6] drm/i915: Do not clflush snooped objects Eric Anholt
2011-03-29 23:59 ` [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level Eric Anholt
2011-03-30 7:09 ` Chris Wilson
2011-03-30 16:59 ` Eric Anholt
2011-03-30 17:16 ` Chris Wilson
2011-03-30 21:45 ` Eric Anholt
2011-03-31 7:29 ` Chris Wilson
2011-03-31 20:10 ` Eric Anholt [this message]
2011-03-29 23:59 ` [PATCH 5/6] drm/i915: Use the uncached domain for the display planes v2 Eric Anholt
2011-03-29 23:59 ` [PATCH 6/6] drm/i915: Use the LLC mode on gen6 for everything but display Eric Anholt
2011-03-30 22:35 ` reduced LLC caching series Michael Larabel
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