messages from 2020-05-20 08:43:29 to 2020-05-22 02:28:09 UTC [more...]
[Intel-gfx] [PATCH 1/2] drm/i915: Disable semaphore inter-engine sync without timeslicing
2020-05-22 2:28 UTC (15+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915: Avoid using rq->engine after free during i915_fence_release
` [Intel-gfx] [PATCH] drm/i915: Disable semaphore inter-engine sync without timeslicing
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with drm/i915: Disable semaphore inter-engine sync without timeslicing (rev2)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v3] drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC
2020-05-22 2:03 UTC (5+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC (rev3)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI] drm/i915/selftests: Measure CS_TIMESTAMP
2020-05-21 23:14 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Measure CS_TIMESTAMP (rev5)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v9 0/7] Consider DBuf bandwidth when calculating CDCLK
2020-05-21 22:17 UTC (15+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for Consider DBuf bandwidth when calculating CDCLK (rev15)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Consider DBuf bandwidth when calculating CDCLK (rev18)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: success for Consider DBuf bandwidth when calculating CDCLK (rev15)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for Consider DBuf bandwidth when calculating CDCLK (rev18)
` [Intel-gfx] ✓ Fi.CI.IGT: success "
[Intel-gfx] [PATCH 0/4] mm/gup, drm/i915: refactor gup_fast, convert to pin_user_pages()
2020-05-21 20:40 UTC (4+ messages)
` [Intel-gfx] Solved: "
[Intel-gfx] [PATCH 1/2] drm/i915/execlists: Shortcircuit queue_prio() for no internal levels
2020-05-21 19:00 UTC (3+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915: Improve execute_cb struct packing
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/execlists: Shortcircuit queue_prio() for no internal levels
[Intel-gfx] [PATCH] drm/i915/gt: Stop cross-poluting PIN_GLOBAL with PIN_USER with no-ppgtt
2020-05-21 18:34 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
[Intel-gfx] [PATCH 00/37] Introduce DG1
2020-05-21 18:34 UTC (46+ messages)
` [Intel-gfx] [PATCH 01/37] drm/i915/rkl: Add DPLL4 support
` [Intel-gfx] [PATCH 02/37] drm/i915/rkl: Add DDC pin mapping
` [Intel-gfx] [PATCH 03/37] drm/i915/rkl: Setup ports/phys
` [Intel-gfx] [PATCH 04/37] drm/i915/rkl: provide port/phy mapping for vbt
` [Intel-gfx] [PATCH 05/37] drm/i915/rkl: Handle HTI
` [Intel-gfx] [PATCH 06/37] drm/i915/rkl: Handle comp master/slave relationships for PHYs
` [Intel-gfx] [PATCH 07/37] drm/i915/rkl: Add initial workarounds
` [Intel-gfx] [PATCH 08/37] drm/i915: make intel_{uncore, de}_rmw() more useful
` [Intel-gfx] [PATCH 09/37] drm/i915: Add has_master_unit_irq flag
` [Intel-gfx] [PATCH 10/37] drm/i915: add pcie snoop flag
` [Intel-gfx] [PATCH 11/37] drm/i915/dg1: add initial DG-1 definitions
` [Intel-gfx] [PATCH 12/37] drm/i915/dg1: Add DG1 PCI IDs
` [Intel-gfx] [PATCH 13/37] drm/i915/dg1: Add fake PCH
` [Intel-gfx] [PATCH 14/37] drm/i915/dg1: Initialize RAWCLK properly
` [Intel-gfx] [PATCH 15/37] drm/i915/dg1: Define MOCS table for DG1
` [Intel-gfx] [PATCH 16/37] drm/i915/dg1: Add DG1 power wells
` [Intel-gfx] [PATCH 17/37] drm/i915/dg1: Increase mmio size to 4MB
` [Intel-gfx] [PATCH 18/37] drm/i915/dg1: add support for the master unit interrupt
` [Intel-gfx] [PATCH 19/37] drm/i915/dg1: Wait for pcode/uncore handshake at startup
` [Intel-gfx] [PATCH 20/37] drm/i915/dg1: Add DPLL macros for DG1
` [Intel-gfx] [PATCH 21/37] drm/i915/dg1: Add and setup DPLLs "
` [Intel-gfx] [PATCH 22/37] drm/i915/dg1: Enable DPLL "
` [Intel-gfx] [PATCH 23/37] drm/i915/dg1: add hpd interrupt handling
` [Intel-gfx] [PATCH 24/37] drm/i915/dg1: invert HPD pins
` [Intel-gfx] [PATCH 25/37] drm/i915/dg1: gmbus pin mapping
` [Intel-gfx] [PATCH 26/37] drm/i915/dg1: Handle GRF/IC ECC error irq
` [Intel-gfx] [PATCH 27/37] drm/i915/dg1: Log counter on SLM ECC error
` [Intel-gfx] [PATCH 28/37] drm/i915/dg1: Enable first 2 ports for DG1
` [Intel-gfx] [PATCH 29/37] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
` [Intel-gfx] [PATCH 30/37] drm/i915/dg1: Update comp master/slave relationships for PHYs
` [Intel-gfx] [PATCH 31/37] drm/i915/dg1: Update voltage swing tables for DP
` [Intel-gfx] [PATCH 32/37] drm/i915/dg1: provide port/phy mapping for vbt
` [Intel-gfx] [PATCH 33/37] drm/i915/dg1: map/unmap pll clocks
` [Intel-gfx] [PATCH 34/37] drm/i915/dg1: enable PORT C/D aka D/E
` [Intel-gfx] [PATCH 35/37] drm/i915/dg1: Load DMC
` [Intel-gfx] [PATCH 36/37] drm/i915/dg1: Add initial DG1 workarounds
` [Intel-gfx] [PATCH 37/37] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI] drm/i915: Remove PIN_UPDATE for i915_vma_pin
2020-05-21 16:32 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
[Intel-gfx] [CI 1/2] drm/i915: Disable semaphore inter-engine sync without timeslicing
2020-05-21 16:05 UTC (4+ messages)
` [Intel-gfx] [CI 2/2] drm/i915: Avoid using rq->engine after free during i915_fence_release
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/2] drm/i915: Disable semaphore inter-engine sync without timeslicing
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PATCH] drm/i915: Add psr_safest_params
2020-05-21 16:04 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_nop: Specify timeout in milliseconds
2020-05-21 15:23 UTC (2+ messages)
` [Intel-gfx] [igt-dev] "
[Intel-gfx] [PATCH] drm/i915/gt: Cancel the flush worker more thoroughly
2020-05-21 15:16 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH 1/2] drm/i915: Remove PIN_UPDATE for i915_vma_pin
2020-05-21 14:36 UTC (2+ messages)
[Intel-gfx] [PATCH] drm/i915/selftests: Flush the submission, not cancel it!
2020-05-21 13:54 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
[Intel-gfx] [PATCH] drm/i915/hdcp: Avoid duplicate HDCP enables
2020-05-21 13:38 UTC (6+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/hdcp: Avoid duplicate HDCP enables (rev2)
[Intel-gfx] [PATCH] drm/i915/gt: Immediately check for ACK after submission
2020-05-21 13:11 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
[Intel-gfx] [PATCH] softirq: Kick ksoftirqd if __do_softirq() is incomplete
2020-05-21 12:04 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
[Intel-gfx] [CI] drm/i915/gt: Trace the CS interrupt
2020-05-21 10:52 UTC (7+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Trace the CS interrupt (rev5)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Trace the CS interrupt (rev6)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Trace the CS interrupt (rev7)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Trace the CS interrupt (rev8)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Trace the CS interrupt (rev9)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Trace the CS interrupt (rev10)
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_balancer: Exercise stalls of bonded pairs
2020-05-21 10:22 UTC
[Intel-gfx] [PATCH v11] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer
2020-05-21 6:09 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: Pre allocate and late cleanup of cmd buffer (rev10)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/hdcp: Add additional R0' wait
2020-05-21 5:27 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hdcp: Add additional R0' wait (rev2)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/hdcp: Add additional R0' wait
2020-05-21 5:12 UTC (4+ messages)
` [Intel-gfx] [PATCH v2] "
[Intel-gfx] [PATCH] drm: Replace deprecated function in drm_crtc_helper
2020-05-21 4:36 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] drm/i915: device params part 1
2020-05-21 3:52 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/params: don't expose inject_probe_failure in debugfs (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915: Disable semaphore inter-engine sync without timeslicing
2020-05-20 23:53 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable semaphore inter-engine sync without timeslicing (rev2)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH 01/22] drm/i915/gem: Suppress some random warnings
2020-05-20 20:47 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/22] "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915/ehl: Wa_22010271021
2020-05-20 18:29 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ehl: Wa_22010271021 (rev2)
[Intel-gfx] [PATCH 1/3] drm/writeback: don't set fence->ops to default
2020-05-20 18:09 UTC (10+ messages)
` [Intel-gfx] [PATCH 3/3] misc/habalabs: don't set default fence_ops->wait
[Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake
2020-05-20 17:49 UTC (6+ messages)
` [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Verify timeslicing between submit-fence
2020-05-20 16:29 UTC
[Intel-gfx] [PATCH i-g-t] i915/i915_pm_rc6_residency: Check we conserve power while waiting
2020-05-20 15:54 UTC
[Intel-gfx] [PATCH v2] drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC
2020-05-20 15:46 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ehl: Extend w/a 14010685332 to JSP/MCC (rev2)
[Intel-gfx] [PATCH v9 6/7] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs
2020-05-20 15:00 UTC (2+ messages)
[Intel-gfx] [PATCH v9 4/7] drm/i915: Plane configuration affects CDCLK in Gen11+
2020-05-20 14:59 UTC (2+ messages)
[Intel-gfx] [PATCH v9 3/7] drm/i915: Check plane configuration properly
2020-05-20 14:58 UTC (2+ messages)
[Intel-gfx] [PATCH 01/23] Revert "drm/i915/gem: Drop relocation slowpath"
2020-05-20 14:00 UTC (26+ messages)
` [Intel-gfx] [PATCH 02/23] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2
` [Intel-gfx] [PATCH 03/23] drm/i915: Remove locking from i915_gem_object_prepare_read/write
` [Intel-gfx] [PATCH 04/23] drm/i915: Parse command buffer earlier in eb_relocate(slow)
` [Intel-gfx] [PATCH 05/23] Revert "drm/i915/gem: Split eb_vma into its own allocation"
` [Intel-gfx] [PATCH 06/23] drm/i915/gem: Make eb_add_lut interruptible wait on object lock
` [Intel-gfx] [PATCH 07/23] drm/i915: Use per object locking in execbuf, v10
` [Intel-gfx] [PATCH 08/23] drm/i915: Use ww locking in intel_renderstate
` [Intel-gfx] [PATCH 09/23] drm/i915: Add ww context handling to context_barrier_task
` [Intel-gfx] [PATCH 10/23] drm/i915: Nuke arguments to eb_pin_engine
` [Intel-gfx] [PATCH 11/23] drm/i915: Pin engine before pinning all objects, v4
` [Intel-gfx] [PATCH 12/23] drm/i915: Rework intel_context pinning to do everything outside of pin_mutex
` [Intel-gfx] [PATCH 13/23] drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin
` [Intel-gfx] [PATCH 14/23] drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2
` [Intel-gfx] [PATCH 15/23] drm/i915: Kill last user of intel_context_create_request outside of selftests
` [Intel-gfx] [PATCH 16/23] drm/i915: Convert i915_perf to ww locking as well
` [Intel-gfx] [PATCH 17/23] drm/i915: Dirty hack to fix selftests locking inversion
` [Intel-gfx] [PATCH 18/23] drm/i915/selftests: Fix locking inversion in lrc selftest
` [Intel-gfx] [PATCH 19/23] drm/i915: Use ww pinning for intel_context_create_request()
` [Intel-gfx] [PATCH 20/23] drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2
` [Intel-gfx] [PATCH 21/23] drm/i915: Add ww locking to vm_fault_gtt
` [Intel-gfx] [PATCH 22/23] drm/i915: Add ww locking to pin_to_display_plane
` [Intel-gfx] [PATCH 23/23] drm/i915: Ensure we hold the pin mutex
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/23] Revert "drm/i915/gem: Drop relocation slowpath"
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH v6 00/16] drm/i915: Add support for HDCP 1.4 over MST connectors
2020-05-20 13:11 UTC (5+ messages)
[Intel-gfx] [CI] drm/i915/gt: Trace the CS interrupt
2020-05-20 12:43 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Trace the CS interrupt (rev3)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Trace the CS interrupt (rev4)
[Intel-gfx] [PULL] drm-intel-next-fixes
2020-05-20 12:32 UTC
[Intel-gfx] [PATCH i-g-t] tools/intel_gpu_top: Include total package power
2020-05-20 12:07 UTC (4+ messages)
` [Intel-gfx] [igt-dev] "
[Intel-gfx] [PATCH] dma-fence: add might_sleep annotation to _wait()
2020-05-20 11:03 UTC (3+ messages)
[Intel-gfx] [PATCH] drm/i915/gem: Suppress some random warnings
2020-05-20 10:58 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
[Intel-gfx] [PATCH] drm/i915/gt: Remove errant assertion in __intel_context_do_pin
2020-05-20 10:51 UTC (2+ messages)
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