Re: [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time

[Paulo Zanoni <przanoni@gmail.com>]

2012/10/27 Daniel Vetter <daniel.vetter@ffwll.ch>:
> On Sat, Oct 27, 2012 at 3:03 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>> 2012/10/27 Daniel Vetter <daniel.vetter@ffwll.ch>:
>>> On Sat, Oct 27, 2012 at 1:51 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>>>> 2012/10/26 Daniel Vetter <daniel.vetter@ffwll.ch>:
>>>>> According to "Graphics BSpec: vol4g North Display Engine Registers [IVB],
>>>>> Display Mode Set Sequence" We need to write the TU size register
>>>>> of the fdi RX unit _before_ starting to train the link.
>>>>
>>>> Well, we are still writing it before training the link, but it's
>>>> waaaaay before :)
>>>> But I agree with the patch, it makes the code look more like our mode
>>>> set sequence docs.
>>>
>>> Indeed, I've confused myself with the placement of the fdi pll code
>>> quite a bit. I think that's actually a remnant of the pre-modeset
>>> world, where we could potentially enter the modeset functions with
>>> unknown states. I think I'll keep things as-is, and instead add a
>>> comment to the fdi_pll function that we need to evetually move this to
>>> the pch/fdi enabling ...
>>
>> I don't understand. Why not just apply the current patch?
>
> We could move the call to enable_fdi_pll to the right place, where we
> enable all fdi/pch resources, instead of just the TU_SIZE write. Or do
> you think that's worse?

Our mode set sequence says the FDI PLL should be enabled way earlier
than the other FDI/PCH resources, and that's what we currently do, so
I believe it is currently being called at the "right place" or at
least close to the right place. It seems RX TU_SIZE enablement is not
part of the "FDI PLL enablement", but part of the "other FDI/PCH
resources" enablement (at least that's that the HSW mode set sequence
says), and that's why I agree with the patch.

(I have the feeling I am trying to explain to you why your patch is correct...)

Well, it's your patch, your choice :)

> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



-- 
Paulo Zanoni