From: Daniel Vetter <daniel.vetter@ffwll.ch>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time
Date: Sat, 27 Oct 2012 15:04:19 +0200 [thread overview]
Message-ID: <CAKMK7uEL19w_Ab9kJFXbiEd4DWqVw0NuYYvJYijikWeKiiviGA@mail.gmail.com> (raw)
In-Reply-To: <CA+gsUGQUEWo3Pqp6rgfXpFNsnu4nVBw5i7F=GhqcxJDM6X1aBQ@mail.gmail.com>
On Sat, Oct 27, 2012 at 3:03 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> 2012/10/27 Daniel Vetter <daniel.vetter@ffwll.ch>:
>> On Sat, Oct 27, 2012 at 1:51 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
>>> 2012/10/26 Daniel Vetter <daniel.vetter@ffwll.ch>:
>>>> According to "Graphics BSpec: vol4g North Display Engine Registers [IVB],
>>>> Display Mode Set Sequence" We need to write the TU size register
>>>> of the fdi RX unit _before_ starting to train the link.
>>>
>>> Well, we are still writing it before training the link, but it's
>>> waaaaay before :)
>>> But I agree with the patch, it makes the code look more like our mode
>>> set sequence docs.
>>
>> Indeed, I've confused myself with the placement of the fdi pll code
>> quite a bit. I think that's actually a remnant of the pre-modeset
>> world, where we could potentially enter the modeset functions with
>> unknown states. I think I'll keep things as-is, and instead add a
>> comment to the fdi_pll function that we need to evetually move this to
>> the pch/fdi enabling ...
>
> I don't understand. Why not just apply the current patch?
We could move the call to enable_fdi_pll to the right place, where we
enable all fdi/pch resources, instead of just the TU_SIZE write. Or do
you think that's worse?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2012-10-27 13:04 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-26 8:58 [PATCH 0/9] some ivb fdi b/c fixes Daniel Vetter
2012-10-26 8:58 ` [PATCH 1/9] drm/i915: shut up spurious message in intel_dp_get_hw_state Daniel Vetter
2012-10-26 14:01 ` Paulo Zanoni
2012-10-26 8:58 ` [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time Daniel Vetter
2012-10-27 11:51 ` Paulo Zanoni
2012-10-27 12:59 ` Daniel Vetter
2012-10-27 13:03 ` Paulo Zanoni
2012-10-27 13:04 ` Daniel Vetter [this message]
2012-10-27 13:18 ` Paulo Zanoni
2012-10-27 13:50 ` Daniel Vetter
2012-10-27 13:20 ` [PATCH] " Daniel Vetter
2012-10-26 8:58 ` [PATCH 3/9] drm/i915: set FDI_RX_MISC to recommended values on CPT/PPT Daniel Vetter
2012-10-27 12:02 ` Paulo Zanoni
2012-10-26 8:58 ` [PATCH 4/9] drm/i915: add comment about pch pll enabling rules Daniel Vetter
2012-10-27 12:15 ` Paulo Zanoni
2012-10-27 12:57 ` Daniel Vetter
2012-10-27 16:46 ` [PATCH] " Daniel Vetter
2012-10-29 12:02 ` Paulo Zanoni
2012-10-26 8:58 ` [PATCH 5/9] drm/i915: CPT/PPT pch dp transcoder workaround Daniel Vetter
2012-10-26 14:21 ` Paulo Zanoni
2012-10-29 15:38 ` Daniel Vetter
2012-10-29 17:02 ` Paulo Zanoni
2012-10-29 17:14 ` Daniel Vetter
2012-10-31 17:41 ` Paulo Zanoni
2012-10-26 8:58 ` [PATCH 6/9] drm/i915: BUG on impossible pch dp port Daniel Vetter
2012-10-26 15:04 ` Paulo Zanoni
2012-10-26 8:58 ` [PATCH 7/9] drm/i915: drop unnecessary check from fdi_link_train code Daniel Vetter
2012-10-26 15:32 ` Paulo Zanoni
2012-10-26 8:58 ` [PATCH 8/9] drm/i915: add ->display.modeset_global_resources callback Daniel Vetter
2012-10-27 12:18 ` Paulo Zanoni
2012-10-26 8:58 ` [PATCH 9/9] drm/i915: check fdi B/C lane sharing constraint Daniel Vetter
2012-10-27 12:56 ` Paulo Zanoni
2012-10-27 13:03 ` Daniel Vetter
2012-10-27 13:58 ` [PATCH] " Daniel Vetter
2012-10-29 12:06 ` Paulo Zanoni
2012-10-29 17:42 ` Daniel Vetter
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