* [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes
@ 2023-03-20 16:59 Jouni Högander
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Unify pre/post hooks Jouni Högander
` (8 more replies)
0 siblings, 9 replies; 17+ messages in thread
From: Jouni Högander @ 2023-03-20 16:59 UTC (permalink / raw)
To: intel-gfx
Fix/adjust Wa_16013835468 and Wa_14015648006. Implement Wa_1136 and
check for vblank being long enough for psr2.
v3:
- apply Wa_16013835468 for icl as well
- set/clear chicken bit in post plane update
- Unify pre/post hooks
v2: Implement Wa_1136
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Jouni Högander (4):
drm/i915/psr: Unify pre/post hooks
drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006
drm/i915/psr: Check that vblank is long enough for psr2
drm/i915/psr: Implement Display WA #1136
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 94 +++++++++++++------
drivers/gpu/drm/i915/display/skl_watermark.c | 6 +-
3 files changed, 70 insertions(+), 31 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Unify pre/post hooks
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
@ 2023-03-20 16:59 ` Jouni Högander
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006 Jouni Högander
` (7 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Jouni Högander @ 2023-03-20 16:59 UTC (permalink / raw)
To: intel-gfx
pre/post hooks are doing thing differently. Unify them.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 31084d95711d..8dbf452d63c2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1954,23 +1954,22 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_psr *psr = &intel_dp->psr;
+ bool keep_disabled = false;
mutex_lock(&psr->lock);
- if (psr->sink_not_reliable)
- goto exit;
-
drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes);
- /* Only enable if there is active planes */
- if (!psr->enabled && crtc_state->active_planes)
+ keep_disabled |= psr->sink_not_reliable;
+ keep_disabled |= !crtc_state->active_planes;
+
+ if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
if (crtc_state->crc_enabled && psr->enabled)
psr_force_hw_tracking_exit(intel_dp);
-exit:
mutex_unlock(&psr->lock);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Unify pre/post hooks Jouni Högander
@ 2023-03-20 16:59 ` Jouni Högander
2023-03-21 15:34 ` Ville Syrjälä
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2 Jouni Högander
` (6 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Jouni Högander @ 2023-03-20 16:59 UTC (permalink / raw)
To: intel-gfx
PSR WM optimization should be disabled based on any wm level being
disabled. Currently it's disabled always when using delayed vblank.
Also same WA should be applied for ICL as well
Bspec: 71580
v2:
- set/clear chicken bit in post_plane_update
- apply for ICL as well
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 67 ++++++++++++-------
drivers/gpu/drm/i915/display/skl_watermark.c | 7 +-
3 files changed, 50 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c32bfba06ca1..60504c390408 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1152,6 +1152,7 @@ struct intel_crtc_state {
bool has_psr2;
bool enable_psr2_sel_fetch;
bool req_psr2_sdp_prior_scanline;
+ bool wm_level_disabled;
u32 dc3co_exitline;
u16 su_y_granularity;
struct drm_dp_vsc_sdp psr_vsc;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8dbf452d63c2..1050d777a108 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1173,18 +1173,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
intel_dp->psr.psr2_sel_fetch_enabled ?
IGNORE_PSR2_HW_TRACKING : 0);
- /*
- * Wa_16013835468
- * Wa_14015648006
- */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
- IS_DISPLAY_VER(dev_priv, 12, 13)) {
- if (crtc_state->hw.adjusted_mode.crtc_vblank_start !=
- crtc_state->hw.adjusted_mode.crtc_vdisplay)
- intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
- wa_16013835468_bit_get(intel_dp));
- }
-
if (intel_dp->psr.psr2_enabled) {
if (DISPLAY_VER(dev_priv) == 9)
intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
@@ -1362,7 +1350,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
* Wa_14015648006
*/
if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
- IS_DISPLAY_VER(dev_priv, 12, 13))
+ IS_DISPLAY_VER(dev_priv, 11, 13))
intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
wa_16013835468_bit_get(intel_dp), 0);
@@ -1941,33 +1929,64 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
}
}
+/*
+ * Wa_16013835468
+ * Wa_14015648006
+ */
+static void wa_16013835468(struct intel_dp *intel_dp, bool wm_level_disabled)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (!IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
+ !IS_DISPLAY_VER(dev_priv, 11, 13))
+ return;
+
+ if (intel_dp->psr.enabled && wm_level_disabled)
+ intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
+ wa_16013835468_bit_get(intel_dp));
+ else
+ intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
+ wa_16013835468_bit_get(intel_dp), 0);
+}
+
static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
- const struct intel_crtc_state *crtc_state)
+ const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_encoder *encoder;
- if (!crtc_state->has_psr)
+ if (!new_crtc_state->has_psr)
return;
for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
- crtc_state->uapi.encoder_mask) {
+ new_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_psr *psr = &intel_dp->psr;
bool keep_disabled = false;
mutex_lock(&psr->lock);
- drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes);
+ drm_WARN_ON(&dev_priv->drm, psr->enabled &&
+ !new_crtc_state->active_planes);
keep_disabled |= psr->sink_not_reliable;
- keep_disabled |= !crtc_state->active_planes;
+ keep_disabled |= !new_crtc_state->active_planes;
if (!psr->enabled && !keep_disabled)
- intel_psr_enable_locked(intel_dp, crtc_state);
+ intel_psr_enable_locked(intel_dp, new_crtc_state);
+
+ /*
+ * Wa_16013835468
+ * Wa_14015648006
+ */
+ if (old_crtc_state->wm_level_disabled !=
+ new_crtc_state->wm_level_disabled)
+ wa_16013835468(intel_dp,
+ new_crtc_state->wm_level_disabled);
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
- if (crtc_state->crc_enabled && psr->enabled)
+ if (new_crtc_state->crc_enabled && psr->enabled)
psr_force_hw_tracking_exit(intel_dp);
mutex_unlock(&psr->lock);
@@ -1977,15 +1996,17 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
void intel_psr_post_plane_update(const struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_crtc_state *crtc_state;
+ struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_crtc *crtc;
int i;
if (!HAS_PSR(dev_priv))
return;
- for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
- _intel_psr_post_plane_update(state, crtc_state);
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i)
+ _intel_psr_post_plane_update(state, old_crtc_state,
+ new_crtc_state);
}
static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 50a9a6adbe32..afb751c024ba 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2273,9 +2273,12 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
return level;
/*
- * FIXME PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
+ * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
* based on whether we're limited by the vblank duration.
- *
+ */
+ crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
+
+ /*
* FIXME also related to skl+ w/a 1136 (also unimplemented as of
* now) perhaps?
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Unify pre/post hooks Jouni Högander
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006 Jouni Högander
@ 2023-03-20 16:59 ` Jouni Högander
2023-03-21 15:43 ` Ville Syrjälä
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 4/4] drm/i915/psr: Implement Display WA #1136 Jouni Högander
` (5 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Jouni Högander @ 2023-03-20 16:59 UTC (permalink / raw)
To: intel-gfx
Ensure vblank >= psr2 vblank
where
Psr2 vblank = PSR2_CTL Block Count Number maximum line count.
Bspec: 71580, 49274
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1050d777a108..1b40d9c73c18 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -958,6 +958,14 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
+ /* Vblank >= PSR2_CTL Block Count Number maximum line count */
+ if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
+ crtc_state->hw.adjusted_mode.crtc_vblank_start < 12) {
+ drm_dbg_kms(&dev_priv->drm,
+ "PSR2 not enabled, too short vblank time\n");
+ return false;
+ }
+
if (HAS_PSR2_SEL_FETCH(dev_priv)) {
if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
!HAS_PSR_HW_TRACKING(dev_priv)) {
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v3 4/4] drm/i915/psr: Implement Display WA #1136
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
` (2 preceding siblings ...)
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2 Jouni Högander
@ 2023-03-20 16:59 ` Jouni Högander
2023-03-21 5:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for High refresh rate PSR fixes (rev3) Patchwork
` (4 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Jouni Högander @ 2023-03-20 16:59 UTC (permalink / raw)
To: intel-gfx
Implement Display WA #1136 for SKL/BXT.
Bspec: 21664
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/skl_watermark.c | 5 -----
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1b40d9c73c18..ad058b67f4f8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1940,11 +1940,18 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
/*
* Wa_16013835468
* Wa_14015648006
+ * Display WA #1136: skl, bxt
*/
static void wa_16013835468(struct intel_dp *intel_dp, bool wm_level_disabled)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ if (DISPLAY_VER(dev_priv) <= 9 && wm_level_disabled &&
+ intel_dp->psr.enabled) {
+ intel_psr_disable_locked(intel_dp);
+ return;
+ }
+
if (!IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
!IS_DISPLAY_VER(dev_priv, 11, 13))
return;
@@ -1981,12 +1988,17 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
keep_disabled |= psr->sink_not_reliable;
keep_disabled |= !new_crtc_state->active_planes;
+ /* Display WA #1136: skl, bxt */
+ keep_disabled |= DISPLAY_VER(dev_priv) <= 9 &&
+ new_crtc_state->wm_level_disabled;
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, new_crtc_state);
/*
* Wa_16013835468
* Wa_14015648006
+ * Display WA #1136: skl, bxt
*/
if (old_crtc_state->wm_level_disabled !=
new_crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index afb751c024ba..ced61da8b496 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2278,11 +2278,6 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
*/
crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
- /*
- * FIXME also related to skl+ w/a 1136 (also unimplemented as of
- * now) perhaps?
- */
-
for (level++; level < i915->display.wm.num_levels; level++) {
enum plane_id plane_id;
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for High refresh rate PSR fixes (rev3)
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
` (3 preceding siblings ...)
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 4/4] drm/i915/psr: Implement Display WA #1136 Jouni Högander
@ 2023-03-21 5:24 ` Patchwork
2023-03-21 5:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-03-21 5:24 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
== Series Details ==
Series: High refresh rate PSR fixes (rev3)
URL : https://patchwork.freedesktop.org/series/115109/
State : warning
== Summary ==
Error: git fetch origin failed
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for High refresh rate PSR fixes (rev3)
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
` (4 preceding siblings ...)
2023-03-21 5:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for High refresh rate PSR fixes (rev3) Patchwork
@ 2023-03-21 5:24 ` Patchwork
2023-03-21 5:24 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-03-21 5:24 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
== Series Details ==
Series: High refresh rate PSR fixes (rev3)
URL : https://patchwork.freedesktop.org/series/115109/
State : warning
== Summary ==
Error: git fetch origin failed
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for High refresh rate PSR fixes (rev3)
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
` (5 preceding siblings ...)
2023-03-21 5:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-03-21 5:24 ` Patchwork
2023-03-21 5:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-21 9:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-03-21 5:24 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
== Series Details ==
Series: High refresh rate PSR fixes (rev3)
URL : https://patchwork.freedesktop.org/series/115109/
State : warning
== Summary ==
Error: git fetch origin failed
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for High refresh rate PSR fixes (rev3)
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
` (6 preceding siblings ...)
2023-03-21 5:24 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2023-03-21 5:36 ` Patchwork
2023-03-21 9:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-03-21 5:36 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3037 bytes --]
== Series Details ==
Series: High refresh rate PSR fixes (rev3)
URL : https://patchwork.freedesktop.org/series/115109/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12884 -> Patchwork_115109v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/index.html
Participating hosts (35 -> 34)
------------------------------
Missing (1): bat-dg1-6
Known issues
------------
Here are the changes found in Patchwork_115109v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_lrc:
- bat-adln-1: [PASS][1] -> [INCOMPLETE][2] ([i915#7609])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/bat-adln-1/igt@i915_selftest@live@gt_lrc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/bat-adln-1/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- bat-atsm-1: [PASS][3] -> [INCOMPLETE][4] ([i915#7913])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/bat-atsm-1/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/bat-atsm-1/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@migrate:
- bat-adlp-9: [PASS][5] -> [DMESG-FAIL][6] ([i915#7699])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/bat-adlp-9/igt@i915_selftest@live@migrate.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/bat-adlp-9/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][7] -> [ABORT][8] ([i915#7911])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/bat-rpls-1/igt@i915_selftest@live@requests.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/bat-rpls-1/igt@i915_selftest@live@requests.html
[i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
Build changes
-------------
* Linux: CI_DRM_12884 -> Patchwork_115109v3
CI-20190529: 20190529
CI_DRM_12884: 1d4054731cfcb1cb9810d309b70535ae0b90ecf0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7208: f327c5d77b6ea6adff1ef6d08f21f232dfe093e3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115109v3: 1d4054731cfcb1cb9810d309b70535ae0b90ecf0 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
80e72ec7f1e1 drm/i915/psr: Implement Display WA #1136
278f96a25a07 drm/i915/psr: Check that vblank is long enough for psr2
1b026ad21bc9 drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006
acd5086f3530 drm/i915/psr: Unify pre/post hooks
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/index.html
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for High refresh rate PSR fixes (rev3)
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
` (7 preceding siblings ...)
2023-03-21 5:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-03-21 9:08 ` Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-03-21 9:08 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 20947 bytes --]
== Series Details ==
Series: High refresh rate PSR fixes (rev3)
URL : https://patchwork.freedesktop.org/series/115109/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12884_full -> Patchwork_115109v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-rkl0
Known issues
------------
Here are the changes found in Patchwork_115109v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [PASS][1] -> [ABORT][2] ([i915#180])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-apl2/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-apl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
#### Possible fixes ####
* igt@device_reset@unbind-reset-rebind:
- {shard-rkl}: [FAIL][5] ([i915#4778]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-5/igt@device_reset@unbind-reset-rebind.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-3/igt@device_reset@unbind-reset-rebind.html
* igt@drm_fdinfo@virtual-idle:
- {shard-rkl}: [FAIL][7] ([i915#7742]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-4/igt@drm_fdinfo@virtual-idle.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-6/igt@drm_fdinfo@virtual-idle.html
* {igt@gem_barrier_race@remote-request@rcs0}:
- {shard-tglu}: [ABORT][9] ([i915#8211]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-tglu-9/igt@gem_barrier_race@remote-request@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-tglu-9/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}: [FAIL][11] ([i915#6268]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-3/igt@gem_ctx_exec@basic-nohangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@smoketest:
- {shard-tglu}: [FAIL][13] ([i915#5099]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-tglu-6/igt@gem_ctx_persistence@smoketest.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-tglu-8/igt@gem_ctx_persistence@smoketest.html
* igt@gem_exec_balancer@fairslice:
- {shard-rkl}: [SKIP][15] ([i915#6259]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-5/igt@gem_exec_balancer@fairslice.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-3/igt@gem_exec_balancer@fairslice.html
* igt@gem_exec_fair@basic-pace@rcs0:
- {shard-rkl}: [FAIL][17] ([i915#2842]) -> [PASS][18] +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-6/igt@gem_exec_fair@basic-pace@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_reloc@basic-write-read-noreloc:
- {shard-rkl}: [SKIP][19] ([i915#3281]) -> [PASS][20] +7 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-6/igt@gem_exec_reloc@basic-write-read-noreloc.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- {shard-tglu}: [ABORT][21] ([i915#7975]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-tglu-9/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_mmap_gtt@basic-small-bo:
- {shard-rkl}: [SKIP][23] ([fdo#109315]) -> [PASS][24] +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-5/igt@gem_mmap_gtt@basic-small-bo.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-3/igt@gem_mmap_gtt@basic-small-bo.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- {shard-rkl}: [SKIP][25] ([i915#3282]) -> [PASS][26] +5 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-2/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gen9_exec_parse@bb-start-out:
- {shard-rkl}: [SKIP][27] ([i915#2527]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-6/igt@gen9_exec_parse@bb-start-out.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-5/igt@gen9_exec_parse@bb-start-out.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-tglu}: [FAIL][29] ([i915#3989] / [i915#454]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-tglu-7/igt@i915_pm_dc@dc6-dpms.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-tglu-4/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-rkl}: [SKIP][31] ([i915#1397]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-4/igt@i915_pm_rpm@dpms-lpsp.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-6/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-tglu}: [SKIP][33] ([i915#1397]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-tglu-10/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-tglu-4/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@system-suspend-modeset:
- {shard-rkl}: [SKIP][35] ([fdo#109308]) -> [PASS][36] +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-2/igt@i915_pm_rpm@system-suspend-modeset.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-6/igt@i915_pm_rpm@system-suspend-modeset.html
* {igt@i915_power@sanity}:
- {shard-rkl}: [SKIP][37] ([i915#7984]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-2/igt@i915_power@sanity.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-5/igt@i915_power@sanity.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- {shard-rkl}: [SKIP][39] ([i915#1845] / [i915#4098]) -> [PASS][40] +32 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-2/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
- {shard-tglu}: [SKIP][41] ([i915#1845]) -> [PASS][42] +38 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-tglu-10/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-tglu-8/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- {shard-rkl}: [SKIP][43] ([i915#1849] / [i915#4098]) -> [PASS][44] +16 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
- {shard-tglu}: [SKIP][45] ([i915#1849]) -> [PASS][46] +6 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-tglu-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-tglu-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
* {igt@kms_plane@invalid-pixel-format-settings}:
- {shard-rkl}: [SKIP][47] ([i915#8152]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-4/igt@kms_plane@invalid-pixel-format-settings.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-6/igt@kms_plane@invalid-pixel-format-settings.html
* igt@kms_psr@primary_mmap_cpu:
- {shard-rkl}: [SKIP][49] ([i915#1072]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-4/igt@kms_psr@primary_mmap_cpu.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-6/igt@kms_psr@primary_mmap_cpu.html
* igt@perf_pmu@idle@rcs0:
- {shard-rkl}: [FAIL][51] ([i915#4349]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-4/igt@perf_pmu@idle@rcs0.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-3/igt@perf_pmu@idle@rcs0.html
* igt@prime_vgem@basic-fence-flip:
- {shard-rkl}: [SKIP][53] ([fdo#109295] / [i915#3708] / [i915#4098]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-2/igt@prime_vgem@basic-fence-flip.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-write:
- {shard-rkl}: [SKIP][55] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-2/igt@prime_vgem@basic-write.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-5/igt@prime_vgem@basic-write.html
* igt@prime_vgem@coherency-gtt:
- {shard-rkl}: [SKIP][57] ([fdo#109295] / [fdo#111656] / [i915#3708]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-6/igt@prime_vgem@coherency-gtt.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-5/igt@prime_vgem@coherency-gtt.html
* igt@syncobj_timeline@invalid-multi-wait-all-unsubmitted-submitted-signaled:
- {shard-rkl}: [SKIP][59] ([i915#2575]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-rkl-5/igt@syncobj_timeline@invalid-multi-wait-all-unsubmitted-submitted-signaled.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-rkl-3/igt@syncobj_timeline@invalid-multi-wait-all-unsubmitted-submitted-signaled.html
* igt@sysfs_heartbeat_interval@precise@vcs1:
- {shard-dg1}: [FAIL][61] ([i915#1755]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12884/shard-dg1-15/igt@sysfs_heartbeat_interval@precise@vcs1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/shard-dg1-12/igt@sysfs_heartbeat_interval@precise@vcs1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4778]: https://gitlab.freedesktop.org/drm/intel/issues/4778
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7330]: https://gitlab.freedesktop.org/drm/intel/issues/7330
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7811]: https://gitlab.freedesktop.org/drm/intel/issues/7811
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8282]: https://gitlab.freedesktop.org/drm/intel/issues/8282
Build changes
-------------
* Linux: CI_DRM_12884 -> Patchwork_115109v3
CI-20190529: 20190529
CI_DRM_12884: 1d4054731cfcb1cb9810d309b70535ae0b90ecf0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7208: f327c5d77b6ea6adff1ef6d08f21f232dfe093e3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115109v3: 1d4054731cfcb1cb9810d309b70535ae0b90ecf0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115109v3/index.html
[-- Attachment #2: Type: text/html, Size: 16791 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006 Jouni Högander
@ 2023-03-21 15:34 ` Ville Syrjälä
2023-03-21 15:57 ` Hogander, Jouni
0 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjälä @ 2023-03-21 15:34 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
On Mon, Mar 20, 2023 at 06:59:43PM +0200, Jouni Högander wrote:
> PSR WM optimization should be disabled based on any wm level being
> disabled. Currently it's disabled always when using delayed vblank.
> Also same WA should be applied for ICL as well
>
> Bspec: 71580
>
> v2:
> - set/clear chicken bit in post_plane_update
> - apply for ICL as well
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 67 ++++++++++++-------
> drivers/gpu/drm/i915/display/skl_watermark.c | 7 +-
> 3 files changed, 50 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c32bfba06ca1..60504c390408 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1152,6 +1152,7 @@ struct intel_crtc_state {
> bool has_psr2;
> bool enable_psr2_sel_fetch;
> bool req_psr2_sdp_prior_scanline;
> + bool wm_level_disabled;
> u32 dc3co_exitline;
> u16 su_y_granularity;
> struct drm_dp_vsc_sdp psr_vsc;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8dbf452d63c2..1050d777a108 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1173,18 +1173,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> intel_dp->psr.psr2_sel_fetch_enabled ?
> IGNORE_PSR2_HW_TRACKING : 0);
>
> - /*
> - * Wa_16013835468
> - * Wa_14015648006
> - */
> - if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> - IS_DISPLAY_VER(dev_priv, 12, 13)) {
> - if (crtc_state->hw.adjusted_mode.crtc_vblank_start !=
> - crtc_state->hw.adjusted_mode.crtc_vdisplay)
> - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> - wa_16013835468_bit_get(intel_dp));
> - }
> -
> if (intel_dp->psr.psr2_enabled) {
> if (DISPLAY_VER(dev_priv) == 9)
> intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
> @@ -1362,7 +1350,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> * Wa_14015648006
> */
> if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> - IS_DISPLAY_VER(dev_priv, 12, 13))
> + IS_DISPLAY_VER(dev_priv, 11, 13))
> intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> wa_16013835468_bit_get(intel_dp), 0);
>
> @@ -1941,33 +1929,64 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> }
> }
>
> +/*
> + * Wa_16013835468
> + * Wa_14015648006
> + */
> +static void wa_16013835468(struct intel_dp *intel_dp, bool wm_level_disabled)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (!IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
> + !IS_DISPLAY_VER(dev_priv, 11, 13))
> + return;
This is still confusing the two different workarounds,
and actually losing the one about the delayed vblank.
> +
> + if (intel_dp->psr.enabled && wm_level_disabled)
> + intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> + wa_16013835468_bit_get(intel_dp));
> + else
> + intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> + wa_16013835468_bit_get(intel_dp), 0);
> +}
> +
> static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
> - const struct intel_crtc_state *crtc_state)
> + const struct intel_crtc_state *old_crtc_state,
> + const struct intel_crtc_state *new_crtc_state)
The rename reduces the signal-to-noise ratio near zero.
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_encoder *encoder;
>
> - if (!crtc_state->has_psr)
> + if (!new_crtc_state->has_psr)
> return;
>
> for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> - crtc_state->uapi.encoder_mask) {
> + new_crtc_state->uapi.encoder_mask) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> struct intel_psr *psr = &intel_dp->psr;
> bool keep_disabled = false;
>
> mutex_lock(&psr->lock);
>
> - drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes);
> + drm_WARN_ON(&dev_priv->drm, psr->enabled &&
> + !new_crtc_state->active_planes);
>
> keep_disabled |= psr->sink_not_reliable;
> - keep_disabled |= !crtc_state->active_planes;
> + keep_disabled |= !new_crtc_state->active_planes;
>
> if (!psr->enabled && !keep_disabled)
> - intel_psr_enable_locked(intel_dp, crtc_state);
> + intel_psr_enable_locked(intel_dp, new_crtc_state);
> +
> + /*
> + * Wa_16013835468
> + * Wa_14015648006
> + */
> + if (old_crtc_state->wm_level_disabled !=
> + new_crtc_state->wm_level_disabled)
> + wa_16013835468(intel_dp,
> + new_crtc_state->wm_level_disabled);
>
> /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
> - if (crtc_state->crc_enabled && psr->enabled)
> + if (new_crtc_state->crc_enabled && psr->enabled)
> psr_force_hw_tracking_exit(intel_dp);
>
> mutex_unlock(&psr->lock);
> @@ -1977,15 +1996,17 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
> void intel_psr_post_plane_update(const struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct intel_crtc_state *crtc_state;
> + struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> struct intel_crtc *crtc;
> int i;
>
> if (!HAS_PSR(dev_priv))
> return;
>
> - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
> - _intel_psr_post_plane_update(state, crtc_state);
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i)
> + _intel_psr_post_plane_update(state, old_crtc_state,
> + new_crtc_state);
> }
>
> static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 50a9a6adbe32..afb751c024ba 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2273,9 +2273,12 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
> return level;
>
> /*
> - * FIXME PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
> + * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
> * based on whether we're limited by the vblank duration.
> - *
> + */
> + crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
> +
> + /*
> * FIXME also related to skl+ w/a 1136 (also unimplemented as of
> * now) perhaps?
> */
> --
> 2.34.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2 Jouni Högander
@ 2023-03-21 15:43 ` Ville Syrjälä
2023-03-21 16:14 ` Hogander, Jouni
0 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjälä @ 2023-03-21 15:43 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx
On Mon, Mar 20, 2023 at 06:59:44PM +0200, Jouni Högander wrote:
> Ensure vblank >= psr2 vblank
> where
> Psr2 vblank = PSR2_CTL Block Count Number maximum line count.
>
> Bspec: 71580, 49274
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1050d777a108..1b40d9c73c18 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -958,6 +958,14 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> return false;
> }
>
> + /* Vblank >= PSR2_CTL Block Count Number maximum line count */
> + if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
> + crtc_state->hw.adjusted_mode.crtc_vblank_start < 12) {
Why 12? Shouldn't it be based on the wake_lines/BLOCK_COUNT_NUM stuff?
If so I would suggest we try someting like this:
psr2_block_count_lines()
{
return ...wake_lines... ? 12 : 8;
}
psr2_block_count()
{
return psr2_block_count_lines() / 4;
}
if (vblank_lengh < psr2_block_count_lines())
fail;
if (psr_block_count() > 2)
val |= BLOCK_COUNT_NUM_3;
else
val |= BLOCK_COUNT_NUM_2;
> + drm_dbg_kms(&dev_priv->drm,
> + "PSR2 not enabled, too short vblank time\n");
> + return false;
> + }
> +
> if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
> !HAS_PSR_HW_TRACKING(dev_priv)) {
> --
> 2.34.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006
2023-03-21 15:34 ` Ville Syrjälä
@ 2023-03-21 15:57 ` Hogander, Jouni
2023-03-21 16:19 ` Ville Syrjälä
0 siblings, 1 reply; 17+ messages in thread
From: Hogander, Jouni @ 2023-03-21 15:57 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
Thank you Ville for checking my patch. Please see my responses below.
On Tue, 2023-03-21 at 17:34 +0200, Ville Syrjälä wrote:
> On Mon, Mar 20, 2023 at 06:59:43PM +0200, Jouni Högander wrote:
> > PSR WM optimization should be disabled based on any wm level being
> > disabled. Currently it's disabled always when using delayed vblank.
> > Also same WA should be applied for ICL as well
> >
> > Bspec: 71580
> >
> > v2:
> > - set/clear chicken bit in post_plane_update
> > - apply for ICL as well
> >
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 1 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 67 ++++++++++++---
> > ----
> > drivers/gpu/drm/i915/display/skl_watermark.c | 7 +-
> > 3 files changed, 50 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c32bfba06ca1..60504c390408 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1152,6 +1152,7 @@ struct intel_crtc_state {
> > bool has_psr2;
> > bool enable_psr2_sel_fetch;
> > bool req_psr2_sdp_prior_scanline;
> > + bool wm_level_disabled;
> > u32 dc3co_exitline;
> > u16 su_y_granularity;
> > struct drm_dp_vsc_sdp psr_vsc;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 8dbf452d63c2..1050d777a108 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1173,18 +1173,6 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> > intel_dp->psr.psr2_sel_fetch_enabled ?
> > IGNORE_PSR2_HW_TRACKING : 0);
> >
> > - /*
> > - * Wa_16013835468
> > - * Wa_14015648006
> > - */
> > - if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > - IS_DISPLAY_VER(dev_priv, 12, 13)) {
> > - if (crtc_state->hw.adjusted_mode.crtc_vblank_start
> > !=
> > - crtc_state->hw.adjusted_mode.crtc_vdisplay)
> > - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> > 0,
> > -
> > wa_16013835468_bit_get(intel_dp));
> > - }
> > -
> > if (intel_dp->psr.psr2_enabled) {
> > if (DISPLAY_VER(dev_priv) == 9)
> > intel_de_rmw(dev_priv,
> > CHICKEN_TRANS(cpu_transcoder), 0,
> > @@ -1362,7 +1350,7 @@ static void intel_psr_disable_locked(struct
> > intel_dp *intel_dp)
> > * Wa_14015648006
> > */
> > if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > - IS_DISPLAY_VER(dev_priv, 12, 13))
> > + IS_DISPLAY_VER(dev_priv, 11, 13))
> > intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> > wa_16013835468_bit_get(intel_dp), 0);
> >
> > @@ -1941,33 +1929,64 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> > }
> > }
> >
> > +/*
> > + * Wa_16013835468
> > + * Wa_14015648006
> > + */
> > +static void wa_16013835468(struct intel_dp *intel_dp, bool
> > wm_level_disabled)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > + if (!IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
> > + !IS_DISPLAY_VER(dev_priv, 11, 13))
> > + return;
>
> This is still confusing the two different workarounds,
> and actually losing the one about the delayed vblank.
This is only one Wa. There are two lineage numbers describing same
workaround.
Can you please point me out the delayed vblank wa description? I can't
find it from Bspec? Original implementation is referring lineages
1601383546 and 14015648006. Neither of these are about delayed vblank
specifically.
>
> > +
> > + if (intel_dp->psr.enabled && wm_level_disabled)
> > + intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> > + wa_16013835468_bit_get(intel_dp));
> > + else
> > + intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> > + wa_16013835468_bit_get(intel_dp), 0);
> > +}
> > +
> > static void _intel_psr_post_plane_update(const struct
> > intel_atomic_state *state,
> > - const struct
> > intel_crtc_state *crtc_state)
> > + const struct
> > intel_crtc_state *old_crtc_state,
> > + const struct
> > intel_crtc_state *new_crtc_state)
>
> The rename reduces the signal-to-noise ratio near zero.
Can you please elaborate this a bit more? What would you suggest? I
need to use both, old and new state to detect difference in
wm_level_disabled. I want to set/clear the chicken bit only when
necessary.
>
> > {
> > struct drm_i915_private *dev_priv = to_i915(state-
> > >base.dev);
> > struct intel_encoder *encoder;
> >
> > - if (!crtc_state->has_psr)
> > + if (!new_crtc_state->has_psr)
> > return;
> >
> > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > encoder,
> > - crtc_state-
> > >uapi.encoder_mask) {
> > + new_crtc_state-
> > >uapi.encoder_mask) {
> > struct intel_dp *intel_dp =
> > enc_to_intel_dp(encoder);
> > struct intel_psr *psr = &intel_dp->psr;
> > bool keep_disabled = false;
> >
> > mutex_lock(&psr->lock);
> >
> > - drm_WARN_ON(&dev_priv->drm, psr->enabled &&
> > !crtc_state->active_planes);
> > + drm_WARN_ON(&dev_priv->drm, psr->enabled &&
> > + !new_crtc_state->active_planes);
> >
> > keep_disabled |= psr->sink_not_reliable;
> > - keep_disabled |= !crtc_state->active_planes;
> > + keep_disabled |= !new_crtc_state->active_planes;
> >
> > if (!psr->enabled && !keep_disabled)
> > - intel_psr_enable_locked(intel_dp,
> > crtc_state);
> > + intel_psr_enable_locked(intel_dp,
> > new_crtc_state);
> > +
> > + /*
> > + * Wa_16013835468
> > + * Wa_14015648006
> > + */
> > + if (old_crtc_state->wm_level_disabled !=
> > + new_crtc_state->wm_level_disabled)
> > + wa_16013835468(intel_dp,
> > + new_crtc_state-
> > >wm_level_disabled);
> >
> > /* Force a PSR exit when enabling CRC to avoid CRC
> > timeouts */
> > - if (crtc_state->crc_enabled && psr->enabled)
> > + if (new_crtc_state->crc_enabled && psr->enabled)
> > psr_force_hw_tracking_exit(intel_dp);
> >
> > mutex_unlock(&psr->lock);
> > @@ -1977,15 +1996,17 @@ static void
> > _intel_psr_post_plane_update(const struct intel_atomic_state
> > *state,
> > void intel_psr_post_plane_update(const struct intel_atomic_state
> > *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state-
> > >base.dev);
> > - struct intel_crtc_state *crtc_state;
> > + struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > struct intel_crtc *crtc;
> > int i;
> >
> > if (!HAS_PSR(dev_priv))
> > return;
> >
> > - for_each_new_intel_crtc_in_state(state, crtc, crtc_state,
> > i)
> > - _intel_psr_post_plane_update(state, crtc_state);
> > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > + new_crtc_state, i)
> > + _intel_psr_post_plane_update(state, old_crtc_state,
> > + new_crtc_state);
> > }
> >
> > static int _psr2_ready_for_pipe_update_locked(struct intel_dp
> > *intel_dp)
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index 50a9a6adbe32..afb751c024ba 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -2273,9 +2273,12 @@ static int skl_wm_check_vblank(struct
> > intel_crtc_state *crtc_state)
> > return level;
> >
> > /*
> > - * FIXME PSR needs to toggle
> > LATENCY_REPORTING_REMOVED_PIPE_*
> > + * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
> > * based on whether we're limited by the vblank duration.
> > - *
> > + */
> > + crtc_state->wm_level_disabled = level < i915-
> > >display.wm.num_levels - 1;
> > +
> > + /*
> > * FIXME also related to skl+ w/a 1136 (also unimplemented
> > as of
> > * now) perhaps?
> > */
> > --
> > 2.34.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2
2023-03-21 15:43 ` Ville Syrjälä
@ 2023-03-21 16:14 ` Hogander, Jouni
2023-03-21 16:29 ` Ville Syrjälä
2023-03-21 16:41 ` Ville Syrjälä
0 siblings, 2 replies; 17+ messages in thread
From: Hogander, Jouni @ 2023-03-21 16:14 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Tue, 2023-03-21 at 17:43 +0200, Ville Syrjälä wrote:
> On Mon, Mar 20, 2023 at 06:59:44PM +0200, Jouni Högander wrote:
> > Ensure vblank >= psr2 vblank
> > where
> > Psr2 vblank = PSR2_CTL Block Count Number maximum line count.
> >
> > Bspec: 71580, 49274
> >
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 1050d777a108..1b40d9c73c18 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -958,6 +958,14 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> > return false;
> > }
> >
> > + /* Vblank >= PSR2_CTL Block Count Number maximum line count
> > */
> > + if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
> > + crtc_state->hw.adjusted_mode.crtc_vblank_start < 12) {
>
> Why 12? Shouldn't it be based on the wake_lines/BLOCK_COUNT_NUM
> stuff?
I took this directly from Bspec. I think your suggestions make sense. I
will experiment them and come back on this.
>
>
> If so I would suggest we try someting like this:
>
> psr2_block_count_lines()
> {
> return ...wake_lines... ? 12 : 8;
> }
>
> psr2_block_count()
> {
> return psr2_block_count_lines() / 4;
> }
>
> if (vblank_lengh < psr2_block_count_lines())
> fail;
>
> if (psr_block_count() > 2)
> val |= BLOCK_COUNT_NUM_3;
> else
> val |= BLOCK_COUNT_NUM_2;
>
> > + drm_dbg_kms(&dev_priv->drm,
> > + "PSR2 not enabled, too short vblank
> > time\n");
> > + return false;
> > + }
> > +
> > if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > if (!intel_psr2_sel_fetch_config_valid(intel_dp,
> > crtc_state) &&
> > !HAS_PSR_HW_TRACKING(dev_priv)) {
> > --
> > 2.34.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006
2023-03-21 15:57 ` Hogander, Jouni
@ 2023-03-21 16:19 ` Ville Syrjälä
0 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2023-03-21 16:19 UTC (permalink / raw)
To: Hogander, Jouni; +Cc: intel-gfx
On Tue, Mar 21, 2023 at 03:57:11PM +0000, Hogander, Jouni wrote:
> Thank you Ville for checking my patch. Please see my responses below.
>
> On Tue, 2023-03-21 at 17:34 +0200, Ville Syrjälä wrote:
> > On Mon, Mar 20, 2023 at 06:59:43PM +0200, Jouni Högander wrote:
> > > PSR WM optimization should be disabled based on any wm level being
> > > disabled. Currently it's disabled always when using delayed vblank.
> > > Also same WA should be applied for ICL as well
> > >
> > > Bspec: 71580
> > >
> > > v2:
> > > - set/clear chicken bit in post_plane_update
> > > - apply for ICL as well
> > >
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 1 +
> > > drivers/gpu/drm/i915/display/intel_psr.c | 67 ++++++++++++---
> > > ----
> > > drivers/gpu/drm/i915/display/skl_watermark.c | 7 +-
> > > 3 files changed, 50 insertions(+), 25 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index c32bfba06ca1..60504c390408 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1152,6 +1152,7 @@ struct intel_crtc_state {
> > > bool has_psr2;
> > > bool enable_psr2_sel_fetch;
> > > bool req_psr2_sdp_prior_scanline;
> > > + bool wm_level_disabled;
> > > u32 dc3co_exitline;
> > > u16 su_y_granularity;
> > > struct drm_dp_vsc_sdp psr_vsc;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 8dbf452d63c2..1050d777a108 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1173,18 +1173,6 @@ static void intel_psr_enable_source(struct
> > > intel_dp *intel_dp,
> > > intel_dp->psr.psr2_sel_fetch_enabled ?
> > > IGNORE_PSR2_HW_TRACKING : 0);
> > >
> > > - /*
> > > - * Wa_16013835468
> > > - * Wa_14015648006
> > > - */
> > > - if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > - IS_DISPLAY_VER(dev_priv, 12, 13)) {
> > > - if (crtc_state->hw.adjusted_mode.crtc_vblank_start
> > > !=
> > > - crtc_state->hw.adjusted_mode.crtc_vdisplay)
> > > - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> > > 0,
> > > -
> > > wa_16013835468_bit_get(intel_dp));
> > > - }
> > > -
> > > if (intel_dp->psr.psr2_enabled) {
> > > if (DISPLAY_VER(dev_priv) == 9)
> > > intel_de_rmw(dev_priv,
> > > CHICKEN_TRANS(cpu_transcoder), 0,
> > > @@ -1362,7 +1350,7 @@ static void intel_psr_disable_locked(struct
> > > intel_dp *intel_dp)
> > > * Wa_14015648006
> > > */
> > > if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > - IS_DISPLAY_VER(dev_priv, 12, 13))
> > > + IS_DISPLAY_VER(dev_priv, 11, 13))
> > > intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> > > wa_16013835468_bit_get(intel_dp), 0);
> > >
> > > @@ -1941,33 +1929,64 @@ void intel_psr_pre_plane_update(struct
> > > intel_atomic_state *state,
> > > }
> > > }
> > >
> > > +/*
> > > + * Wa_16013835468
> > > + * Wa_14015648006
> > > + */
> > > +static void wa_16013835468(struct intel_dp *intel_dp, bool
> > > wm_level_disabled)
> > > +{
> > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > +
> > > + if (!IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&
> > > + !IS_DISPLAY_VER(dev_priv, 11, 13))
> > > + return;
> >
> > This is still confusing the two different workarounds,
> > and actually losing the one about the delayed vblank.
>
> This is only one Wa. There are two lineage numbers describing same
> workaround.
>
> Can you please point me out the delayed vblank wa description? I can't
> find it from Bspec? Original implementation is referring lineages
> 1601383546 and 14015648006. Neither of these are about delayed vblank
> specifically.
I thought I already copy pasted the quote from the spec
in an earlier reply?
1601383546:
"Display underrun when using delayed vblank with PSR2. Workaround: If
using PSR2 on transcoder A with delayed vblank, set bit 0x46430[23]=0x1.
If using PSR2 on transcoder B with delayed vblank, set bit
0x46430[24]=0x1."
>
> >
> > > +
> > > + if (intel_dp->psr.enabled && wm_level_disabled)
> > > + intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> > > + wa_16013835468_bit_get(intel_dp));
> > > + else
> > > + intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> > > + wa_16013835468_bit_get(intel_dp), 0);
> > > +}
> > > +
> > > static void _intel_psr_post_plane_update(const struct
> > > intel_atomic_state *state,
> > > - const struct
> > > intel_crtc_state *crtc_state)
> > > + const struct
> > > intel_crtc_state *old_crtc_state,
> > > + const struct
> > > intel_crtc_state *new_crtc_state)
> >
> > The rename reduces the signal-to-noise ratio near zero.
>
> Can you please elaborate this a bit more? What would you suggest? I
> need to use both, old and new state to detect difference in
> wm_level_disabled. I want to set/clear the chicken bit only when
> necessary.
I would either just always set/clear the chicken bit (dunno if
there's any real point in optimizing it out), or split the rename
to a separate patch.
>
> >
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state-
> > > >base.dev);
> > > struct intel_encoder *encoder;
> > >
> > > - if (!crtc_state->has_psr)
> > > + if (!new_crtc_state->has_psr)
> > > return;
> > >
> > > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > > encoder,
> > > - crtc_state-
> > > >uapi.encoder_mask) {
> > > + new_crtc_state-
> > > >uapi.encoder_mask) {
> > > struct intel_dp *intel_dp =
> > > enc_to_intel_dp(encoder);
> > > struct intel_psr *psr = &intel_dp->psr;
> > > bool keep_disabled = false;
> > >
> > > mutex_lock(&psr->lock);
> > >
> > > - drm_WARN_ON(&dev_priv->drm, psr->enabled &&
> > > !crtc_state->active_planes);
> > > + drm_WARN_ON(&dev_priv->drm, psr->enabled &&
> > > + !new_crtc_state->active_planes);
> > >
> > > keep_disabled |= psr->sink_not_reliable;
> > > - keep_disabled |= !crtc_state->active_planes;
> > > + keep_disabled |= !new_crtc_state->active_planes;
> > >
> > > if (!psr->enabled && !keep_disabled)
> > > - intel_psr_enable_locked(intel_dp,
> > > crtc_state);
> > > + intel_psr_enable_locked(intel_dp,
> > > new_crtc_state);
> > > +
> > > + /*
> > > + * Wa_16013835468
> > > + * Wa_14015648006
> > > + */
> > > + if (old_crtc_state->wm_level_disabled !=
> > > + new_crtc_state->wm_level_disabled)
> > > + wa_16013835468(intel_dp,
> > > + new_crtc_state-
> > > >wm_level_disabled);
> > >
> > > /* Force a PSR exit when enabling CRC to avoid CRC
> > > timeouts */
> > > - if (crtc_state->crc_enabled && psr->enabled)
> > > + if (new_crtc_state->crc_enabled && psr->enabled)
> > > psr_force_hw_tracking_exit(intel_dp);
> > >
> > > mutex_unlock(&psr->lock);
> > > @@ -1977,15 +1996,17 @@ static void
> > > _intel_psr_post_plane_update(const struct intel_atomic_state
> > > *state,
> > > void intel_psr_post_plane_update(const struct intel_atomic_state
> > > *state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state-
> > > >base.dev);
> > > - struct intel_crtc_state *crtc_state;
> > > + struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> > > struct intel_crtc *crtc;
> > > int i;
> > >
> > > if (!HAS_PSR(dev_priv))
> > > return;
> > >
> > > - for_each_new_intel_crtc_in_state(state, crtc, crtc_state,
> > > i)
> > > - _intel_psr_post_plane_update(state, crtc_state);
> > > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > > old_crtc_state,
> > > + new_crtc_state, i)
> > > + _intel_psr_post_plane_update(state, old_crtc_state,
> > > + new_crtc_state);
> > > }
> > >
> > > static int _psr2_ready_for_pipe_update_locked(struct intel_dp
> > > *intel_dp)
> > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > > index 50a9a6adbe32..afb751c024ba 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > > @@ -2273,9 +2273,12 @@ static int skl_wm_check_vblank(struct
> > > intel_crtc_state *crtc_state)
> > > return level;
> > >
> > > /*
> > > - * FIXME PSR needs to toggle
> > > LATENCY_REPORTING_REMOVED_PIPE_*
> > > + * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
> > > * based on whether we're limited by the vblank duration.
> > > - *
> > > + */
> > > + crtc_state->wm_level_disabled = level < i915-
> > > >display.wm.num_levels - 1;
> > > +
> > > + /*
> > > * FIXME also related to skl+ w/a 1136 (also unimplemented
> > > as of
> > > * now) perhaps?
> > > */
> > > --
> > > 2.34.1
> >
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2
2023-03-21 16:14 ` Hogander, Jouni
@ 2023-03-21 16:29 ` Ville Syrjälä
2023-03-21 16:41 ` Ville Syrjälä
1 sibling, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2023-03-21 16:29 UTC (permalink / raw)
To: Hogander, Jouni; +Cc: intel-gfx
On Tue, Mar 21, 2023 at 04:14:57PM +0000, Hogander, Jouni wrote:
> On Tue, 2023-03-21 at 17:43 +0200, Ville Syrjälä wrote:
> > On Mon, Mar 20, 2023 at 06:59:44PM +0200, Jouni Högander wrote:
> > > Ensure vblank >= psr2 vblank
> > > where
> > > Psr2 vblank = PSR2_CTL Block Count Number maximum line count.
> > >
> > > Bspec: 71580, 49274
> > >
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++
> > > 1 file changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 1050d777a108..1b40d9c73c18 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -958,6 +958,14 @@ static bool intel_psr2_config_valid(struct
> > > intel_dp *intel_dp,
> > > return false;
> > > }
> > >
> > > + /* Vblank >= PSR2_CTL Block Count Number maximum line count
> > > */
> > > + if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
> > > + crtc_state->hw.adjusted_mode.crtc_vblank_start < 12) {
> >
> > Why 12? Shouldn't it be based on the wake_lines/BLOCK_COUNT_NUM
> > stuff?
>
> I took this directly from Bspec. I think your suggestions make sense. I
> will experiment them and come back on this.
>
> >
> >
> > If so I would suggest we try someting like this:
> >
> > psr2_block_count_lines()
> > {
> > return ...wake_lines... ? 12 : 8;
I guess we could even make that 'roundup(max(wake_lines), 4)'
to be more future proof.
Hmm, except that might not be all that future proof if the
hardware didn't support all block size between the min/max.
Eg. if it only supported 2,3,5 blocks.
So I guess we might want this thing to return only actually
supported numbers.
> > }
> >
> > psr2_block_count()
> > {
> > return psr2_block_count_lines() / 4;
> > }
> >
> > if (vblank_lengh < psr2_block_count_lines())
> > fail;
> >
> > if (psr_block_count() > 2)
> > val |= BLOCK_COUNT_NUM_3;
> > else
> > val |= BLOCK_COUNT_NUM_2;
> >
> > > + drm_dbg_kms(&dev_priv->drm,
> > > + "PSR2 not enabled, too short vblank
> > > time\n");
> > > + return false;
> > > + }
> > > +
> > > if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > > if (!intel_psr2_sel_fetch_config_valid(intel_dp,
> > > crtc_state) &&
> > > !HAS_PSR_HW_TRACKING(dev_priv)) {
> > > --
> > > 2.34.1
> >
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2
2023-03-21 16:14 ` Hogander, Jouni
2023-03-21 16:29 ` Ville Syrjälä
@ 2023-03-21 16:41 ` Ville Syrjälä
1 sibling, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2023-03-21 16:41 UTC (permalink / raw)
To: Hogander, Jouni; +Cc: intel-gfx
On Tue, Mar 21, 2023 at 04:14:57PM +0000, Hogander, Jouni wrote:
> On Tue, 2023-03-21 at 17:43 +0200, Ville Syrjälä wrote:
> > On Mon, Mar 20, 2023 at 06:59:44PM +0200, Jouni Högander wrote:
> > > Ensure vblank >= psr2 vblank
> > > where
> > > Psr2 vblank = PSR2_CTL Block Count Number maximum line count.
> > >
> > > Bspec: 71580, 49274
> > >
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++
> > > 1 file changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 1050d777a108..1b40d9c73c18 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -958,6 +958,14 @@ static bool intel_psr2_config_valid(struct
> > > intel_dp *intel_dp,
> > > return false;
> > > }
> > >
> > > + /* Vblank >= PSR2_CTL Block Count Number maximum line count
> > > */
> > > + if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
> > > + crtc_state->hw.adjusted_mode.crtc_vblank_start < 12) {
> >
> > Why 12? Shouldn't it be based on the wake_lines/BLOCK_COUNT_NUM
> > stuff?
>
> I took this directly from Bspec. I think your suggestions make sense. I
> will experiment them and come back on this.
BTW the other thing that might be a bit unclear here is whether
we care about the transcoder's full vblank length, or the pipe's
vblank length (as reduced by the delayed vblank stuff).
If you're experimenting with this then changing the vblank
delay can be done live with intel_reg (on tgl just alter
TRANS_VBLANK.vblanl_start, on adl+ alter TRANS_SET_CONTEXT_LATENCY).
When doing stuff like this I always just run eg. 'testdisplay -o <id>,0'
to quiesce the driver as much as possible, and then
'export IGT_NO_FORCEWAKE=1' before poking the registers with
intel_reg avoid the debugfs forcewake stuff from perturbing the
system either.
Using that approach it should be possible to determine which vblank
length actually matters. Though you do need to be careful about
the pkg-c latency/prefill stuff when increasing the vblank delay.
So might also need to disable wm1+ (and maybe also sagv) leaving
only wm0 enabled. That would allow you to push the pipe's delayed
start of vblank very close to the end of vblank without getting
underruns.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2023-03-21 16:41 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Unify pre/post hooks Jouni Högander
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006 Jouni Högander
2023-03-21 15:34 ` Ville Syrjälä
2023-03-21 15:57 ` Hogander, Jouni
2023-03-21 16:19 ` Ville Syrjälä
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2 Jouni Högander
2023-03-21 15:43 ` Ville Syrjälä
2023-03-21 16:14 ` Hogander, Jouni
2023-03-21 16:29 ` Ville Syrjälä
2023-03-21 16:41 ` Ville Syrjälä
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 4/4] drm/i915/psr: Implement Display WA #1136 Jouni Högander
2023-03-21 5:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for High refresh rate PSR fixes (rev3) Patchwork
2023-03-21 5:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-21 5:24 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2023-03-21 5:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-21 9:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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