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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 22/57] drm/i915: Move scheduler queue
Date: Thu, 4 Feb 2021 11:19:00 +0000
Message-ID: <ad0639e8-7eab-7d38-1cc2-f93bd1800c6b@linux.intel.com> (raw)
In-Reply-To: <20210201085715.27435-22-chris@chris-wilson.co.uk>


On 01/02/2021 08:56, Chris Wilson wrote:
> Extract the scheduling queue from "execlists" into the per-engine
> scheduling structs, for reuse by other backends.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   .../gpu/drm/i915/gem/i915_gem_context_types.h |  2 +-
>   drivers/gpu/drm/i915/gem/i915_gem_wait.c      |  1 +
>   drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  7 ++-
>   drivers/gpu/drm/i915/gt/intel_engine_pm.c     |  3 +-
>   drivers/gpu/drm/i915/gt/intel_engine_types.h  | 14 -----
>   .../drm/i915/gt/intel_execlists_submission.c  | 29 +++++-----
>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 ++--
>   drivers/gpu/drm/i915/i915_drv.h               |  1 -
>   drivers/gpu/drm/i915/i915_request.h           |  2 +-
>   drivers/gpu/drm/i915/i915_scheduler.c         | 57 ++++++++++++-------
>   drivers/gpu/drm/i915/i915_scheduler.h         | 15 +++++
>   drivers/gpu/drm/i915/i915_scheduler_types.h   | 14 +++++
>   .../gpu/drm/i915/selftests/i915_scheduler.c   | 13 ++---
>   13 files changed, 100 insertions(+), 69 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 085f6a3735e8..d5bc75508048 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -19,7 +19,7 @@
>   
>   #include "gt/intel_context_types.h"
>   
> -#include "i915_scheduler.h"
> +#include "i915_scheduler_types.h"
>   #include "i915_sw_fence.h"
>   
>   struct pid;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
> index d79bf16083bd..4d1897c347b9 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
> @@ -13,6 +13,7 @@
>   #include "dma_resv_utils.h"
>   #include "i915_gem_ioctls.h"
>   #include "i915_gem_object.h"
> +#include "i915_scheduler.h"
>   
>   static long
>   i915_gem_object_wait_fence(struct dma_fence *fence,
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index d7ff84d92936..4c07c6f61924 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -574,7 +574,6 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine)
>   		memset(execlists->inflight, 0, sizeof(execlists->inflight));
>   
>   	execlists->queue_priority_hint = INT_MIN;
> -	execlists->queue = RB_ROOT_CACHED;
>   }
>   
>   static void cleanup_status_page(struct intel_engine_cs *engine)
> @@ -911,7 +910,7 @@ int intel_engines_init(struct intel_gt *gt)
>    */
>   void intel_engine_cleanup_common(struct intel_engine_cs *engine)
>   {
> -	GEM_BUG_ON(!list_empty(&engine->sched.requests));
> +	i915_sched_fini(intel_engine_get_scheduler(engine));
>   	tasklet_kill(&engine->execlists.tasklet); /* flush the callback */
>   
>   	intel_breadcrumbs_free(engine->breadcrumbs);
> @@ -1225,6 +1224,8 @@ void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
>    */
>   bool intel_engine_is_idle(struct intel_engine_cs *engine)
>   {
> +	struct i915_sched *se = intel_engine_get_scheduler(engine);

What do you have 'se' stand for?

> +
>   	/* More white lies, if wedged, hw state is inconsistent */
>   	if (intel_gt_is_wedged(engine->gt))
>   		return true;
> @@ -1237,7 +1238,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
>   	intel_engine_flush_submission(engine);
>   
>   	/* ELSP is empty, but there are ready requests? E.g. after reset */
> -	if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
> +	if (!i915_sched_is_idle(se))
>   		return false;
>   
>   	/* Ring stopped? */
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index 6372d7826bc9..3510c9236334 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -4,6 +4,7 @@
>    */
>   
>   #include "i915_drv.h"
> +#include "i915_scheduler.h"
>   
>   #include "intel_breadcrumbs.h"
>   #include "intel_context.h"
> @@ -276,7 +277,7 @@ static int __engine_park(struct intel_wakeref *wf)
>   	if (engine->park)
>   		engine->park(engine);
>   
> -	engine->execlists.no_priolist = false;
> +	i915_sched_park(intel_engine_get_scheduler(engine));
>   
>   	/* While gt calls i915_vma_parked(), we have to break the lock cycle */
>   	intel_gt_pm_put_async(engine->gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 0936b0699cbb..c36bdd957f8f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -153,11 +153,6 @@ struct intel_engine_execlists {
>   	 */
>   	struct timer_list preempt;
>   
> -	/**
> -	 * @default_priolist: priority list for I915_PRIORITY_NORMAL
> -	 */
> -	struct i915_priolist default_priolist;
> -
>   	/**
>   	 * @ccid: identifier for contexts submitted to this engine
>   	 */
> @@ -192,11 +187,6 @@ struct intel_engine_execlists {
>   	 */
>   	u32 reset_ccid;
>   
> -	/**
> -	 * @no_priolist: priority lists disabled
> -	 */
> -	bool no_priolist;
> -
>   	/**
>   	 * @submit_reg: gen-specific execlist submission register
>   	 * set to the ExecList Submission Port (elsp) register pre-Gen11 and to
> @@ -252,10 +242,6 @@ struct intel_engine_execlists {
>   	 */
>   	int queue_priority_hint;
>   
> -	/**
> -	 * @queue: queue of requests, in priority lists
> -	 */
> -	struct rb_root_cached queue;
>   	struct rb_root_cached virtual;

Presumably virtual queue will go later in the series since I have seen 
some patches which improve that algorithm.

>   
>   	/**
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index dd1429a476d5..95208d45ffb1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -272,11 +272,11 @@ static int effective_prio(const struct i915_request *rq)
>   	return prio;
>   }
>   
> -static int queue_prio(const struct intel_engine_execlists *execlists)
> +static int queue_prio(const struct i915_sched *se)
>   {
>   	struct rb_node *rb;
>   
> -	rb = rb_first_cached(&execlists->queue);
> +	rb = rb_first_cached(&se->queue);
>   	if (!rb)
>   		return INT_MIN;
>   
> @@ -340,7 +340,7 @@ static bool need_preempt(const struct intel_engine_cs *engine,
>   	 * context, it's priority would not exceed ELSP[0] aka last_prio.
>   	 */
>   	return max(virtual_prio(&engine->execlists),
> -		   queue_prio(&engine->execlists)) > last_prio;
> +		   queue_prio(se)) > last_prio;
>   }
>   
>   __maybe_unused static bool
> @@ -1033,13 +1033,13 @@ static bool needs_timeslice(const struct intel_engine_cs *engine,
>   		return false;
>   
>   	/* If ELSP[1] is occupied, always check to see if worth slicing */
> -	if (!list_is_last_rcu(&rq->sched.link, &se->requests)) {
> +	if (!i915_sched_is_last_request(se, rq)) {
>   		ENGINE_TRACE(engine, "timeslice required for second inflight context\n");
>   		return true;
>   	}
>   
>   	/* Otherwise, ELSP[0] is by itself, but may be waiting in the queue */
> -	if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)) {
> +	if (!i915_sched_is_idle(se)) {
>   		ENGINE_TRACE(engine, "timeslice required for queue\n");
>   		return true;
>   	}
> @@ -1285,7 +1285,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>   		GEM_BUG_ON(rq->engine != &ve->base);
>   		GEM_BUG_ON(rq->context != &ve->context);
>   
> -		if (unlikely(rq_prio(rq) < queue_prio(execlists))) {
> +		if (unlikely(rq_prio(rq) < queue_prio(se))) {
>   			spin_unlock(&ve->base.sched.lock);
>   			break;
>   		}
> @@ -1351,7 +1351,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>   			break;
>   	}
>   
> -	while ((rb = rb_first_cached(&execlists->queue))) {
> +	while ((rb = rb_first_cached(&se->queue))) {
>   		struct i915_priolist *p = to_priolist(rb);
>   		struct i915_request *rq, *rn;
>   
> @@ -1430,7 +1430,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>   			}
>   		}
>   
> -		rb_erase_cached(&p->node, &execlists->queue);
> +		rb_erase_cached(&p->node, &se->queue);
>   		i915_priolist_free(p);
>   	}
>   done:
> @@ -1452,7 +1452,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>   	 * request triggering preemption on the next dequeue (or subsequent
>   	 * interrupt for secondary ports).
>   	 */
> -	execlists->queue_priority_hint = queue_prio(execlists);
> +	execlists->queue_priority_hint = queue_prio(se);
>   	spin_unlock(&se->lock);
>   
>   	/*
> @@ -2678,7 +2678,7 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine)
>   	intel_engine_signal_breadcrumbs(engine);
>   
>   	/* Flush the queued requests to the timeline list (for retiring). */
> -	while ((rb = rb_first_cached(&execlists->queue))) {
> +	while ((rb = rb_first_cached(&se->queue))) {
>   		struct i915_priolist *p = to_priolist(rb);
>   
>   		priolist_for_each_request_consume(rq, rn, p) {
> @@ -2688,9 +2688,10 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine)
>   			}
>   		}
>   
> -		rb_erase_cached(&p->node, &execlists->queue);
> +		rb_erase_cached(&p->node, &se->queue);
>   		i915_priolist_free(p);
>   	}
> +	GEM_BUG_ON(!i915_sched_is_idle(se));
>   
>   	/* On-hold requests will be flushed to timeline upon their release */
>   	list_for_each_entry(rq, &se->hold, sched.link)
> @@ -2722,7 +2723,7 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine)
>   	/* Remaining _unready_ requests will be nop'ed when submitted */
>   
>   	execlists->queue_priority_hint = INT_MIN;
> -	execlists->queue = RB_ROOT_CACHED;
> +	se->queue = RB_ROOT_CACHED;
>   
>   	GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
>   	execlists->tasklet.callback = nop_submission_tasklet;
> @@ -2957,7 +2958,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
>   
>   static struct list_head *virtual_queue(struct virtual_engine *ve)
>   {
> -	return &ve->base.execlists.default_priolist.requests;
> +	return &ve->base.sched.default_priolist.requests;
>   }
>   
>   static void rcu_virtual_context_destroy(struct work_struct *wrk)
> @@ -3558,7 +3559,7 @@ void intel_execlists_show_requests(struct intel_engine_cs *engine,
>   
>   	last = NULL;
>   	count = 0;
> -	for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
> +	for (rb = rb_first_cached(&se->queue); rb; rb = rb_next(rb)) {
>   		struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
>   
>   		priolist_for_each_request(rq, p) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 45f6d38341ef..6f07f1124a13 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -204,7 +204,7 @@ static void __guc_dequeue(struct intel_engine_cs *engine)
>   	 * event.
>   	 */
>   	port = first;
> -	while ((rb = rb_first_cached(&execlists->queue))) {
> +	while ((rb = rb_first_cached(&se->queue))) {
>   		struct i915_priolist *p = to_priolist(rb);
>   		struct i915_request *rq, *rn;
>   
> @@ -224,7 +224,7 @@ static void __guc_dequeue(struct intel_engine_cs *engine)
>   			last = rq;
>   		}
>   
> -		rb_erase_cached(&p->node, &execlists->queue);
> +		rb_erase_cached(&p->node, &se->queue);
>   		i915_priolist_free(p);
>   	}
>   done:
> @@ -362,7 +362,7 @@ static void guc_reset_cancel(struct intel_engine_cs *engine)
>   	}
>   
>   	/* Flush the queued requests to the timeline list (for retiring). */
> -	while ((rb = rb_first_cached(&execlists->queue))) {
> +	while ((rb = rb_first_cached(&se->queue))) {
>   		struct i915_priolist *p = to_priolist(rb);
>   
>   		priolist_for_each_request_consume(rq, rn, p) {
> @@ -372,14 +372,15 @@ static void guc_reset_cancel(struct intel_engine_cs *engine)
>   			i915_request_mark_complete(rq);
>   		}
>   
> -		rb_erase_cached(&p->node, &execlists->queue);
> +		rb_erase_cached(&p->node, &se->queue);
>   		i915_priolist_free(p);
>   	}
> +	GEM_BUG_ON(!i915_sched_is_idle(se));
>   
>   	/* Remaining _unready_ requests will be nop'ed when submitted */
>   
>   	execlists->queue_priority_hint = INT_MIN;
> -	execlists->queue = RB_ROOT_CACHED;
> +	se->queue = RB_ROOT_CACHED;
>   
>   	spin_unlock_irqrestore(&se->lock, flags);
>   }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f684147290cb..0e4d7998be53 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -99,7 +99,6 @@
>   #include "i915_gpu_error.h"
>   #include "i915_perf_types.h"
>   #include "i915_request.h"
> -#include "i915_scheduler.h"
>   #include "gt/intel_timeline.h"
>   #include "i915_vma.h"
>   #include "i915_irq.h"
> diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
> index 3a5d6bdcd8dd..c41582b96b46 100644
> --- a/drivers/gpu/drm/i915/i915_request.h
> +++ b/drivers/gpu/drm/i915/i915_request.h
> @@ -35,7 +35,7 @@
>   #include "gt/intel_timeline_types.h"
>   
>   #include "i915_gem.h"
> -#include "i915_scheduler.h"
> +#include "i915_scheduler_types.h"
>   #include "i915_selftest.h"
>   #include "i915_sw_fence.h"
>   
> diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
> index 5eea8c6b85a8..aef14e4463c3 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler.c
> +++ b/drivers/gpu/drm/i915/i915_scheduler.c
> @@ -107,6 +107,7 @@ void i915_sched_init(struct i915_sched *se,
>   
>   	INIT_LIST_HEAD(&se->requests);
>   	INIT_LIST_HEAD(&se->hold);
> +	se->queue = RB_ROOT_CACHED;
>   
>   	i915_sched_init_ipi(&se->ipi);
>   
> @@ -123,6 +124,19 @@ void i915_sched_init(struct i915_sched *se,
>   #endif
>   }
>   
> +void i915_sched_park(struct i915_sched *se)
> +{
> +	GEM_BUG_ON(!i915_sched_is_idle(se));
> +	se->no_priolist = false;
> +}
> +
> +void i915_sched_fini(struct i915_sched *se)
> +{
> +	GEM_BUG_ON(!list_empty(&se->requests));
> +
> +	i915_sched_park(se);
> +}
> +
>   static void __ipi_add(struct i915_request *rq)
>   {
>   #define STUB ((struct i915_request *)1)
> @@ -191,7 +205,7 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb)
>   	return rb_entry(rb, struct i915_priolist, node);
>   }
>   
> -static void assert_priolists(struct intel_engine_execlists * const execlists)
> +static void assert_priolists(struct i915_sched * const se)
>   {
>   	struct rb_node *rb;
>   	long last_prio;
> @@ -199,11 +213,11 @@ static void assert_priolists(struct intel_engine_execlists * const execlists)
>   	if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>   		return;
>   
> -	GEM_BUG_ON(rb_first_cached(&execlists->queue) !=
> -		   rb_first(&execlists->queue.rb_root));
> +	GEM_BUG_ON(rb_first_cached(&se->queue) !=
> +		   rb_first(&se->queue.rb_root));
>   
>   	last_prio = INT_MAX;
> -	for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
> +	for (rb = rb_first_cached(&se->queue); rb; rb = rb_next(rb)) {
>   		const struct i915_priolist *p = to_priolist(rb);
>   
>   		GEM_BUG_ON(p->priority > last_prio);
> @@ -212,24 +226,22 @@ static void assert_priolists(struct intel_engine_execlists * const execlists)
>   }
>   
>   static struct list_head *
> -lookup_priolist(struct intel_engine_cs *engine, int prio)
> +lookup_priolist(struct i915_sched *se, int prio)
>   {
> -	struct intel_engine_execlists * const execlists = &engine->execlists;
> -	struct i915_sched *se = intel_engine_get_scheduler(engine);
>   	struct i915_priolist *p;
>   	struct rb_node **parent, *rb;
>   	bool first = true;
>   
>   	lockdep_assert_held(&se->lock);
> -	assert_priolists(execlists);
> +	assert_priolists(se);
>   
> -	if (unlikely(execlists->no_priolist))
> +	if (unlikely(se->no_priolist))
>   		prio = I915_PRIORITY_NORMAL;
>   
>   find_priolist:
>   	/* most positive priority is scheduled first, equal priorities fifo */
>   	rb = NULL;
> -	parent = &execlists->queue.rb_root.rb_node;
> +	parent = &se->queue.rb_root.rb_node;
>   	while (*parent) {
>   		rb = *parent;
>   		p = to_priolist(rb);
> @@ -244,7 +256,7 @@ lookup_priolist(struct intel_engine_cs *engine, int prio)
>   	}
>   
>   	if (prio == I915_PRIORITY_NORMAL) {
> -		p = &execlists->default_priolist;
> +		p = &se->default_priolist;
>   	} else {
>   		p = kmem_cache_alloc(global.slab_priorities, GFP_ATOMIC);
>   		/* Convert an allocation failure to a priority bump */
> @@ -259,7 +271,7 @@ lookup_priolist(struct intel_engine_cs *engine, int prio)
>   			 * requests, so if userspace lied about their
>   			 * dependencies that reordering may be visible.
>   			 */
> -			execlists->no_priolist = true;
> +			se->no_priolist = true;
>   			goto find_priolist;
>   		}
>   	}
> @@ -268,7 +280,7 @@ lookup_priolist(struct intel_engine_cs *engine, int prio)
>   	INIT_LIST_HEAD(&p->requests);
>   
>   	rb_link_node(&p->node, rb, parent);
> -	rb_insert_color_cached(&p->node, &execlists->queue, first);
> +	rb_insert_color_cached(&p->node, &se->queue, first);
>   
>   	return &p->requests;
>   }
> @@ -361,13 +373,14 @@ static void ipi_priority(struct i915_request *rq, int prio)
>   static void __i915_request_set_priority(struct i915_request *rq, int prio)
>   {
>   	struct intel_engine_cs *engine = rq->engine;
> +	struct i915_sched *se = intel_engine_get_scheduler(engine);
>   	struct list_head *pos = &rq->sched.signalers_list;
>   	struct list_head *plist;
>   
>   	SCHED_TRACE(&engine->sched, "PI for " RQ_FMT ", prio:%d\n",
>   		    RQ_ARG(rq), prio);
>   
> -	plist = lookup_priolist(engine, prio);
> +	plist = lookup_priolist(se, prio);
>   
>   	/*
>   	 * Recursively bump all dependent priorities to match the new request.
> @@ -570,18 +583,18 @@ void __i915_sched_defer_request(struct intel_engine_cs *engine,
>   		clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
>   	} while ((rq = stack_pop(rq, &pos)));
>   
> -	pos = lookup_priolist(engine, prio);
> +	pos = lookup_priolist(se, prio);
>   	list_for_each_entry_safe(rq, rn, &dfs, sched.link) {
>   		set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
>   		list_add_tail(&rq->sched.link, pos);
>   	}
>   }
>   
> -static void queue_request(struct intel_engine_cs *engine,
> +static void queue_request(struct i915_sched *se,
>   			  struct i915_request *rq)
>   {
>   	GEM_BUG_ON(!list_empty(&rq->sched.link));
> -	list_add_tail(&rq->sched.link, lookup_priolist(engine, rq_prio(rq)));
> +	list_add_tail(&rq->sched.link, lookup_priolist(se, rq_prio(rq)));
>   	set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
>   }
>   
> @@ -648,9 +661,9 @@ void i915_request_enqueue(struct i915_request *rq)
>   		list_add_tail(&rq->sched.link, &se->hold);
>   		i915_request_set_hold(rq);
>   	} else {
> -		queue_request(engine, rq);
> +		queue_request(se, rq);
>   
> -		GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
> +		GEM_BUG_ON(i915_sched_is_idle(se));
>   
>   		kick = submit_queue(engine, rq);
>   	}
> @@ -682,9 +695,9 @@ __i915_sched_rewind_requests(struct intel_engine_cs *engine)
>   		GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
>   		if (rq_prio(rq) != prio) {
>   			prio = rq_prio(rq);
> -			pl = lookup_priolist(engine, prio);
> +			pl = lookup_priolist(se, prio);
>   		}
> -		GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
> +		GEM_BUG_ON(i915_sched_is_idle(se));
>   
>   		list_move(&rq->sched.link, pl);
>   		set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
> @@ -819,7 +832,7 @@ void __i915_sched_resume_request(struct intel_engine_cs *engine,
>   		i915_request_clear_hold(rq);
>   		list_del_init(&rq->sched.link);
>   
> -		queue_request(engine, rq);
> +		queue_request(se, rq);
>   
>   		/* Also release any children on this engine that are ready */
>   		for_each_waiter(p, rq) {
> diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
> index ebd93ae303b4..71bef75859b4 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler.h
> +++ b/drivers/gpu/drm/i915/i915_scheduler.h
> @@ -12,6 +12,7 @@
>   #include <linux/kernel.h>
>   
>   #include "i915_scheduler_types.h"
> +#include "i915_request.h"
>   
>   struct drm_printer;
>   struct intel_engine_cs;
> @@ -48,6 +49,8 @@ void i915_sched_init(struct i915_sched *se,
>   		     const char *name,
>   		     unsigned long mask,
>   		     unsigned int subclass);
> +void i915_sched_park(struct i915_sched *se);
> +void i915_sched_fini(struct i915_sched *se);
>   
>   void i915_request_set_priority(struct i915_request *request, int prio);
>   
> @@ -75,6 +78,18 @@ static inline void i915_priolist_free(struct i915_priolist *p)
>   		__i915_priolist_free(p);
>   }
>   
> +static inline bool i915_sched_is_idle(const struct i915_sched *se)
> +{
> +	return RB_EMPTY_ROOT(&se->queue.rb_root);
> +}
> +
> +static inline bool
> +i915_sched_is_last_request(const struct i915_sched *se,
> +			   const struct i915_request *rq)
> +{
> +	return list_is_last_rcu(&rq->sched.link, &se->requests);
> +}
> +
>   void i915_request_show_with_schedule(struct drm_printer *m,
>   				     const struct i915_request *rq,
>   				     const char *prefix,
> diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
> index b7ee122d4f28..44dae932e5af 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler_types.h
> +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
> @@ -29,6 +29,10 @@ struct i915_sched {
>   
>   	struct list_head requests; /* active request, on HW */
>   	struct list_head hold; /* ready requests, but on hold */
> +	/**
> +	 * @queue: queue of requests, in priority lists
> +	 */
> +	struct rb_root_cached queue;
>   
>   	/* Inter-engine scheduling delegate */
>   	struct i915_sched_ipi {
> @@ -36,6 +40,16 @@ struct i915_sched {
>   		struct work_struct work;
>   	} ipi;
>   
> +	/**
> +	 * @default_priolist: priority list for I915_PRIORITY_NORMAL
> +	 */
> +	struct i915_priolist default_priolist;
> +
> +	/**
> +	 * @no_priolist: priority lists disabled
> +	 */
> +	bool no_priolist;
> +
>   	/* Pretty device names for debug messages */
>   	struct {
>   		struct device *dev;
> diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
> index b1a0a711e01f..56d785581535 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
> @@ -77,8 +77,7 @@ static int all_engines(struct drm_i915_private *i915,
>   	return 0;
>   }
>   
> -static bool check_context_order(struct i915_sched *se,
> -				struct intel_engine_cs *engine)
> +static bool check_context_order(struct i915_sched *se)
>   {
>   	u64 last_seqno, last_context;
>   	unsigned long count;
> @@ -93,7 +92,7 @@ static bool check_context_order(struct i915_sched *se,
>   	last_context = 0;
>   	last_seqno = 0;
>   	last_prio = 0;
> -	for (rb = rb_first_cached(&engine->execlists.queue); rb; rb = rb_next(rb)) {
> +	for (rb = rb_first_cached(&se->queue); rb; rb = rb_next(rb)) {
>   		struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
>   		struct i915_request *rq;
>   
> @@ -175,7 +174,7 @@ static int __single_chain(struct intel_engine_cs *engine, unsigned long length,
>   	intel_engine_flush_submission(engine);
>   
>   	execlists_active_lock_bh(&engine->execlists);
> -	if (fn(rq, count, count - 1) && !check_context_order(se, engine))
> +	if (fn(rq, count, count - 1) && !check_context_order(se))
>   		err = -EINVAL;
>   	execlists_active_unlock_bh(&engine->execlists);
>   
> @@ -260,7 +259,7 @@ static int __wide_chain(struct intel_engine_cs *engine, unsigned long width,
>   	intel_engine_flush_submission(engine);
>   
>   	execlists_active_lock_bh(&engine->execlists);
> -	if (fn(rq[i - 1], i, count) && !check_context_order(se, engine))
> +	if (fn(rq[i - 1], i, count) && !check_context_order(se))
>   		err = -EINVAL;
>   	execlists_active_unlock_bh(&engine->execlists);
>   
> @@ -349,7 +348,7 @@ static int __inv_chain(struct intel_engine_cs *engine, unsigned long width,
>   	intel_engine_flush_submission(engine);
>   
>   	execlists_active_lock_bh(&engine->execlists);
> -	if (fn(rq[i - 1], i, count) && !check_context_order(se, engine))
> +	if (fn(rq[i - 1], i, count) && !check_context_order(se))
>   		err = -EINVAL;
>   	execlists_active_unlock_bh(&engine->execlists);
>   
> @@ -455,7 +454,7 @@ static int __sparse_chain(struct intel_engine_cs *engine, unsigned long width,
>   	intel_engine_flush_submission(engine);
>   
>   	execlists_active_lock_bh(&engine->execlists);
> -	if (fn(rq[i - 1], i, count) && !check_context_order(se, engine))
> +	if (fn(rq[i - 1], i, count) && !check_context_order(se))
>   		err = -EINVAL;
>   	execlists_active_unlock_bh(&engine->execlists);
>   
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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  reply index

Thread overview: 103+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-01  8:56 [Intel-gfx] [PATCH 01/57] drm/i915/gt: Restrict the GT clock override to just Icelake Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 02/57] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Chris Wilson
2021-02-01 14:34   ` Mika Kuoppala
2021-02-01  8:56 ` [Intel-gfx] [PATCH 03/57] drm/i915/selftests: Exercise cross-process context isolation Chris Wilson
2021-02-01 16:37   ` Mika Kuoppala
2021-02-01  8:56 ` [Intel-gfx] [PATCH 04/57] drm/i915: Protect against request freeing during cancellation on wedging Chris Wilson
2021-02-02  9:55   ` Mika Kuoppala
2021-02-01  8:56 ` [Intel-gfx] [PATCH 05/57] drm/i915: Take rcu_read_lock for querying fence's driver/timeline names Chris Wilson
2021-02-02 18:33   ` Mika Kuoppala
2021-02-01  8:56 ` [Intel-gfx] [PATCH 06/57] drm/i915/gt: Always flush the submission queue on checking for idle Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 07/57] drm/i915/gt: Move engine setup out of set_default_submission Chris Wilson
2021-02-02 11:57   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 08/57] drm/i915/gt: Move submission_method into intel_gt Chris Wilson
2021-02-02 12:03   ` Tvrtko Ursulin
2021-02-02 12:18     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 09/57] drm/i915: Replace engine->schedule() with a known request operation Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 10/57] drm/i915: Restructure priority inheritance Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 11/57] drm/i915/selftests: Measure set-priority duration Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 12/57] drm/i915/selftests: Exercise priority inheritance around an engine loop Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 13/57] drm/i915/selftests: Force a rewind if at first we don't succeed Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 14/57] drm/i915: Improve DFS for priority inheritance Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 15/57] drm/i915: Extract request submission from execlists Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 16/57] drm/i915: Extract request rewinding " Chris Wilson
2021-02-02 13:08   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 17/57] drm/i915: Extract request suspension from the execlists Chris Wilson
2021-02-02 13:15   ` Tvrtko Ursulin
2021-02-02 13:26     ` Chris Wilson
2021-02-02 13:32       ` Tvrtko Ursulin
2021-02-02 13:27     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 18/57] drm/i915: Extract the ability to defer and rerun a request later Chris Wilson
2021-02-02 13:18   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 19/57] drm/i915: Fix the iterative dfs for defering requests Chris Wilson
2021-02-02 14:10   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 20/57] drm/i915: Wrap access to intel_engine.active Chris Wilson
2021-02-04 11:07   ` Tvrtko Ursulin
2021-02-04 11:18     ` Chris Wilson
2021-02-04 11:56       ` Chris Wilson
2021-02-04 12:08         ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 21/57] drm/i915: Move common active lists from engine to i915_scheduler Chris Wilson
2021-02-04 11:12   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 22/57] drm/i915: Move scheduler queue Chris Wilson
2021-02-04 11:19   ` Tvrtko Ursulin [this message]
2021-02-04 11:32     ` Chris Wilson
2021-02-04 11:40     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 23/57] drm/i915: Move tasklet from execlists to sched Chris Wilson
2021-02-04 14:06   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 24/57] drm/i915/gt: Only kick the scheduler on timeslice/preemption change Chris Wilson
2021-02-04 14:09   ` Tvrtko Ursulin
2021-02-04 14:43     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 25/57] drm/i915: Move submit_request to i915_sched_engine Chris Wilson
2021-02-04 14:13   ` Tvrtko Ursulin
2021-02-04 14:45     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 26/57] drm/i915: Move finding the current active request to the scheduler Chris Wilson
2021-02-04 14:30   ` Tvrtko Ursulin
2021-02-04 14:59     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 27/57] drm/i915: Show execlists queues when dumping state Chris Wilson
2021-02-04 15:04   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 28/57] drm/i915: Wrap i915_request_use_semaphores() Chris Wilson
2021-02-04 15:05   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 29/57] drm/i915: Move scheduler flags Chris Wilson
2021-02-04 15:14   ` Tvrtko Ursulin
2021-02-04 16:05     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 30/57] drm/i915: Move timeslicing flag to scheduler Chris Wilson
2021-02-04 15:18   ` Tvrtko Ursulin
2021-02-04 16:11     ` Chris Wilson
2021-02-05  9:48       ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 31/57] drm/i915/gt: Declare when we enabled timeslicing Chris Wilson
2021-02-04 15:26   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 32/57] drm/i915: Move needs-breadcrumb flags to scheduler Chris Wilson
2021-02-04 15:28   ` Tvrtko Ursulin
2021-02-04 16:12     ` Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 33/57] drm/i915: Move busywaiting control to the scheduler Chris Wilson
2021-02-04 15:32   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 34/57] drm/i915: Move preempt-reset flag " Chris Wilson
2021-02-04 15:34   ` Tvrtko Ursulin
2021-02-01  8:56 ` [Intel-gfx] [PATCH 35/57] drm/i915: Replace priolist rbtree with a skiplist Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 36/57] drm/i915: Wrap cmpxchg64 with try_cmpxchg64() helper Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 37/57] drm/i915: Fair low-latency scheduling Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 38/57] drm/i915/gt: Specify a deadline for the heartbeat Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 39/57] drm/i915: Extend the priority boosting for the display with a deadline Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 40/57] drm/i915/gt: Support virtual engine queues Chris Wilson
2021-02-01  8:56 ` [Intel-gfx] [PATCH 41/57] drm/i915: Move saturated workload detection back to the context Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 42/57] drm/i915: Bump default timeslicing quantum to 5ms Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 43/57] drm/i915/gt: Delay taking irqoff for execlists submission Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 44/57] drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 45/57] drm/i915/gt: Track timeline GGTT offset separately from subpage offset Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 46/57] drm/i915/gt: Add timeline "mode" Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 47/57] drm/i915/gt: Use indices for writing into relative timelines Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 48/57] drm/i915/selftests: Exercise relative timeline modes Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 49/57] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 50/57] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 51/57] drm/i915/gt: Couple tasklet scheduling for all CS interrupts Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 52/57] drm/i915/gt: Support creation of 'internal' rings Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 53/57] drm/i915/gt: Use client timeline address for seqno writes Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 54/57] drm/i915/gt: Infrastructure for ring scheduling Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 55/57] drm/i915/gt: Implement ring scheduler for gen4-7 Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 56/57] drm/i915/gt: Enable ring scheduling for gen5-7 Chris Wilson
2021-02-01  8:57 ` [Intel-gfx] [PATCH 57/57] drm/i915: Support secure dispatch on gen6/gen7 Chris Wilson
2021-02-01 14:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/57] drm/i915/gt: Restrict the GT clock override to just Icelake Patchwork
2021-02-01 14:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-01 14:15 ` [Intel-gfx] [PATCH 01/57] " Mika Kuoppala
2021-02-01 14:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/57] " Patchwork
2021-02-01 19:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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