From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 25/57] drm/i915: Move submit_request to i915_sched_engine
Date: Thu, 4 Feb 2021 14:13:17 +0000 [thread overview]
Message-ID: <d2c832f2-7891-4cc8-750d-dd50794e977c@linux.intel.com> (raw)
In-Reply-To: <20210201085715.27435-25-chris@chris-wilson.co.uk>
On 01/02/2021 08:56, Chris Wilson wrote:
> Claim the submit_request vfunc as the entry point into the scheduler
> backend for ready requests.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 --------
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 11 ++++++-----
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 ++--
> drivers/gpu/drm/i915/gt/mock_engine.c | 4 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> drivers/gpu/drm/i915/i915_request.c | 2 +-
> drivers/gpu/drm/i915/i915_scheduler.c | 2 ++
> drivers/gpu/drm/i915/i915_scheduler_types.h | 9 +++++++++
> drivers/gpu/drm/i915/selftests/i915_request.c | 3 +--
> 10 files changed, 26 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 97fe5e395a85..6b0bde292916 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -416,14 +416,6 @@ struct intel_engine_cs {
> u32 *cs);
> unsigned int emit_fini_breadcrumb_dw;
>
> - /* Pass the request to the hardware queue (e.g. directly into
> - * the legacy ringbuffer or to the end of an execlist).
> - *
> - * This is called from an atomic context with irqs disabled; must
> - * be irq safe.
> - */
> - void (*submit_request)(struct i915_request *rq);
> -
> /*
> * Called on signaling of a SUBMIT_FENCE, passing along the signaling
> * request down to the bonded pairs.
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index be79a352e512..33c1a833df20 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -483,7 +483,7 @@ resubmit_virtual_request(struct i915_request *rq, struct virtual_engine *ve)
>
> clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
> WRITE_ONCE(rq->engine, &ve->base);
> - ve->base.submit_request(rq);
> + ve->base.sched.submit_request(rq);
>
> spin_unlock_irq(&se->lock);
> }
> @@ -2766,7 +2766,7 @@ static bool can_preempt(struct intel_engine_cs *engine)
>
> static void execlists_set_default_submission(struct intel_engine_cs *engine)
> {
> - engine->submit_request = i915_request_enqueue;
> + engine->sched.submit_request = i915_request_enqueue;
> engine->sched.tasklet.callback = execlists_submission_tasklet;
> }
>
> @@ -3227,7 +3227,7 @@ static void virtual_submit_request(struct i915_request *rq)
> rq->fence.context,
> rq->fence.seqno);
>
> - GEM_BUG_ON(ve->base.submit_request != virtual_submit_request);
> + GEM_BUG_ON(ve->base.sched.submit_request != virtual_submit_request);
>
> spin_lock_irqsave(&se->lock, flags);
>
> @@ -3341,12 +3341,10 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
> ve->base.cops = &virtual_context_ops;
> ve->base.request_alloc = execlists_request_alloc;
>
> - ve->base.submit_request = virtual_submit_request;
> ve->base.bond_execute = virtual_bond_execute;
>
> INIT_LIST_HEAD(virtual_queue(ve));
> ve->base.execlists.queue_priority_hint = INT_MIN;
> - tasklet_setup(&ve->base.sched.tasklet, virtual_submission_tasklet);
>
> intel_context_init(&ve->context, &ve->base);
>
> @@ -3427,6 +3425,9 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
> ve->base.mask,
> ENGINE_VIRTUAL);
>
> + ve->base.sched.submit_request = virtual_submit_request;
> + tasklet_setup(&ve->base.sched.tasklet, virtual_submission_tasklet);
> +
> virtual_engine_initial_hint(ve);
> return &ve->context;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 4a8f982a1a4f..e5cb92c7d0f8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -820,7 +820,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
> __intel_gt_reset(gt, ALL_ENGINES);
>
> for_each_engine(engine, gt, id)
> - engine->submit_request = nop_submit_request;
> + engine->sched.submit_request = nop_submit_request;
>
> /*
> * Make sure no request can slip through without getting completed by
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 8af1bc77e15e..a7d49ea71900 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -970,12 +970,12 @@ static void gen6_bsd_submit_request(struct i915_request *request)
>
> static void i9xx_set_default_submission(struct intel_engine_cs *engine)
> {
> - engine->submit_request = i9xx_submit_request;
> + engine->sched.submit_request = i9xx_submit_request;
> }
>
> static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
> {
> - engine->submit_request = gen6_bsd_submit_request;
> + engine->sched.submit_request = gen6_bsd_submit_request;
> }
>
> static void ring_release(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
> index 8b1c2727d25c..cae736e34bda 100644
> --- a/drivers/gpu/drm/i915/gt/mock_engine.c
> +++ b/drivers/gpu/drm/i915/gt/mock_engine.c
> @@ -302,7 +302,8 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
> engine->base.request_alloc = mock_request_alloc;
> engine->base.emit_flush = mock_emit_flush;
> engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb;
> - engine->base.submit_request = mock_submit_request;
> +
> + engine->base.sched.submit_request = mock_submit_request;
>
> engine->base.reset.prepare = mock_reset_prepare;
> engine->base.reset.rewind = mock_reset_rewind;
> @@ -333,6 +334,7 @@ int mock_engine_init(struct intel_engine_cs *engine)
> engine->name,
> engine->mask,
> ENGINE_MOCK);
> + engine->sched.submit_request = mock_submit_request;
>
> intel_engine_init_execlists(engine);
> intel_engine_init__pm(engine);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 15e4ec5ae73a..db6ac5a12834 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -572,7 +572,7 @@ static int guc_resume(struct intel_engine_cs *engine)
>
> static void guc_set_default_submission(struct intel_engine_cs *engine)
> {
> - engine->submit_request = i915_request_enqueue;
> + engine->sched.submit_request = i915_request_enqueue;
> }
>
> static void guc_release(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index 1b52dcaa023d..c03d3cedf497 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -700,7 +700,7 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
> * proceeding.
> */
> rcu_read_lock();
> - request->engine->submit_request(request);
> + i915_request_get_scheduler(request)->submit_request(request);
> rcu_read_unlock();
> break;
>
> diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
> index 697127981249..620db6430a10 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler.c
> +++ b/drivers/gpu/drm/i915/i915_scheduler.c
> @@ -111,6 +111,8 @@ void i915_sched_init(struct i915_sched *se,
>
> i915_sched_init_ipi(&se->ipi);
>
> + se->submit_request = i915_request_enqueue;
> +
> /*
> * Due to an interesting quirk in lockdep's internal debug tracking,
> * after setting a subclass we must ensure the lock is used. Otherwise,
> diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
> index 9b09749358ad..effd035dcb78 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler_types.h
> +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
> @@ -28,6 +28,15 @@ struct i915_sched {
>
> unsigned long mask; /* available scheduling channels */
>
> + /*
> + * Pass the request to the hardware queue (e.g. directly into
s/hardware queue/submission backend/ ?
> + * the legacy ringbuffer or to the end of an execlist).
> + *
> + * This is called from an atomic context with irqs disabled; must
> + * be irq safe.
> + */
> + void (*submit_request)(struct i915_request *rq);
> +
> struct list_head requests; /* active request, on HW */
> struct list_head hold; /* ready requests, but on hold */
> /**
> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
> index 39c619bccb74..8035ea7565ed 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_request.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c
> @@ -242,10 +242,9 @@ static int igt_request_rewind(void *arg)
> i915_request_get(vip);
> i915_request_add(vip);
> rcu_read_lock();
> - request->engine->submit_request(request);
> + i915_request_get_scheduler(request)->submit_request(request);
> rcu_read_unlock();
>
> -
> if (i915_request_wait(vip, 0, HZ) == -ETIME) {
> pr_err("timed out waiting for high priority request\n");
> goto err;
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
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next prev parent reply other threads:[~2021-02-04 14:13 UTC|newest]
Thread overview: 103+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 8:56 [Intel-gfx] [PATCH 01/57] drm/i915/gt: Restrict the GT clock override to just Icelake Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 02/57] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers Chris Wilson
2021-02-01 14:34 ` Mika Kuoppala
2021-02-01 8:56 ` [Intel-gfx] [PATCH 03/57] drm/i915/selftests: Exercise cross-process context isolation Chris Wilson
2021-02-01 16:37 ` Mika Kuoppala
2021-02-01 8:56 ` [Intel-gfx] [PATCH 04/57] drm/i915: Protect against request freeing during cancellation on wedging Chris Wilson
2021-02-02 9:55 ` Mika Kuoppala
2021-02-01 8:56 ` [Intel-gfx] [PATCH 05/57] drm/i915: Take rcu_read_lock for querying fence's driver/timeline names Chris Wilson
2021-02-02 18:33 ` Mika Kuoppala
2021-02-01 8:56 ` [Intel-gfx] [PATCH 06/57] drm/i915/gt: Always flush the submission queue on checking for idle Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 07/57] drm/i915/gt: Move engine setup out of set_default_submission Chris Wilson
2021-02-02 11:57 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 08/57] drm/i915/gt: Move submission_method into intel_gt Chris Wilson
2021-02-02 12:03 ` Tvrtko Ursulin
2021-02-02 12:18 ` Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 09/57] drm/i915: Replace engine->schedule() with a known request operation Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 10/57] drm/i915: Restructure priority inheritance Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 11/57] drm/i915/selftests: Measure set-priority duration Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 12/57] drm/i915/selftests: Exercise priority inheritance around an engine loop Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 13/57] drm/i915/selftests: Force a rewind if at first we don't succeed Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 14/57] drm/i915: Improve DFS for priority inheritance Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 15/57] drm/i915: Extract request submission from execlists Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 16/57] drm/i915: Extract request rewinding " Chris Wilson
2021-02-02 13:08 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 17/57] drm/i915: Extract request suspension from the execlists Chris Wilson
2021-02-02 13:15 ` Tvrtko Ursulin
2021-02-02 13:26 ` Chris Wilson
2021-02-02 13:32 ` Tvrtko Ursulin
2021-02-02 13:27 ` Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 18/57] drm/i915: Extract the ability to defer and rerun a request later Chris Wilson
2021-02-02 13:18 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 19/57] drm/i915: Fix the iterative dfs for defering requests Chris Wilson
2021-02-02 14:10 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 20/57] drm/i915: Wrap access to intel_engine.active Chris Wilson
2021-02-04 11:07 ` Tvrtko Ursulin
2021-02-04 11:18 ` Chris Wilson
2021-02-04 11:56 ` Chris Wilson
2021-02-04 12:08 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 21/57] drm/i915: Move common active lists from engine to i915_scheduler Chris Wilson
2021-02-04 11:12 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 22/57] drm/i915: Move scheduler queue Chris Wilson
2021-02-04 11:19 ` Tvrtko Ursulin
2021-02-04 11:32 ` Chris Wilson
2021-02-04 11:40 ` Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 23/57] drm/i915: Move tasklet from execlists to sched Chris Wilson
2021-02-04 14:06 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 24/57] drm/i915/gt: Only kick the scheduler on timeslice/preemption change Chris Wilson
2021-02-04 14:09 ` Tvrtko Ursulin
2021-02-04 14:43 ` Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 25/57] drm/i915: Move submit_request to i915_sched_engine Chris Wilson
2021-02-04 14:13 ` Tvrtko Ursulin [this message]
2021-02-04 14:45 ` Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 26/57] drm/i915: Move finding the current active request to the scheduler Chris Wilson
2021-02-04 14:30 ` Tvrtko Ursulin
2021-02-04 14:59 ` Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 27/57] drm/i915: Show execlists queues when dumping state Chris Wilson
2021-02-04 15:04 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 28/57] drm/i915: Wrap i915_request_use_semaphores() Chris Wilson
2021-02-04 15:05 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 29/57] drm/i915: Move scheduler flags Chris Wilson
2021-02-04 15:14 ` Tvrtko Ursulin
2021-02-04 16:05 ` Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 30/57] drm/i915: Move timeslicing flag to scheduler Chris Wilson
2021-02-04 15:18 ` Tvrtko Ursulin
2021-02-04 16:11 ` Chris Wilson
2021-02-05 9:48 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 31/57] drm/i915/gt: Declare when we enabled timeslicing Chris Wilson
2021-02-04 15:26 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 32/57] drm/i915: Move needs-breadcrumb flags to scheduler Chris Wilson
2021-02-04 15:28 ` Tvrtko Ursulin
2021-02-04 16:12 ` Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 33/57] drm/i915: Move busywaiting control to the scheduler Chris Wilson
2021-02-04 15:32 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 34/57] drm/i915: Move preempt-reset flag " Chris Wilson
2021-02-04 15:34 ` Tvrtko Ursulin
2021-02-01 8:56 ` [Intel-gfx] [PATCH 35/57] drm/i915: Replace priolist rbtree with a skiplist Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 36/57] drm/i915: Wrap cmpxchg64 with try_cmpxchg64() helper Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 37/57] drm/i915: Fair low-latency scheduling Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 38/57] drm/i915/gt: Specify a deadline for the heartbeat Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 39/57] drm/i915: Extend the priority boosting for the display with a deadline Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 40/57] drm/i915/gt: Support virtual engine queues Chris Wilson
2021-02-01 8:56 ` [Intel-gfx] [PATCH 41/57] drm/i915: Move saturated workload detection back to the context Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 42/57] drm/i915: Bump default timeslicing quantum to 5ms Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 43/57] drm/i915/gt: Delay taking irqoff for execlists submission Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 44/57] drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 45/57] drm/i915/gt: Track timeline GGTT offset separately from subpage offset Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 46/57] drm/i915/gt: Add timeline "mode" Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 47/57] drm/i915/gt: Use indices for writing into relative timelines Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 48/57] drm/i915/selftests: Exercise relative timeline modes Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 49/57] drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 50/57] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 51/57] drm/i915/gt: Couple tasklet scheduling for all CS interrupts Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 52/57] drm/i915/gt: Support creation of 'internal' rings Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 53/57] drm/i915/gt: Use client timeline address for seqno writes Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 54/57] drm/i915/gt: Infrastructure for ring scheduling Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 55/57] drm/i915/gt: Implement ring scheduler for gen4-7 Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 56/57] drm/i915/gt: Enable ring scheduling for gen5-7 Chris Wilson
2021-02-01 8:57 ` [Intel-gfx] [PATCH 57/57] drm/i915: Support secure dispatch on gen6/gen7 Chris Wilson
2021-02-01 14:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/57] drm/i915/gt: Restrict the GT clock override to just Icelake Patchwork
2021-02-01 14:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-01 14:15 ` [Intel-gfx] [PATCH 01/57] " Mika Kuoppala
2021-02-01 14:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/57] " Patchwork
2021-02-01 19:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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