From: Sean Christopherson <sean.j.christopherson@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Sean Christopherson <sean.j.christopherson@intel.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Xiaoyao Li <xiaoyao.li@intel.com>
Subject: [PATCH v2 51/66] KVM: x86: Set emulated/transmuted feature bits via kvm_cpu_caps
Date: Mon, 2 Mar 2020 15:56:54 -0800 [thread overview]
Message-ID: <20200302235709.27467-52-sean.j.christopherson@intel.com> (raw)
In-Reply-To: <20200302235709.27467-1-sean.j.christopherson@intel.com>
Set emulated and transmuted (set based on other features) feature bits
via kvm_cpu_caps now that the CPUID output for KVM_GET_SUPPORTED_CPUID
is direcly overidden with kvm_cpu_caps.
Note, VMX emulation of UMIP already sets kvm_cpu_caps.
No functional change intended.
Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
---
arch/x86/kvm/cpuid.c | 72 +++++++++++++++++++++---------------------
arch/x86/kvm/svm.c | 18 +++--------
arch/x86/kvm/vmx/vmx.c | 18 +----------
3 files changed, 42 insertions(+), 66 deletions(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 5fef02dbf4e1..c0ee0cb33a37 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -315,6 +315,8 @@ void kvm_set_cpu_caps(void)
0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
F(F16C) | F(RDRAND)
);
+ /* KVM emulates x2apic in software irrespective of host support. */
+ kvm_cpu_cap_set(X86_FEATURE_X2APIC);
kvm_cpu_cap_mask(CPUID_1_EDX,
F(FPU) | F(VME) | F(DE) | F(PSE) |
@@ -351,6 +353,17 @@ void kvm_set_cpu_caps(void)
F(MD_CLEAR)
);
+ /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
+ kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
+ kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
+
+ if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
+ kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
+ if (boot_cpu_has(X86_FEATURE_STIBP))
+ kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
+ if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
+ kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
+
kvm_cpu_cap_mask(CPUID_7_1_EAX,
F(AVX512_BF16)
);
@@ -384,6 +397,29 @@ void kvm_set_cpu_caps(void)
F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON)
);
+ /*
+ * AMD has separate bits for each SPEC_CTRL bit.
+ * arch/x86/kernel/cpu/bugs.c is kind enough to
+ * record that in cpufeatures so use them.
+ */
+ if (boot_cpu_has(X86_FEATURE_IBPB))
+ kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
+ if (boot_cpu_has(X86_FEATURE_IBRS))
+ kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
+ if (boot_cpu_has(X86_FEATURE_STIBP))
+ kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
+ if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
+ kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
+ if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
+ kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
+ /*
+ * The preference is to use SPEC CTRL MSR instead of the
+ * VIRT_SPEC MSR.
+ */
+ if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
+ !boot_cpu_has(X86_FEATURE_AMD_SSBD))
+ kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
+
/*
* Hide all SVM features by default, SVM will set the cap bits for
* features it emulates and/or exposes for L1.
@@ -492,9 +528,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
case 1:
cpuid_entry_override(entry, CPUID_1_EDX);
cpuid_entry_override(entry, CPUID_1_ECX);
- /* we support x2apic emulation even if host does not support
- * it since we emulate x2apic in software */
- cpuid_entry_set(entry, X86_FEATURE_X2APIC);
break;
case 2:
/*
@@ -540,17 +573,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
cpuid_entry_override(entry, CPUID_7_ECX);
cpuid_entry_override(entry, CPUID_7_EDX);
- /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
- cpuid_entry_set(entry, X86_FEATURE_TSC_ADJUST);
- cpuid_entry_set(entry, X86_FEATURE_ARCH_CAPABILITIES);
-
- if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
- cpuid_entry_set(entry, X86_FEATURE_SPEC_CTRL);
- if (boot_cpu_has(X86_FEATURE_STIBP))
- cpuid_entry_set(entry, X86_FEATURE_INTEL_STIBP);
- if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
- cpuid_entry_set(entry, X86_FEATURE_SPEC_CTRL_SSBD);
-
/* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
if (entry->eax == 1) {
entry = do_host_cpuid(array, function, 1);
@@ -722,28 +744,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
entry->eax = g_phys_as | (virt_as << 8);
entry->edx = 0;
cpuid_entry_override(entry, CPUID_8000_0008_EBX);
- /*
- * AMD has separate bits for each SPEC_CTRL bit.
- * arch/x86/kernel/cpu/bugs.c is kind enough to
- * record that in cpufeatures so use them.
- */
- if (boot_cpu_has(X86_FEATURE_IBPB))
- cpuid_entry_set(entry, X86_FEATURE_AMD_IBPB);
- if (boot_cpu_has(X86_FEATURE_IBRS))
- cpuid_entry_set(entry, X86_FEATURE_AMD_IBRS);
- if (boot_cpu_has(X86_FEATURE_STIBP))
- cpuid_entry_set(entry, X86_FEATURE_AMD_STIBP);
- if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
- cpuid_entry_set(entry, X86_FEATURE_AMD_SSBD);
- if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
- cpuid_entry_set(entry, X86_FEATURE_AMD_SSB_NO);
- /*
- * The preference is to use SPEC CTRL MSR instead of the
- * VIRT_SPEC MSR.
- */
- if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
- !boot_cpu_has(X86_FEATURE_AMD_SSBD))
- cpuid_entry_set(entry, X86_FEATURE_VIRT_SSBD);
break;
}
case 0x80000019:
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 964331106e9a..d351007eb7f9 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1377,6 +1377,11 @@ static __init void svm_set_cpu_caps(void)
if (nested)
kvm_cpu_cap_set(X86_FEATURE_SVM);
+ /* CPUID 0x80000008 */
+ if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
+ boot_cpu_has(X86_FEATURE_AMD_SSBD))
+ kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
+
/* CPUID 0x8000000A */
/* Support next_rip if host supports it */
kvm_cpu_cap_check_and_set(X86_FEATURE_NRIPS);
@@ -6047,22 +6052,9 @@ static void svm_cpuid_update(struct kvm_vcpu *vcpu)
APICV_INHIBIT_REASON_NESTED);
}
-/*
- * Vendor specific emulation must be handled via ->set_supported_cpuid(), not
- * svm_set_cpu_caps(), as capabilities configured during hardware_setup() are
- * masked against hardware/kernel support, i.e. they'd be lost.
- *
- * Note, setting a flag based on a *different* feature, e.g. setting VIRT_SSBD
- * if LS_CFG_SSBD or AMD_SSBD is supported, is effectively emulation.
- */
static void svm_set_supported_cpuid(struct kvm_cpuid_entry2 *entry)
{
switch (entry->function) {
- case 0x80000008:
- if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
- boot_cpu_has(X86_FEATURE_AMD_SSBD))
- cpuid_entry_set(entry, X86_FEATURE_VIRT_SSBD);
- break;
case 0x8000000A:
entry->eax = 1; /* SVM revision 1 */
entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index be2aecda733b..d5a5e8f987c8 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -7119,25 +7119,9 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
}
}
-/*
- * Vendor specific emulation must be handled via ->set_supported_cpuid(), not
- * vmx_set_cpu_caps(), as capabilities configured during hardware_setup() are
- * masked against hardware/kernel support, i.e. they'd be lost.
- */
static void vmx_set_supported_cpuid(struct kvm_cpuid_entry2 *entry)
{
- switch (entry->function) {
- case 0x7:
- /*
- * UMIP needs to be manually set even though vmx_set_cpu_caps()
- * also sets UMIP since do_host_cpuid() will drop it.
- */
- if (vmx_umip_emulated())
- cpuid_entry_set(entry, X86_FEATURE_UMIP);
- break;
- default:
- break;
- }
+
}
static __init void vmx_set_cpu_caps(void)
--
2.24.1
next prev parent reply other threads:[~2020-03-03 0:01 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-02 23:56 [PATCH v2 00/66] KVM: x86: Introduce KVM cpu caps Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 01/66] KVM: x86: Return -E2BIG when KVM_GET_SUPPORTED_CPUID hits max entries Sean Christopherson
2020-03-03 14:16 ` Paolo Bonzini
2020-03-03 15:17 ` Sean Christopherson
2020-03-03 19:47 ` Jim Mattson
2020-03-02 23:56 ` [PATCH v2 02/66] KVM: x86: Refactor loop around do_cpuid_func() to separate helper Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 03/66] KVM: x86: Simplify handling of Centaur CPUID leafs Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 04/66] KVM: x86: Clean up error handling in kvm_dev_ioctl_get_cpuid() Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 05/66] KVM: x86: Check userapce CPUID array size after validating sub-leaf Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 06/66] KVM: x86: Move CPUID 0xD.1 handling out of the index>0 loop Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 07/66] KVM: x86: Check for CPUID 0xD.N support before validating array size Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 08/66] KVM: x86: Warn on zero-size save state for valid CPUID 0xD.N sub-leaf Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 09/66] KVM: x86: Refactor CPUID 0xD.N sub-leaf entry creation Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 10/66] KVM: x86: Clean up CPUID 0x7 sub-leaf loop Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 11/66] KVM: x86: Drop the explicit @index from do_cpuid_7_mask() Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 12/66] KVM: x86: Drop redundant boot cpu checks on SSBD feature bits Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 13/66] KVM: x86: Consolidate CPUID array max num entries checking Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 14/66] KVM: x86: Hoist loop counter and terminator to top of __do_cpuid_func() Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 15/66] KVM: x86: Refactor CPUID 0x4 and 0x8000001d handling Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 16/66] KVM: x86: Encapsulate CPUID entries and metadata in struct Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 17/66] KVM: x86: Drop redundant array size check Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 18/66] KVM: x86: Use common loop iterator when handling CPUID 0xD.N Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 19/66] KVM: VMX: Add helpers to query Intel PT mode Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 20/66] KVM: x86: Calculate the supported xcr0 mask at load time Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 21/66] KVM: x86: Use supported_xcr0 to detect MPX support Sean Christopherson
2020-03-03 14:34 ` Paolo Bonzini
2020-03-02 23:56 ` [PATCH v2 22/66] KVM: x86: Make kvm_mpx_supported() an inline function Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 23/66] KVM: x86: Clear output regs for CPUID 0x14 if PT isn't exposed to guest Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 24/66] KVM: x86: Drop explicit @func param from ->set_supported_cpuid() Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 25/66] KVM: x86: Use u32 for holding CPUID register value in helpers Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 26/66] KVM: x86: Replace bare "unsigned" with "unsigned int" in cpuid helpers Sean Christopherson
2020-03-03 15:43 ` Vitaly Kuznetsov
2020-03-02 23:56 ` [PATCH v2 27/66] KVM: x86: Introduce cpuid_entry_{get,has}() accessors Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 28/66] KVM: x86: Introduce cpuid_entry_{change,set,clear}() mutators Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 29/66] KVM: x86: Refactor cpuid_mask() to auto-retrieve the register Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 30/66] KVM: x86: Handle MPX CPUID adjustment in VMX code Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 31/66] KVM: x86: Handle INVPCID " Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 32/66] KVM: x86: Handle UMIP emulation " Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 33/66] KVM: x86: Handle PKU " Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 34/66] KVM: x86: Handle RDTSCP " Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 35/66] KVM: x86: Handle Intel PT " Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 36/66] KVM: x86: Handle GBPAGE CPUID adjustment for EPT " Sean Christopherson
2020-03-03 14:59 ` Paolo Bonzini
2020-03-03 15:35 ` Sean Christopherson
2020-03-03 15:40 ` Paolo Bonzini
2020-03-03 15:44 ` Sean Christopherson
2020-03-03 15:47 ` Paolo Bonzini
2020-03-03 15:54 ` Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 37/66] KVM: x86: Refactor handling of XSAVES CPUID adjustment Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 38/66] KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking Sean Christopherson
2020-03-03 15:51 ` Vitaly Kuznetsov
2020-03-02 23:56 ` [PATCH v2 39/66] KVM: SVM: Convert feature updates from CPUID to KVM cpu caps Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 40/66] KVM: VMX: " Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 41/66] KVM: x86: Move XSAVES CPUID adjust to VMX's KVM cpu cap update Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 42/66] KVM: x86: Add a helper to check kernel support when setting cpu cap Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 43/66] KVM: x86: Use KVM cpu caps to mark CR4.LA57 as not-reserved Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 44/66] KVM: x86: Use KVM cpu caps to track UMIP emulation Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 45/66] KVM: x86: Fold CPUID 0x7 masking back into __do_cpuid_func() Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 46/66] KVM: x86: Remove the unnecessary loop on CPUID 0x7 sub-leafs Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 47/66] KVM: x86: Squash CPUID 0x2.0 insanity for modern CPUs Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 48/66] KVM: x86: Remove stateful CPUID handling Sean Christopherson
2020-03-03 15:59 ` Vitaly Kuznetsov
2020-03-03 19:23 ` Jim Mattson
2020-03-02 23:56 ` [PATCH v2 49/66] KVM: x86: Do host CPUID at load time to mask KVM cpu caps Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 50/66] KVM: x86: Override host CPUID results with kvm_cpu_caps Sean Christopherson
2020-03-03 15:22 ` Paolo Bonzini
2020-03-03 15:56 ` Sean Christopherson
2020-03-02 23:56 ` Sean Christopherson [this message]
2020-03-02 23:56 ` [PATCH v2 52/66] KVM: x86: Use kvm_cpu_caps to detect Intel PT support Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 53/66] KVM: x86: Do kvm_cpuid_array capacity checks in terminal functions Sean Christopherson
2020-03-03 16:03 ` Vitaly Kuznetsov
2020-03-02 23:56 ` [PATCH v2 54/66] KVM: x86: Use KVM cpu caps to detect MSR_TSC_AUX virt support Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 55/66] KVM: VMX: Directly use VMX capabilities helper to detect RDTSCP support Sean Christopherson
2020-03-02 23:56 ` [PATCH v2 56/66] KVM: x86: Check for Intel PT MSR virtualization using KVM cpu caps Sean Christopherson
2020-03-02 23:57 ` [PATCH v2 57/66] KVM: VMX: Directly query Intel PT mode when refreshing PMUs Sean Christopherson
2020-03-02 23:57 ` [PATCH v2 58/66] KVM: SVM: Refactor logging of NPT enabled/disabled Sean Christopherson
2020-03-02 23:57 ` [PATCH v2 59/66] KVM: x86/mmu: Merge kvm_{enable,disable}_tdp() into a common function Sean Christopherson
2020-03-02 23:57 ` [PATCH v2 60/66] KVM: x86/mmu: Configure max page level during hardware setup Sean Christopherson
2020-03-02 23:57 ` [PATCH v2 61/66] KVM: x86: Don't propagate MMU lpage support to memslot.disallow_lpage Sean Christopherson
2020-03-03 15:31 ` Paolo Bonzini
2020-03-03 16:00 ` Sean Christopherson
2020-03-02 23:57 ` [PATCH v2 62/66] KVM: Drop largepages_enabled and its accessor/mutator Sean Christopherson
2020-03-02 23:57 ` [PATCH v2 63/66] KVM: x86: Move VMX's host_efer to common x86 code Sean Christopherson
2020-03-02 23:57 ` [PATCH v2 64/66] KVM: nSVM: Expose SVM features to L1 iff nested is enabled Sean Christopherson
2020-03-03 16:12 ` Vitaly Kuznetsov
2020-03-03 18:37 ` Jim Mattson
2020-03-02 23:57 ` [PATCH v2 65/66] KVM: nSVM: Advertise and enable NRIPS for L1 iff nrips " Sean Christopherson
2020-03-03 16:14 ` Vitaly Kuznetsov
2020-03-02 23:57 ` [PATCH v2 66/66] KVM: x86: Move nSVM CPUID 0x8000000A handing into common x86 code Sean Christopherson
2020-03-03 15:35 ` Paolo Bonzini
2020-03-03 15:37 ` Sean Christopherson
2020-03-03 16:48 ` [PATCH v2 00/66] KVM: x86: Introduce KVM cpu caps Vitaly Kuznetsov
2020-03-06 8:27 ` Paolo Bonzini
2020-03-09 20:11 ` Sean Christopherson
2020-03-11 18:37 ` Paolo Bonzini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200302235709.27467-52-sean.j.christopherson@intel.com \
--to=sean.j.christopherson@intel.com \
--cc=jmattson@google.com \
--cc=joro@8bytes.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=vkuznets@redhat.com \
--cc=wanpengli@tencent.com \
--cc=xiaoyao.li@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).