From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: libvir-list@redhat.com, "Paolo Bonzini" <pbonzini@redhat.com>,
"Laurent Vivier" <laurent@vivier.eu>,
kvm@vger.kernel.org, "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Paul Burton" <paulburton@kernel.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PULL 37/66] target/mips: Introduce ase_msa_available() helper
Date: Thu, 7 Jan 2021 23:22:24 +0100 [thread overview]
Message-ID: <20210107222253.20382-38-f4bug@amsat.org> (raw)
In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org>
Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-2-f4bug@amsat.org>
---
target/mips/cpu.h | 6 ++++++
target/mips/cpu.c | 2 +-
target/mips/kvm.c | 12 ++++++------
target/mips/translate.c | 6 ++----
4 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 9c45744c5c1..b9e227a30e9 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1299,6 +1299,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
+/* Check presence of MSA implementation */
+static inline bool ase_msa_available(CPUMIPSState *env)
+{
+ return env->CP0_Config3 & (1 << CP0C3_MSAP);
+}
+
/* Check presence of multi-threading ASE implementation */
static inline bool ase_mt_available(CPUMIPSState *env)
{
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 55c6a054bba..45375ebc45c 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -532,7 +532,7 @@ static void mips_cpu_reset(DeviceState *dev)
}
/* MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
msa_reset(env);
}
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index a5b6fe35dbc..84fb10ea35d 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -79,7 +79,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
}
}
- if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (kvm_mips_msa_cap && ase_msa_available(env)) {
ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0);
if (ret < 0) {
/* mark unsupported so it gets disabled on reset */
@@ -105,7 +105,7 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu)
warn_report("KVM does not support FPU, disabling");
env->CP0_Config1 &= ~(1 << CP0C1_FP);
}
- if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (!kvm_mips_msa_cap && ase_msa_available(env)) {
warn_report("KVM does not support MSA, disabling");
env->CP0_Config3 &= ~(1 << CP0C3_MSAP);
}
@@ -618,7 +618,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
* FPU register state is a subset of MSA vector state, so don't put FPU
* registers if we're emulating a CPU with MSA.
*/
- if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if (!ase_msa_available(env)) {
/* Floating point registers */
for (i = 0; i < 32; ++i) {
if (env->CP0_Status & (1 << CP0St_FR)) {
@@ -637,7 +637,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
}
/* Only put MSA state if we're emulating a CPU with MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
/* MSA Control Registers */
if (level == KVM_PUT_FULL_STATE) {
err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR,
@@ -698,7 +698,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
* FPU register state is a subset of MSA vector state, so don't save FPU
* registers if we're emulating a CPU with MSA.
*/
- if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if (!ase_msa_available(env)) {
/* Floating point registers */
for (i = 0; i < 32; ++i) {
if (env->CP0_Status & (1 << CP0St_FR)) {
@@ -717,7 +717,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
}
/* Only get MSA state if we're emulating a CPU with MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
/* MSA Control Registers */
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR,
&env->msair);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 69fa8a50790..c01db5f9d39 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24920,8 +24920,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
gen_trap(ctx, op1, rs, rt, -1);
break;
case OPC_LSA: /* OPC_PMON */
- if ((ctx->insn_flags & ISA_MIPS_R6) ||
- (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
} else {
/* Pmon entry point, also R4010 selsl */
@@ -25023,8 +25022,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DLSA:
- if ((ctx->insn_flags & ISA_MIPS_R6) ||
- (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
}
break;
--
2.26.2
next prev parent reply other threads:[~2021-01-07 22:26 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-07 22:21 [PULL 00/66] MIPS patches for 2021-01-07 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 02/66] target/mips: Replace CP0_Config0 magic values by proper definitions Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 03/66] target/mips/addr: Add translation helpers for KSEG1 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 06/66] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 08/66] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 10/66] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 18/66] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 19/66] target/mips: Inline cpu_state_reset() in mips_cpu_reset() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 20/66] target/mips: Extract FPU helpers to 'fpu_helper.h' Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 23/66] target/mips: Move common helpers from helper.c to cpu.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 24/66] target/mips: Rename helper.c as tlb_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 25/66] target/mips: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 26/66] target/mips: Move mmu_init() functions to tlb_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 27/66] target/mips: Rename translate_init.c as cpu-defs.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 28/66] target/mips/translate: Extract DisasContext structure Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 29/66] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h' Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 33/66] target/mips: Extract FPU specific definitions to translate.h Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 34/66] target/mips: Only build TCG code when CONFIG_TCG is set Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 35/66] target/mips/translate: Extract decode_opc_legacy() from decode_opc() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode Philippe Mathieu-Daudé
2021-01-07 22:22 ` Philippe Mathieu-Daudé [this message]
2021-01-07 22:22 ` [PULL 38/66] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 40/66] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 41/66] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 43/66] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 46/66] target/mips: Move msa_reset() to msa_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 47/66] target/mips: Extract MSA helpers from op_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 48/66] target/mips: Extract MSA helper definitions Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 49/66] target/mips: Declare gen_msa/_branch() in 'translate.h' Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 52/66] target/mips: Introduce decode tree bindings for MSA ASE Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 53/66] target/mips: Use decode_ase_msa() generated from decodetree Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 54/66] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 56/66] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 57/66] target/mips: Remove now unreachable LSA/DLSA opcodes code Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 58/66] target/mips: Convert Rel6 Special2 opcode to decodetree Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 59/66] target/mips: Convert Rel6 COP1X " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 60/66] target/mips: Convert Rel6 CACHE/PREF opcodes " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 61/66] target/mips: Convert Rel6 LWL/LWR/SWL/SWR " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 62/66] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 63/66] target/mips: Convert Rel6 LDL/LDR/SDL/SDR " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 64/66] target/mips: Convert Rel6 LLD/SCD " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 65/66] target/mips: Convert Rel6 LL/SC " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 66/66] docs/system: Remove deprecated 'fulong2e' machine alias Philippe Mathieu-Daudé
2021-01-07 22:34 ` [PULL 00/66] MIPS patches for 2021-01-07 Philippe Mathieu-Daudé
2021-01-07 22:52 ` no-reply
2021-01-08 10:35 ` Peter Maydell
[not found] ` <CAAdtpL7CKT3gG8VCP4K1COjfqbG+pP_p_LG5Py8rmjUJH4foMg@mail.gmail.com>
2021-01-08 11:54 ` Peter Maydell
[not found] ` <CAE2XoE8YWYnvap+Ox7hWaKfpRjDS+vEKpP61F0w3NkkKse5_iA@mail.gmail.com>
2021-01-08 18:48 ` Richard Henderson
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