From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: libvir-list@redhat.com, "Paolo Bonzini" <pbonzini@redhat.com>,
"Laurent Vivier" <laurent@vivier.eu>,
kvm@vger.kernel.org, "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Paul Burton" <paulburton@kernel.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PULL 06/66] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
Date: Thu, 7 Jan 2021 23:21:53 +0100 [thread overview]
Message-ID: <20210107222253.20382-7-f4bug@amsat.org> (raw)
In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org>
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
---
target/mips/mips-defs.h | 8 ++++----
target/mips/translate_init.c.inc | 14 +++++++-------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 48544ba73b4..1630ae20d59 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -72,12 +72,12 @@
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
/* MIPS Technologies "Release 1" */
-#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
-#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
+#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32)
+#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64)
/* MIPS Technologies "Release 2" */
-#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
-#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
+#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS32R2)
+#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2 | ISA_MIPS64R2)
/* MIPS Technologies "Release 3" */
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index cac3d241831..0ba3cf18ef7 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -72,7 +72,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1278FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32,
+ .insn_flags = CPU_MIPS32R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -94,7 +94,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1258FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
.mmu_type = MMU_TYPE_FMT,
},
{
@@ -114,7 +114,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1278FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32,
+ .insn_flags = CPU_MIPS32R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -134,7 +134,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x1258FF17,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+ .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
.mmu_type = MMU_TYPE_FMT,
},
{
@@ -552,7 +552,7 @@ const mips_def_t mips_defs[] =
.CP0_Status_rw_bitmask = 0x12F8FFFF,
.SEGBITS = 42,
.PABITS = 36,
- .insn_flags = CPU_MIPS64,
+ .insn_flags = CPU_MIPS64R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -578,7 +578,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 36,
- .insn_flags = CPU_MIPS64,
+ .insn_flags = CPU_MIPS64R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -607,7 +607,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 36,
- .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
+ .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D,
.mmu_type = MMU_TYPE_R4000,
},
{
--
2.26.2
next prev parent reply other threads:[~2021-01-07 22:24 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-07 22:21 [PULL 00/66] MIPS patches for 2021-01-07 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 02/66] target/mips: Replace CP0_Config0 magic values by proper definitions Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 03/66] target/mips/addr: Add translation helpers for KSEG1 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition Philippe Mathieu-Daudé
2021-01-07 22:21 ` Philippe Mathieu-Daudé [this message]
2021-01-07 22:21 ` [PULL 07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 08/66] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 10/66] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 18/66] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 19/66] target/mips: Inline cpu_state_reset() in mips_cpu_reset() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 20/66] target/mips: Extract FPU helpers to 'fpu_helper.h' Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 23/66] target/mips: Move common helpers from helper.c to cpu.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 24/66] target/mips: Rename helper.c as tlb_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 25/66] target/mips: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 26/66] target/mips: Move mmu_init() functions to tlb_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 27/66] target/mips: Rename translate_init.c as cpu-defs.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 28/66] target/mips/translate: Extract DisasContext structure Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 29/66] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h' Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 33/66] target/mips: Extract FPU specific definitions to translate.h Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 34/66] target/mips: Only build TCG code when CONFIG_TCG is set Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 35/66] target/mips/translate: Extract decode_opc_legacy() from decode_opc() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 37/66] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 38/66] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 40/66] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 41/66] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 43/66] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 46/66] target/mips: Move msa_reset() to msa_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 47/66] target/mips: Extract MSA helpers from op_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 48/66] target/mips: Extract MSA helper definitions Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 49/66] target/mips: Declare gen_msa/_branch() in 'translate.h' Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 52/66] target/mips: Introduce decode tree bindings for MSA ASE Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 53/66] target/mips: Use decode_ase_msa() generated from decodetree Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 54/66] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 56/66] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 57/66] target/mips: Remove now unreachable LSA/DLSA opcodes code Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 58/66] target/mips: Convert Rel6 Special2 opcode to decodetree Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 59/66] target/mips: Convert Rel6 COP1X " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 60/66] target/mips: Convert Rel6 CACHE/PREF opcodes " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 61/66] target/mips: Convert Rel6 LWL/LWR/SWL/SWR " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 62/66] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 63/66] target/mips: Convert Rel6 LDL/LDR/SDL/SDR " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 64/66] target/mips: Convert Rel6 LLD/SCD " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 65/66] target/mips: Convert Rel6 LL/SC " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 66/66] docs/system: Remove deprecated 'fulong2e' machine alias Philippe Mathieu-Daudé
2021-01-07 22:34 ` [PULL 00/66] MIPS patches for 2021-01-07 Philippe Mathieu-Daudé
2021-01-07 22:52 ` no-reply
2021-01-08 10:35 ` Peter Maydell
[not found] ` <CAAdtpL7CKT3gG8VCP4K1COjfqbG+pP_p_LG5Py8rmjUJH4foMg@mail.gmail.com>
2021-01-08 11:54 ` Peter Maydell
[not found] ` <CAE2XoE8YWYnvap+Ox7hWaKfpRjDS+vEKpP61F0w3NkkKse5_iA@mail.gmail.com>
2021-01-08 18:48 ` Richard Henderson
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