From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: libvir-list@redhat.com, "Paolo Bonzini" <pbonzini@redhat.com>,
"Laurent Vivier" <laurent@vivier.eu>,
kvm@vger.kernel.org, "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Paul Burton" <paulburton@kernel.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PULL 53/66] target/mips: Use decode_ase_msa() generated from decodetree
Date: Thu, 7 Jan 2021 23:22:40 +0100 [thread overview]
Message-ID: <20210107222253.20382-54-f4bug@amsat.org> (raw)
In-Reply-To: <20210107222253.20382-1-f4bug@amsat.org>
Now that we can decode the MSA ASE with decode_ase_msa(),
use it and remove the previous code, now unreachable.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-21-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/translate.h | 12 ------------
target/mips/msa_translate.c | 29 +----------------------------
target/mips/translate.c | 32 ++++++++++----------------------
3 files changed, 11 insertions(+), 62 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 858e47cf833..35e9c4cd135 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -82,8 +82,6 @@ enum {
OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
- OPC_BZ_V = (0x0B << 21) | OPC_CP1,
- OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
@@ -93,14 +91,6 @@ enum {
OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
- OPC_BZ_B = (0x18 << 21) | OPC_CP1,
- OPC_BZ_H = (0x19 << 21) | OPC_CP1,
- OPC_BZ_W = (0x1A << 21) | OPC_CP1,
- OPC_BZ_D = (0x1B << 21) | OPC_CP1,
- OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
- OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
- OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
- OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
};
#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
@@ -164,8 +154,6 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
-void gen_msa(DisasContext *ctx);
-void gen_msa_branch(DisasContext *ctx, uint32_t op1);
/* decodetree generated */
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
index 5efb0a1fc8a..8a48f889aa2 100644
--- a/target/mips/msa_translate.c
+++ b/target/mips/msa_translate.c
@@ -412,33 +412,6 @@ static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
}
-void gen_msa_branch(DisasContext *ctx, uint32_t op1)
-{
- uint8_t df = (ctx->opcode >> 21) & 0x3;
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- int64_t s16 = (int16_t)ctx->opcode;
-
- switch (op1) {
- case OPC_BZ_V:
- case OPC_BNZ_V:
- gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
- TCG_COND_EQ : TCG_COND_NE);
- break;
- case OPC_BZ_B:
- case OPC_BZ_H:
- case OPC_BZ_W:
- case OPC_BZ_D:
- gen_msa_BxZ(ctx, df, wt, s16, false);
- break;
- case OPC_BNZ_B:
- case OPC_BNZ_H:
- case OPC_BNZ_W:
- case OPC_BNZ_D:
- gen_msa_BxZ(ctx, df, wt, s16, true);
- break;
- }
-}
-
static void gen_msa_i8(DisasContext *ctx)
{
#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
@@ -2188,7 +2161,7 @@ static void gen_msa_vec(DisasContext *ctx)
}
}
-void gen_msa(DisasContext *ctx)
+static void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 01fe4609c9d..3da12e31351 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6,6 +6,7 @@
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -135,8 +136,6 @@ enum {
OPC_JIALC = (0x3E << 26),
/* MDMX ASE specific */
OPC_MDMX = (0x1E << 26),
- /* MSA ASE, same as MDMX */
- OPC_MSA = OPC_MDMX,
/* Cache and prefetch */
OPC_CACHE = (0x2F << 26),
OPC_PREF = (0x33 << 26),
@@ -28828,21 +28827,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
}
- case OPC_BZ_V:
- case OPC_BNZ_V:
- case OPC_BZ_B:
- case OPC_BZ_H:
- case OPC_BZ_W:
- case OPC_BZ_D:
- case OPC_BNZ_B:
- case OPC_BNZ_H:
- case OPC_BNZ_W:
- case OPC_BNZ_D:
- if (ase_msa_available(env)) {
- gen_msa_branch(ctx, op1);
- break;
- }
- /* fall through */
default:
MIPS_INVAL("cp1");
gen_reserved_instruction(ctx);
@@ -29024,16 +29008,13 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
}
break;
- case OPC_MSA: /* OPC_MDMX */
+ case OPC_MDMX: /* MMI_OPC_LQ */
if (ctx->insn_flags & INSN_R5900) {
#if defined(TARGET_MIPS64)
- gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */
+ gen_mmi_lq(env, ctx);
#endif
} else {
/* MDMX: Not implemented. */
- if (ase_msa_available(env)) {
- gen_msa(ctx);
- }
}
break;
case OPC_PCREL:
@@ -29066,6 +29047,13 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_set_label(l1);
}
+ /* Transition to the auto-generated decoder. */
+
+ /* ISA extensions */
+ if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
+ return;
+ }
+
if (!decode_opc_legacy(env, ctx)) {
gen_reserved_instruction(ctx);
}
--
2.26.2
next prev parent reply other threads:[~2021-01-07 22:28 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-07 22:21 [PULL 00/66] MIPS patches for 2021-01-07 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 01/66] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 02/66] target/mips: Replace CP0_Config0 magic values by proper definitions Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 03/66] target/mips/addr: Add translation helpers for KSEG1 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 04/66] target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 05/66] target/mips/mips-defs: Reorder CPU_MIPS5 definition Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 06/66] target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 07/66] target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 08/66] hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 09/66] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 10/66] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Philippe Mathieu-Daudé
2021-01-07 22:21 ` [PULL 12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 18/66] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 19/66] target/mips: Inline cpu_state_reset() in mips_cpu_reset() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 20/66] target/mips: Extract FPU helpers to 'fpu_helper.h' Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 23/66] target/mips: Move common helpers from helper.c to cpu.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 24/66] target/mips: Rename helper.c as tlb_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 25/66] target/mips: Fix code style for checkpatch.pl Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 26/66] target/mips: Move mmu_init() functions to tlb_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 27/66] target/mips: Rename translate_init.c as cpu-defs.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 28/66] target/mips/translate: Extract DisasContext structure Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 29/66] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h' Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 33/66] target/mips: Extract FPU specific definitions to translate.h Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 34/66] target/mips: Only build TCG code when CONFIG_TCG is set Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 35/66] target/mips/translate: Extract decode_opc_legacy() from decode_opc() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 37/66] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 38/66] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 40/66] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 41/66] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 43/66] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 44/66] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 45/66] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 46/66] target/mips: Move msa_reset() to msa_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 47/66] target/mips: Extract MSA helpers from op_helper.c Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 48/66] target/mips: Extract MSA helper definitions Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 49/66] target/mips: Declare gen_msa/_branch() in 'translate.h' Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 51/66] target/mips: Pass TCGCond argument to MSA gen_check_zero_element() Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 52/66] target/mips: Introduce decode tree bindings for MSA ASE Philippe Mathieu-Daudé
2021-01-07 22:22 ` Philippe Mathieu-Daudé [this message]
2021-01-07 22:22 ` [PULL 54/66] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 55/66] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 56/66] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 57/66] target/mips: Remove now unreachable LSA/DLSA opcodes code Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 58/66] target/mips: Convert Rel6 Special2 opcode to decodetree Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 59/66] target/mips: Convert Rel6 COP1X " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 60/66] target/mips: Convert Rel6 CACHE/PREF opcodes " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 61/66] target/mips: Convert Rel6 LWL/LWR/SWL/SWR " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 62/66] target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 63/66] target/mips: Convert Rel6 LDL/LDR/SDL/SDR " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 64/66] target/mips: Convert Rel6 LLD/SCD " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 65/66] target/mips: Convert Rel6 LL/SC " Philippe Mathieu-Daudé
2021-01-07 22:22 ` [PULL 66/66] docs/system: Remove deprecated 'fulong2e' machine alias Philippe Mathieu-Daudé
2021-01-07 22:34 ` [PULL 00/66] MIPS patches for 2021-01-07 Philippe Mathieu-Daudé
2021-01-07 22:52 ` no-reply
2021-01-08 10:35 ` Peter Maydell
[not found] ` <CAAdtpL7CKT3gG8VCP4K1COjfqbG+pP_p_LG5Py8rmjUJH4foMg@mail.gmail.com>
2021-01-08 11:54 ` Peter Maydell
[not found] ` <CAE2XoE8YWYnvap+Ox7hWaKfpRjDS+vEKpP61F0w3NkkKse5_iA@mail.gmail.com>
2021-01-08 18:48 ` Richard Henderson
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