From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
<libvir-list@redhat.com>, <anup.patel@wdc.com>,
<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
<sagark@eecs.berkeley.edu>, <kbastian@mail.uni-paderborn.de>,
<bin.meng@windriver.com>, <fanliang@huawei.com>,
<wu.wubin@huawei.com>, <zhang.zhanghailiang@huawei.com>,
<yinyipeng1@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>
Subject: [PATCH RFC v5 09/12] target/riscv: Add host cpu type
Date: Mon, 12 Apr 2021 14:52:43 +0800 [thread overview]
Message-ID: <20210412065246.1853-10-jiangyifei@huawei.com> (raw)
In-Reply-To: <20210412065246.1853-1-jiangyifei@huawei.com>
'host' type cpu is set isa to RVXLEN simply, more isa info
will obtain from KVM in kvm_arch_init_vcpu()
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/cpu.c | 9 +++++++++
target/riscv/cpu.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dd34ab4978..8132d35a92 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -216,6 +216,12 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
}
#endif
+static void riscv_host_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RVXLEN);
+}
+
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
@@ -706,6 +712,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_init = riscv_cpu_class_init,
},
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
+#if defined(CONFIG_KVM)
+ DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init),
+#endif
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a489d94187..3ca3dad341 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -43,6 +43,7 @@
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
#if defined(TARGET_RISCV32)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
--
2.19.1
next prev parent reply other threads:[~2021-04-12 6:53 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 01/12] linux-header: Update linux/kvm.h Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2021-04-14 22:32 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2021-04-14 22:39 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2021-04-14 22:46 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
2021-04-14 22:48 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
2021-04-14 22:50 ` Alistair Francis
2021-04-30 4:53 ` Anup Patel
2021-05-06 7:59 ` Jiangyifei
2021-04-12 6:52 ` [PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2021-04-12 6:52 ` Yifei Jiang [this message]
2021-04-14 22:33 ` [PATCH RFC v5 09/12] target/riscv: Add host cpu type Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang
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