From: Alistair Francis <alistair23@gmail.com>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
"open list:Overall" <kvm@vger.kernel.org>,
libvir-list@redhat.com,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Anup Patel <anup.patel@wdc.com>,
yinyipeng <yinyipeng1@huawei.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
kvm-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
fanliang@huawei.com, "Wubin (H)" <wu.wubin@huawei.com>,
Zhanghailiang <zhang.zhanghailiang@huawei.com>
Subject: Re: [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers
Date: Thu, 15 Apr 2021 08:39:49 +1000 [thread overview]
Message-ID: <CAKmqyKPnrhC9c2ek5ZetoHaDHir52ihEKzRCXHioOqMNvnVknQ@mail.gmail.com> (raw)
In-Reply-To: <20210412065246.1853-5-jiangyifei@huawei.com>
On Mon, Apr 12, 2021 at 4:58 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/kvm.c | 150 ++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 149 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 0d924be33f..63485d7b65 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -50,13 +50,161 @@ static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
> return id;
> }
>
> +#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
> + KVM_REG_RISCV_CORE_REG(name))
> +
> +#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
> + KVM_REG_RISCV_CSR_REG(name))
> +
> +#define RISCV_FP_F_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_F, idx)
> +
> +#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx)
> +
> +static int kvm_riscv_get_regs_core(CPUState *cs)
> +{
> + int ret = 0;
> + int i;
> + target_ulong reg;
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®);
> + if (ret) {
> + return ret;
> + }
> + env->pc = reg;
> +
> + for (i = 1; i < 32; i++) {
> + __u64 id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
> + ret = kvm_get_one_reg(cs, id, ®);
> + if (ret) {
> + return ret;
> + }
> + env->gpr[i] = reg;
> + }
> +
> + return ret;
> +}
> +
> +static int kvm_riscv_get_regs_csr(CPUState *cs)
> +{
> + int ret = 0;
> + target_ulong reg;
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sstatus), ®);
> + if (ret) {
> + return ret;
> + }
> + env->mstatus = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sie), ®);
> + if (ret) {
> + return ret;
> + }
> + env->mie = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stvec), ®);
> + if (ret) {
> + return ret;
> + }
> + env->stvec = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sscratch), ®);
> + if (ret) {
> + return ret;
> + }
> + env->sscratch = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sepc), ®);
> + if (ret) {
> + return ret;
> + }
> + env->sepc = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, scause), ®);
> + if (ret) {
> + return ret;
> + }
> + env->scause = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, stval), ®);
> + if (ret) {
> + return ret;
> + }
> + env->sbadaddr = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, sip), ®);
> + if (ret) {
> + return ret;
> + }
> + env->mip = reg;
> +
> + ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, satp), ®);
> + if (ret) {
> + return ret;
> + }
> + env->satp = reg;
> +
> + return ret;
> +}
> +
> +static int kvm_riscv_get_regs_fp(CPUState *cs)
> +{
> + int ret = 0;
> + int i;
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + if (riscv_has_ext(env, RVD)) {
> + uint64_t reg;
> + for (i = 0; i < 32; i++) {
> + ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
> + if (ret) {
> + return ret;
> + }
> + env->fpr[i] = reg;
> + }
> + return ret;
> + }
> +
> + if (riscv_has_ext(env, RVF)) {
> + uint32_t reg;
> + for (i = 0; i < 32; i++) {
> + ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
> + if (ret) {
> + return ret;
> + }
> + env->fpr[i] = reg;
> + }
> + return ret;
> + }
> +
> + return ret;
> +}
> +
> const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
> KVM_CAP_LAST_INFO
> };
>
> int kvm_arch_get_registers(CPUState *cs)
> {
> - return 0;
> + int ret = 0;
> +
> + ret = kvm_riscv_get_regs_core(cs);
> + if (ret) {
> + return ret;
> + }
> +
> + ret = kvm_riscv_get_regs_csr(cs);
> + if (ret) {
> + return ret;
> + }
> +
> + ret = kvm_riscv_get_regs_fp(cs);
> + if (ret) {
> + return ret;
> + }
> +
> + return ret;
> }
>
> int kvm_arch_put_registers(CPUState *cs, int level)
> --
> 2.19.1
>
>
next prev parent reply other threads:[~2021-04-14 22:40 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-12 6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 01/12] linux-header: Update linux/kvm.h Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2021-04-14 22:32 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2021-04-14 22:39 ` Alistair Francis [this message]
2021-04-12 6:52 ` [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2021-04-14 22:46 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
2021-04-14 22:48 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
2021-04-14 22:50 ` Alistair Francis
2021-04-30 4:53 ` Anup Patel
2021-05-06 7:59 ` Jiangyifei
2021-04-12 6:52 ` [PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 09/12] target/riscv: Add host cpu type Yifei Jiang
2021-04-14 22:33 ` Alistair Francis
2021-04-12 6:52 ` [PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2021-04-12 6:52 ` [PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang
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