[PATCH 0/2] mips: KVM T&E segment support for TCG

[PATCH 0/2] mips: KVM T&E segment support for TCG

[James Hogan]

MIPS KVM trap & emulate guest kernels have a different segment layout
compared with traditional MIPS kernels, to allow both the user and
kernel code to run from the user address segment without repeatedly
trapping to KVM.

QEMU currently supports this layout only for KVM, but its sometimes
useful to be able to run these kernels in QEMU on a PC. This patchset
enables it for TCG too.

This also paves the way for MIPS KVM VZ support (which uses the normal
virtual memory layout) by abstracting whether user mode kernel segments
are in use.

Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org

James Hogan (2):
  mips: Improve segment defs for KVM T&E guests
  mips: Add KVM T&E segment support for TCG

 hw/mips/addr.c            | 12 ++++++++++++
 hw/mips/mips_malta.c      | 17 +++++++----------
 include/hw/mips/cpudevs.h |  5 +++--
 target/mips/helper.c      | 27 +++++++++++++--------------
 target/mips/translate.c   |  4 ++--
 5 files changed, 37 insertions(+), 28 deletions(-)

-- 
git-series 0.8.10

[PATCH 1/2] mips: Improve segment defs for KVM T&E guests

[James Hogan]

Improve the segment definitions used by get_physical_address() to yield
target_ulong types, e.g. 0xffffffff80000000 instead of 0x80000000. This
is in preparation for enabling emulation of MIPS KVM T&E segments in TCG
MIPS targets, which unlike KVM could potentially have 64-bit
target_ulong. In such a case the offset guest KSEG0 address ends up at
e.g. 0x000000008xxxxxxx instead of 0xffffffff8xxxxxxx.

This also allows the casts to int32_t that force sign extension to be
removed, which removes any confusion due to relational comparison of
unsigned (target_ulong) and signed (int32_t) types.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org
---
 target/mips/helper.c | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/target/mips/helper.c b/target/mips/helper.c
index a2b79e8725a6..05883b9f4251 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -216,14 +216,14 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
     /* effective address (modified for KVM T&E kernel segments) */
     target_ulong address = real_address;
 
-#define USEG_LIMIT      0x7FFFFFFFUL
-#define KSEG0_BASE      0x80000000UL
-#define KSEG1_BASE      0xA0000000UL
-#define KSEG2_BASE      0xC0000000UL
-#define KSEG3_BASE      0xE0000000UL
+#define USEG_LIMIT      ((target_ulong)(int32_t)0x7FFFFFFFUL)
+#define KSEG0_BASE      ((target_ulong)(int32_t)0x80000000UL)
+#define KSEG1_BASE      ((target_ulong)(int32_t)0xA0000000UL)
+#define KSEG2_BASE      ((target_ulong)(int32_t)0xC0000000UL)
+#define KSEG3_BASE      ((target_ulong)(int32_t)0xE0000000UL)
 
-#define KVM_KSEG0_BASE  0x40000000UL
-#define KVM_KSEG2_BASE  0x60000000UL
+#define KVM_KSEG0_BASE  ((target_ulong)(int32_t)0x40000000UL)
+#define KVM_KSEG2_BASE  ((target_ulong)(int32_t)0x60000000UL)
 
     if (kvm_enabled()) {
         /* KVM T&E adds guest kernel segments in useg */
@@ -307,17 +307,17 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
             ret = TLBRET_BADADDR;
         }
 #endif
-    } else if (address < (int32_t)KSEG1_BASE) {
+    } else if (address < KSEG1_BASE) {
         /* kseg0 */
         ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
                                           access_type, mmu_idx,
                                           env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
-    } else if (address < (int32_t)KSEG2_BASE) {
+    } else if (address < KSEG2_BASE) {
         /* kseg1 */
         ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
                                           access_type, mmu_idx,
                                           env->CP0_SegCtl1, 0x1FFFFFFF);
-    } else if (address < (int32_t)KSEG3_BASE) {
+    } else if (address < KSEG3_BASE) {
         /* sseg (kseg2) */
         ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
                                           access_type, mmu_idx,
@@ -974,8 +974,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
         } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) &&
                                     env->CP0_Config5 & (1 << CP0C5_CV))) {
             /* Force KSeg1 for cache errors */
-            env->active_tc.PC = (int32_t)KSEG1_BASE |
-                                (env->CP0_EBase & 0x1FFFF000);
+            env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000);
         } else {
             env->active_tc.PC = env->CP0_EBase & ~0xfff;
         }
-- 
git-series 0.8.10

[PATCH 2/2] mips: Add KVM T&E segment support for TCG

[James Hogan]

MIPS KVM trap & emulate guest kernels have a different segment layout
compared with traditional MIPS kernels, to allow both the user and
kernel code to run from the user address segment without repeatedly
trapping to KVM.

QEMU currently supports this layout only for KVM, but its sometimes
useful to be able to run these kernels in QEMU on a PC, so enable it for
TCG too.

This also paves the way for MIPS KVM VZ support (which uses the normal
virtual memory layout) by abstracting whether user mode kernel segments
are in use.

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org
---
 hw/mips/addr.c            | 12 ++++++++++++
 hw/mips/mips_malta.c      | 17 +++++++----------
 include/hw/mips/cpudevs.h |  5 +++--
 target/mips/helper.c      |  4 ++--
 target/mips/translate.c   |  4 ++--
 5 files changed, 26 insertions(+), 16 deletions(-)

diff --git a/hw/mips/addr.c b/hw/mips/addr.c
index e4e86b4a7548..e552dfca843e 100644
--- a/hw/mips/addr.c
+++ b/hw/mips/addr.c
@@ -24,6 +24,8 @@
 #include "hw/hw.h"
 #include "hw/mips/cpudevs.h"
 
+static int mips_um_ksegs;
+
 uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr)
 {
     return addr & 0x1fffffffll;
@@ -38,3 +40,13 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr)
 {
     return addr | 0x40000000ll;
 }
+
+int mips_um_ksegs_enabled(void)
+{
+    return mips_um_ksegs;
+}
+
+void mips_um_ksegs_enable(void)
+{
+    mips_um_ksegs = 1;
+}
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 3487d16f61eb..f3354362890a 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -816,23 +816,20 @@ static int64_t load_kernel (void)
         exit(1);
     }
 
-    /* Sanity check where the kernel has been linked */
-    if (kvm_enabled()) {
-        if (kernel_entry & 0x80000000ll) {
+    /* Check where the kernel has been linked */
+    if (kernel_entry & 0x80000000ll) {
+        if (kvm_enabled()) {
             error_report("KVM guest kernels must be linked in useg. "
                          "Did you forget to enable CONFIG_KVM_GUEST?");
             exit(1);
         }
 
-        xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
+        xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
     } else {
-        if (!(kernel_entry & 0x80000000ll)) {
-            error_report("KVM guest kernels aren't supported with TCG. "
-                         "Did you unintentionally enable CONFIG_KVM_GUEST?");
-            exit(1);
-        }
+        /* if kernel entry is in useg it is probably a KVM T&E kernel */
+        mips_um_ksegs_enable();
 
-        xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
+        xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
     }
 
     /* load initrd */
diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h
index 698339b83ec7..0c114f486edb 100644
--- a/include/hw/mips/cpudevs.h
+++ b/include/hw/mips/cpudevs.h
@@ -5,11 +5,12 @@
 
 /* Definitions for MIPS CPU internal devices.  */
 
-/* mips_addr.c */
+/* addr.c */
 uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr);
 uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr);
 uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr);
-
+int mips_um_ksegs_enabled(void);
+void mips_um_ksegs_enable(void);
 
 /* mips_int.c */
 void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 05883b9f4251..ca39aca08a64 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -19,10 +19,10 @@
 #include "qemu/osdep.h"
 
 #include "cpu.h"
-#include "sysemu/kvm.h"
 #include "exec/exec-all.h"
 #include "exec/cpu_ldst.h"
 #include "exec/log.h"
+#include "hw/mips/cpudevs.h"
 
 enum {
     TLBRET_XI = -6,
@@ -225,7 +225,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 #define KVM_KSEG0_BASE  ((target_ulong)(int32_t)0x40000000UL)
 #define KVM_KSEG2_BASE  ((target_ulong)(int32_t)0x60000000UL)
 
-    if (kvm_enabled()) {
+    if (mips_um_ksegs_enabled()) {
         /* KVM T&E adds guest kernel segments in useg */
         if (real_address >= KVM_KSEG0_BASE) {
             if (real_address < KVM_KSEG2_BASE) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 51626aead32c..4635012d6436 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -27,10 +27,10 @@
 #include "exec/exec-all.h"
 #include "tcg-op.h"
 #include "exec/cpu_ldst.h"
+#include "hw/mips/cpudevs.h"
 
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
-#include "sysemu/kvm.h"
 #include "exec/semihost.h"
 
 #include "target/mips/trace.h"
@@ -20639,7 +20639,7 @@ void cpu_state_reset(CPUMIPSState *env)
     env->CP0_Wired = 0;
     env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
     env->CP0_EBase = (cs->cpu_index & 0x3FF);
-    if (kvm_enabled()) {
+    if (mips_um_ksegs_enabled()) {
         env->CP0_EBase |= 0x40000000;
     } else {
         env->CP0_EBase |= (int32_t)0x80000000;
-- 
git-series 0.8.10

Re: [Qemu-devel] [PATCH 1/2] mips: Improve segment defs for KVM T&E guests

[Philippe Mathieu-Daudé]

On 07/31/2017 10:09 AM, James Hogan wrote:
> Improve the segment definitions used by get_physical_address() to yield
> target_ulong types, e.g. 0xffffffff80000000 instead of 0x80000000. This
> is in preparation for enabling emulation of MIPS KVM T&E segments in TCG
> MIPS targets, which unlike KVM could potentially have 64-bit
> target_ulong. In such a case the offset guest KSEG0 address ends up at
> e.g. 0x000000008xxxxxxx instead of 0xffffffff8xxxxxxx.
> 
> This also allows the casts to int32_t that force sign extension to be
> removed, which removes any confusion due to relational comparison of
> unsigned (target_ulong) and signed (int32_t) types.
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> Cc: Yongbok Kim <yongbok.kim@imgtec.com>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> Cc: Paolo Bonzini <pbonzini@redhat.com>
> Cc: kvm@vger.kernel.org
> ---
>   target/mips/helper.c | 23 +++++++++++------------
>   1 file changed, 11 insertions(+), 12 deletions(-)
> 
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index a2b79e8725a6..05883b9f4251 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -216,14 +216,14 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
>       /* effective address (modified for KVM T&E kernel segments) */
>       target_ulong address = real_address;
>   
> -#define USEG_LIMIT      0x7FFFFFFFUL
> -#define KSEG0_BASE      0x80000000UL
> -#define KSEG1_BASE      0xA0000000UL
> -#define KSEG2_BASE      0xC0000000UL
> -#define KSEG3_BASE      0xE0000000UL
> +#define USEG_LIMIT      ((target_ulong)(int32_t)0x7FFFFFFFUL)
> +#define KSEG0_BASE      ((target_ulong)(int32_t)0x80000000UL)
> +#define KSEG1_BASE      ((target_ulong)(int32_t)0xA0000000UL)
> +#define KSEG2_BASE      ((target_ulong)(int32_t)0xC0000000UL)
> +#define KSEG3_BASE      ((target_ulong)(int32_t)0xE0000000UL)
>   
> -#define KVM_KSEG0_BASE  0x40000000UL
> -#define KVM_KSEG2_BASE  0x60000000UL
> +#define KVM_KSEG0_BASE  ((target_ulong)(int32_t)0x40000000UL)
> +#define KVM_KSEG2_BASE  ((target_ulong)(int32_t)0x60000000UL)
>   
>       if (kvm_enabled()) {
>           /* KVM T&E adds guest kernel segments in useg */
> @@ -307,17 +307,17 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
>               ret = TLBRET_BADADDR;
>           }
>   #endif
> -    } else if (address < (int32_t)KSEG1_BASE) {
> +    } else if (address < KSEG1_BASE) {
>           /* kseg0 */
>           ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
>                                             access_type, mmu_idx,
>                                             env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
> -    } else if (address < (int32_t)KSEG2_BASE) {
> +    } else if (address < KSEG2_BASE) {
>           /* kseg1 */
>           ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
>                                             access_type, mmu_idx,
>                                             env->CP0_SegCtl1, 0x1FFFFFFF);
> -    } else if (address < (int32_t)KSEG3_BASE) {
> +    } else if (address < KSEG3_BASE) {
>           /* sseg (kseg2) */
>           ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
>                                             access_type, mmu_idx,
> @@ -974,8 +974,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
>           } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) &&
>                                       env->CP0_Config5 & (1 << CP0C5_CV))) {
>               /* Force KSeg1 for cache errors */
> -            env->active_tc.PC = (int32_t)KSEG1_BASE |
> -                                (env->CP0_EBase & 0x1FFFF000);
> +            env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000);
>           } else {
>               env->active_tc.PC = env->CP0_EBase & ~0xfff;
>           }
> 

Re: [Qemu-devel] [PATCH 2/2] mips: Add KVM T&E segment support for TCG

[Richard Henderson]

On 07/31/2017 06:09 AM, James Hogan wrote:
> +static int mips_um_ksegs;
> +
>   uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr)
>   {
>       return addr & 0x1fffffffll;
> @@ -38,3 +40,13 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr)
>   {
>       return addr | 0x40000000ll;
>   }
> +
> +int mips_um_ksegs_enabled(void)

bool?

Otherwise,
Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

Re: [Qemu-devel] [PATCH 2/2] mips: Add KVM T&E segment support for TCG

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 613 bytes --]

On Mon, Jul 31, 2017 at 01:47:48PM -0700, Richard Henderson wrote:
> On 07/31/2017 06:09 AM, James Hogan wrote:
> > +static int mips_um_ksegs;
> > +
> >   uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr)
> >   {
> >       return addr & 0x1fffffffll;
> > @@ -38,3 +40,13 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr)
> >   {
> >       return addr | 0x40000000ll;
> >   }
> > +
> > +int mips_um_ksegs_enabled(void)
> 
> bool?

Sure, I'll respin,

> 
> Otherwise,
> Reviewed-by: Richard Henderson <rth@twiddle.net>

Thanks for the review!

Cheers
James

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