* [PATCH 1/7] target/mips/translate: Extract DisasContext structure
2020-12-07 23:55 [PATCH 0/7] target/mips: Add translate.h and fpu_translate.h headers Philippe Mathieu-Daudé
@ 2020-12-07 23:55 ` Philippe Mathieu-Daudé
2020-12-08 22:53 ` Richard Henderson
2020-12-07 23:55 ` [PATCH 2/7] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-07 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Laurent Vivier, Richard Henderson, Huacai Chen, kvm
Extract DisasContext to a new 'translate.h' header so
different translation files (ISA, ASE, extensions)
can use it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 50 +++++++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 38 +------------------------------
2 files changed, 51 insertions(+), 37 deletions(-)
create mode 100644 target/mips/translate.h
diff --git a/target/mips/translate.h b/target/mips/translate.h
new file mode 100644
index 00000000000..fcda1a99001
--- /dev/null
+++ b/target/mips/translate.h
@@ -0,0 +1,50 @@
+/*
+ * MIPS translation routines.
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef TARGET_MIPS_TRANSLATE_H
+#define TARGET_MIPS_TRANSLATE_H
+
+#include "exec/translator.h"
+
+typedef struct DisasContext {
+ DisasContextBase base;
+ target_ulong saved_pc;
+ target_ulong page_start;
+ uint32_t opcode;
+ uint64_t insn_flags;
+ int32_t CP0_Config1;
+ int32_t CP0_Config2;
+ int32_t CP0_Config3;
+ int32_t CP0_Config5;
+ /* Routine used to access memory */
+ int mem_idx;
+ MemOp default_tcg_memop_mask;
+ uint32_t hflags, saved_hflags;
+ target_ulong btarget;
+ bool ulri;
+ int kscrexist;
+ bool rxi;
+ int ie;
+ bool bi;
+ bool bp;
+ uint64_t PAMask;
+ bool mvh;
+ bool eva;
+ bool sc;
+ int CP0_LLAddr_shift;
+ bool ps;
+ bool vp;
+ bool cmgcr;
+ bool mrp;
+ bool nan2008;
+ bool abs2008;
+ bool saar;
+ bool mi;
+ int gi;
+} DisasContext;
+
+#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ee45dce9a50..d7f5a1e8d84 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -39,6 +39,7 @@
#include "exec/translator.h"
#include "exec/log.h"
#include "qemu/qemu-print.h"
+#include "translate.h"
#define MIPS_DEBUG_DISAS 0
@@ -2557,43 +2558,6 @@ static TCGv mxu_CR;
tcg_temp_free_i32(helper_tmp); \
} while (0)
-typedef struct DisasContext {
- DisasContextBase base;
- target_ulong saved_pc;
- target_ulong page_start;
- uint32_t opcode;
- uint64_t insn_flags;
- int32_t CP0_Config1;
- int32_t CP0_Config2;
- int32_t CP0_Config3;
- int32_t CP0_Config5;
- /* Routine used to access memory */
- int mem_idx;
- MemOp default_tcg_memop_mask;
- uint32_t hflags, saved_hflags;
- target_ulong btarget;
- bool ulri;
- int kscrexist;
- bool rxi;
- int ie;
- bool bi;
- bool bp;
- uint64_t PAMask;
- bool mvh;
- bool eva;
- bool sc;
- int CP0_LLAddr_shift;
- bool ps;
- bool vp;
- bool cmgcr;
- bool mrp;
- bool nan2008;
- bool abs2008;
- bool saar;
- bool mi;
- int gi;
-} DisasContext;
-
#define DISAS_STOP DISAS_TARGET_0
#define DISAS_EXIT DISAS_TARGET_1
--
2.26.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/7] target/mips/translate: Extract DisasContext structure
2020-12-07 23:55 ` [PATCH 1/7] target/mips/translate: Extract DisasContext structure Philippe Mathieu-Daudé
@ 2020-12-08 22:53 ` Richard Henderson
0 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2020-12-08 22:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Laurent Vivier, Huacai Chen, kvm
On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
> Extract DisasContext to a new 'translate.h' header so
> different translation files (ISA, ASE, extensions)
> can use it.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.h | 50 +++++++++++++++++++++++++++++++++++++++++
> target/mips/translate.c | 38 +------------------------------
> 2 files changed, 51 insertions(+), 37 deletions(-)
> create mode 100644 target/mips/translate.h
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/7] target/mips/translate: Add declarations for generic code
2020-12-07 23:55 [PATCH 0/7] target/mips: Add translate.h and fpu_translate.h headers Philippe Mathieu-Daudé
2020-12-07 23:55 ` [PATCH 1/7] target/mips/translate: Extract DisasContext structure Philippe Mathieu-Daudé
@ 2020-12-07 23:55 ` Philippe Mathieu-Daudé
2020-12-08 22:53 ` Richard Henderson
2020-12-07 23:55 ` [PATCH 3/7] target/mips: Use FloatRoundMode enum for FCR31 modes conversion Philippe Mathieu-Daudé
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-07 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Laurent Vivier, Richard Henderson, Huacai Chen, kvm
Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 33 ++++++++++++++++++++++++++++++++
target/mips/translate.c | 42 ++++++++++++-----------------------------
2 files changed, 45 insertions(+), 30 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index fcda1a99001..dbf7df7ba6d 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -10,6 +10,8 @@
#include "exec/translator.h"
+#define MIPS_DEBUG_DISAS 0
+
typedef struct DisasContext {
DisasContextBase base;
target_ulong saved_pc;
@@ -47,4 +49,35 @@ typedef struct DisasContext {
int gi;
} DisasContext;
+/* MIPS major opcodes */
+#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
+
+void generate_exception_end(DisasContext *ctx, int excp);
+void gen_reserved_instruction(DisasContext *ctx);
+void check_insn(DisasContext *ctx, uint64_t flags);
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
+
+void gen_load_gpr(TCGv t, int reg);
+void gen_store_gpr(TCGv t, int reg);
+
+extern TCGv bcond;
+
+#define LOG_DISAS(...) \
+ do { \
+ if (MIPS_DEBUG_DISAS) { \
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
+ } \
+ } while (0)
+
+#define MIPS_INVAL(op) \
+ do { \
+ if (MIPS_DEBUG_DISAS) { \
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, \
+ TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
+ ctx->base.pc_next, ctx->opcode, op, \
+ ctx->opcode >> 26, ctx->opcode & 0x3F, \
+ ((ctx->opcode >> 16) & 0x1F)); \
+ } \
+ } while (0)
+
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d7f5a1e8d84..46aab26b868 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -41,11 +41,6 @@
#include "qemu/qemu-print.h"
#include "translate.h"
-#define MIPS_DEBUG_DISAS 0
-
-/* MIPS major opcodes */
-#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
-
enum {
/* indirect opcode tables */
OPC_SPECIAL = (0x00 << 26),
@@ -2496,7 +2491,8 @@ enum {
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
-static TCGv cpu_dspctrl, btarget, bcond;
+static TCGv cpu_dspctrl, btarget;
+TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
static TCGv_i32 fpu_fcr0, fpu_fcr31;
@@ -2609,26 +2605,8 @@ static const char * const mxuregnames[] = {
};
#endif
-#define LOG_DISAS(...) \
- do { \
- if (MIPS_DEBUG_DISAS) { \
- qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
- } \
- } while (0)
-
-#define MIPS_INVAL(op) \
- do { \
- if (MIPS_DEBUG_DISAS) { \
- qemu_log_mask(CPU_LOG_TB_IN_ASM, \
- TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
- ctx->base.pc_next, ctx->opcode, op, \
- ctx->opcode >> 26, ctx->opcode & 0x3F, \
- ((ctx->opcode >> 16) & 0x1F)); \
- } \
- } while (0)
-
/* General purpose registers moves. */
-static inline void gen_load_gpr(TCGv t, int reg)
+void gen_load_gpr(TCGv t, int reg)
{
if (reg == 0) {
tcg_gen_movi_tl(t, 0);
@@ -2637,7 +2615,7 @@ static inline void gen_load_gpr(TCGv t, int reg)
}
}
-static inline void gen_store_gpr(TCGv t, int reg)
+void gen_store_gpr(TCGv t, int reg)
{
if (reg != 0) {
tcg_gen_mov_tl(cpu_gpr[reg], t);
@@ -2782,11 +2760,16 @@ static inline void generate_exception(DisasContext *ctx, int excp)
gen_helper_0e0i(raise_exception, excp);
}
-static inline void generate_exception_end(DisasContext *ctx, int excp)
+void generate_exception_end(DisasContext *ctx, int excp)
{
generate_exception_err(ctx, excp, 0);
}
+void gen_reserved_instruction(DisasContext *ctx)
+{
+ generate_exception_end(ctx, EXCP_RI);
+}
+
/* Floating point register moves. */
static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
{
@@ -3016,7 +2999,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
* This code generates a "reserved instruction" exception if the
* CPU does not support the instruction set corresponding to flags.
*/
-static inline void check_insn(DisasContext *ctx, uint64_t flags)
+void check_insn(DisasContext *ctx, uint64_t flags)
{
if (unlikely(!(ctx->insn_flags & flags))) {
generate_exception_end(ctx, EXCP_RI);
@@ -3393,8 +3376,7 @@ OP_LD_ATOMIC(lld, ld64);
#endif
#undef OP_LD_ATOMIC
-static void gen_base_offset_addr(DisasContext *ctx, TCGv addr,
- int base, int offset)
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
{
if (base == 0) {
tcg_gen_movi_tl(addr, offset);
--
2.26.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 2/7] target/mips/translate: Add declarations for generic code
2020-12-07 23:55 ` [PATCH 2/7] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
@ 2020-12-08 22:53 ` Richard Henderson
0 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2020-12-08 22:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Laurent Vivier, Huacai Chen, kvm
On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
> Some CPU translation functions / registers / macros and
> definitions can be used by ISA / ASE / extensions out of
> the big translate.c file. Declare them in "translate.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.h | 33 ++++++++++++++++++++++++++++++++
> target/mips/translate.c | 42 ++++++++++++-----------------------------
> 2 files changed, 45 insertions(+), 30 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/7] target/mips: Use FloatRoundMode enum for FCR31 modes conversion
2020-12-07 23:55 [PATCH 0/7] target/mips: Add translate.h and fpu_translate.h headers Philippe Mathieu-Daudé
2020-12-07 23:55 ` [PATCH 1/7] target/mips/translate: Extract DisasContext structure Philippe Mathieu-Daudé
2020-12-07 23:55 ` [PATCH 2/7] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
@ 2020-12-07 23:55 ` Philippe Mathieu-Daudé
2020-12-07 23:55 ` [PATCH 4/7] target/mips: Extract FPU helpers to 'fpu_helper.h' Philippe Mathieu-Daudé
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-07 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Laurent Vivier, Richard Henderson, Huacai Chen, kvm
Use the FloatRoundMode enum type introduced in commit 3dede407cc6
("softfloat: Name rounding mode enum") instead of 'unsigned int'.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201123204448.3260804-2-f4bug@amsat.org>
---
target/mips/internal.h | 3 ++-
target/mips/fpu_helper.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index d290c1afe30..5d8a8a1838e 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -226,7 +226,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
uint32_t float_class_s(uint32_t arg, float_status *fst);
uint64_t float_class_d(uint64_t arg, float_status *fst);
-extern unsigned int ieee_rm[];
+extern const FloatRoundMode ieee_rm[4];
+
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
static inline void restore_rounding_mode(CPUMIPSState *env)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 020b768e87b..501bd401a16 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -42,7 +42,7 @@
#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
/* convert MIPS rounding mode in FCR31 to IEEE library */
-unsigned int ieee_rm[] = {
+const FloatRoundMode ieee_rm[4] = {
float_round_nearest_even,
float_round_to_zero,
float_round_up,
--
2.26.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/7] target/mips: Extract FPU helpers to 'fpu_helper.h'
2020-12-07 23:55 [PATCH 0/7] target/mips: Add translate.h and fpu_translate.h headers Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2020-12-07 23:55 ` [PATCH 3/7] target/mips: Use FloatRoundMode enum for FCR31 modes conversion Philippe Mathieu-Daudé
@ 2020-12-07 23:55 ` Philippe Mathieu-Daudé
2020-12-07 23:55 ` [PATCH 5/7] target/mips/fpu_helper: Remove unused headers Philippe Mathieu-Daudé
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-07 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Laurent Vivier, Richard Henderson, Huacai Chen, kvm
Extract FPU specific helpers from "internal.h" to "fpu_helper.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
---
target/mips/fpu_helper.h | 59 ++++++++++++++++++++++++++++++++++++++
target/mips/internal.h | 50 --------------------------------
linux-user/mips/cpu_loop.c | 1 +
target/mips/fpu_helper.c | 1 +
target/mips/gdbstub.c | 1 +
target/mips/kvm.c | 1 +
target/mips/machine.c | 1 +
target/mips/msa_helper.c | 1 +
target/mips/op_helper.c | 1 +
target/mips/translate.c | 1 +
10 files changed, 67 insertions(+), 50 deletions(-)
create mode 100644 target/mips/fpu_helper.h
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
new file mode 100644
index 00000000000..1c2d6d35a71
--- /dev/null
+++ b/target/mips/fpu_helper.h
@@ -0,0 +1,59 @@
+/*
+ * Helpers for emulation of FPU-related MIPS instructions.
+ *
+ * Copyright (C) 2004-2005 Jocelyn Mayer
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "fpu/softfloat-helpers.h"
+#include "cpu.h"
+
+extern const FloatRoundMode ieee_rm[4];
+
+uint32_t float_class_s(uint32_t arg, float_status *fst);
+uint64_t float_class_d(uint64_t arg, float_status *fst);
+
+static inline void restore_rounding_mode(CPUMIPSState *env)
+{
+ set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
+ &env->active_fpu.fp_status);
+}
+
+static inline void restore_flush_mode(CPUMIPSState *env)
+{
+ set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
+ &env->active_fpu.fp_status);
+}
+
+static inline void restore_snan_bit_mode(CPUMIPSState *env)
+{
+ set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
+ &env->active_fpu.fp_status);
+}
+
+static inline void restore_fp_status(CPUMIPSState *env)
+{
+ restore_rounding_mode(env);
+ restore_flush_mode(env);
+ restore_snan_bit_mode(env);
+}
+
+/* MSA */
+
+enum CPUMIPSMSADataFormat {
+ DF_BYTE = 0,
+ DF_HALF,
+ DF_WORD,
+ DF_DOUBLE
+};
+
+static inline void restore_msa_fp_status(CPUMIPSState *env)
+{
+ float_status *status = &env->active_tc.msa_fp_status;
+ int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
+ bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
+
+ set_float_rounding_mode(ieee_rm[rounding_mode], status);
+ set_flush_to_zero(flush_to_zero, status);
+ set_flush_inputs_to_zero(flush_to_zero, status);
+}
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 5d8a8a1838e..6b9d1d4b93b 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -8,8 +8,6 @@
#ifndef MIPS_INTERNAL_H
#define MIPS_INTERNAL_H
-#include "fpu/softfloat-helpers.h"
-
/*
* MMU types, the first four entries have the same layout as the
* CP0C0_MT field.
@@ -74,13 +72,6 @@ struct mips_def_t {
extern const struct mips_def_t mips_defs[];
extern const int mips_defs_number;
-enum CPUMIPSMSADataFormat {
- DF_BYTE = 0,
- DF_HALF,
- DF_WORD,
- DF_DOUBLE
-};
-
void mips_cpu_do_interrupt(CPUState *cpu);
bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
@@ -223,49 +214,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
bool probe, uintptr_t retaddr);
/* op_helper.c */
-uint32_t float_class_s(uint32_t arg, float_status *fst);
-uint64_t float_class_d(uint64_t arg, float_status *fst);
-
-extern const FloatRoundMode ieee_rm[4];
-
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
-static inline void restore_rounding_mode(CPUMIPSState *env)
-{
- set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
- &env->active_fpu.fp_status);
-}
-
-static inline void restore_flush_mode(CPUMIPSState *env)
-{
- set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
- &env->active_fpu.fp_status);
-}
-
-static inline void restore_snan_bit_mode(CPUMIPSState *env)
-{
- set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
- &env->active_fpu.fp_status);
-}
-
-static inline void restore_fp_status(CPUMIPSState *env)
-{
- restore_rounding_mode(env);
- restore_flush_mode(env);
- restore_snan_bit_mode(env);
-}
-
-static inline void restore_msa_fp_status(CPUMIPSState *env)
-{
- float_status *status = &env->active_tc.msa_fp_status;
- int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
- bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
-
- set_float_rounding_mode(ieee_rm[rounding_mode], status);
- set_flush_to_zero(flush_to_zero, status);
- set_flush_inputs_to_zero(flush_to_zero, status);
-}
-
static inline void restore_pamask(CPUMIPSState *env)
{
if (env->hflags & MIPS_HFLAG_ELPA) {
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index cfe7ba5c47d..b58dbeb83d1 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -23,6 +23,7 @@
#include "cpu_loop-common.h"
#include "elf.h"
#include "internal.h"
+#include "fpu_helper.h"
# ifdef TARGET_ABI_MIPSO32
# define MIPS_SYSCALL_NUMBER_UNUSED -1
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 501bd401a16..7d949cd8e3a 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -31,6 +31,7 @@
#include "exec/memop.h"
#include "sysemu/kvm.h"
#include "fpu/softfloat.h"
+#include "fpu_helper.h"
/* Complex FPU operations which may need stack space. */
diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index e39f8d75cf0..f1c2a2cf6d6 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "internal.h"
#include "exec/gdbstub.h"
+#include "fpu_helper.h"
int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index cbd0cb8faa4..3ca3a0da93f 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -27,6 +27,7 @@
#include "kvm_mips.h"
#include "exec/memattrs.h"
#include "hw/boards.h"
+#include "fpu_helper.h"
#define DEBUG_KVM 0
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 5b23e3e912a..a4ea67c2980 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -2,6 +2,7 @@
#include "cpu.h"
#include "internal.h"
#include "migration/cpu.h"
+#include "fpu_helper.h"
static int cpu_post_load(void *opaque, int version_id)
{
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 249f0fdad80..b89b4c44902 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -23,6 +23,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
+#include "fpu_helper.h"
/* Data format min and max values */
#define DF_BITS(df) (1 << ((df) + 3))
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 5184a1838be..72613706188 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -28,6 +28,7 @@
#include "exec/cpu_ldst.h"
#include "exec/memop.h"
#include "sysemu/kvm.h"
+#include "fpu_helper.h"
/*****************************************************************************/
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 46aab26b868..6614512a828 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -39,6 +39,7 @@
#include "exec/translator.h"
#include "exec/log.h"
#include "qemu/qemu-print.h"
+#include "fpu_helper.h"
#include "translate.h"
enum {
--
2.26.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/7] target/mips/fpu_helper: Remove unused headers
2020-12-07 23:55 [PATCH 0/7] target/mips: Add translate.h and fpu_translate.h headers Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2020-12-07 23:55 ` [PATCH 4/7] target/mips: Extract FPU helpers to 'fpu_helper.h' Philippe Mathieu-Daudé
@ 2020-12-07 23:55 ` Philippe Mathieu-Daudé
2020-12-08 22:53 ` Richard Henderson
2020-12-07 23:55 ` [PATCH 6/7] target/mips: Declare generic FPU functions in 'fpu_translate.h' Philippe Mathieu-Daudé
2020-12-07 23:55 ` [PATCH 7/7] target/mips: Extract FPU specific definitions to fpu_translate.h Philippe Mathieu-Daudé
6 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-07 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Laurent Vivier, Richard Henderson, Huacai Chen, kvm
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/fpu_helper.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 7d949cd8e3a..a3c05160b35 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -21,15 +21,11 @@
*/
#include "qemu/osdep.h"
-#include "qemu/main-loop.h"
#include "cpu.h"
#include "internal.h"
-#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
-#include "exec/memop.h"
-#include "sysemu/kvm.h"
#include "fpu/softfloat.h"
#include "fpu_helper.h"
--
2.26.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 5/7] target/mips/fpu_helper: Remove unused headers
2020-12-07 23:55 ` [PATCH 5/7] target/mips/fpu_helper: Remove unused headers Philippe Mathieu-Daudé
@ 2020-12-08 22:53 ` Richard Henderson
0 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2020-12-08 22:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Laurent Vivier, Huacai Chen, kvm
On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/fpu_helper.c | 4 ----
> 1 file changed, 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/7] target/mips: Declare generic FPU functions in 'fpu_translate.h'
2020-12-07 23:55 [PATCH 0/7] target/mips: Add translate.h and fpu_translate.h headers Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2020-12-07 23:55 ` [PATCH 5/7] target/mips/fpu_helper: Remove unused headers Philippe Mathieu-Daudé
@ 2020-12-07 23:55 ` Philippe Mathieu-Daudé
2020-12-08 22:54 ` Richard Henderson
2020-12-07 23:55 ` [PATCH 7/7] target/mips: Extract FPU specific definitions to fpu_translate.h Philippe Mathieu-Daudé
6 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-07 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Laurent Vivier, Richard Henderson, Huacai Chen, kvm
Some FPU translation functions / registers can be used by
ISA / ASE / extensions out of the big translate.c file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/fpu_translate.h | 25 +++++++++++++++++++++++++
target/mips/translate.c | 14 ++++++++------
2 files changed, 33 insertions(+), 6 deletions(-)
create mode 100644 target/mips/fpu_translate.h
diff --git a/target/mips/fpu_translate.h b/target/mips/fpu_translate.h
new file mode 100644
index 00000000000..430e0b77537
--- /dev/null
+++ b/target/mips/fpu_translate.h
@@ -0,0 +1,25 @@
+/*
+ * FPU-related MIPS translation routines.
+ *
+ * Copyright (C) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef TARGET_MIPS_FPU_TRANSLATE_H
+#define TARGET_MIPS_FPU_TRANSLATE_H
+
+#include "exec/translator.h"
+#include "translate.h"
+
+extern TCGv_i32 fpu_fcr0, fpu_fcr31;
+extern TCGv_i64 fpu_f64[32];
+
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+
+int get_fp_bit(int cc);
+
+void check_cp1_enabled(DisasContext *ctx);
+
+#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6614512a828..bc54eb58c70 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -40,7 +40,9 @@
#include "exec/log.h"
#include "qemu/qemu-print.h"
#include "fpu_helper.h"
+
#include "translate.h"
+#include "fpu_translate.h"
enum {
/* indirect opcode tables */
@@ -2496,8 +2498,8 @@ static TCGv cpu_dspctrl, btarget;
TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
-static TCGv_i32 fpu_fcr0, fpu_fcr31;
-static TCGv_i64 fpu_f64[32];
+TCGv_i32 fpu_fcr0, fpu_fcr31;
+TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
#if defined(TARGET_MIPS64)
@@ -2813,7 +2815,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
}
}
-static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
tcg_gen_mov_i64(t, fpu_f64[reg]);
@@ -2822,7 +2824,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
}
}
-static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
tcg_gen_mov_i64(fpu_f64[reg], t);
@@ -2836,7 +2838,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
}
}
-static inline int get_fp_bit(int cc)
+int get_fp_bit(int cc)
{
if (cc) {
return 24 + cc;
@@ -2911,7 +2913,7 @@ static inline void check_cp0_enabled(DisasContext *ctx)
}
}
-static inline void check_cp1_enabled(DisasContext *ctx)
+void check_cp1_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
generate_exception_err(ctx, EXCP_CpU, 1);
--
2.26.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 6/7] target/mips: Declare generic FPU functions in 'fpu_translate.h'
2020-12-07 23:55 ` [PATCH 6/7] target/mips: Declare generic FPU functions in 'fpu_translate.h' Philippe Mathieu-Daudé
@ 2020-12-08 22:54 ` Richard Henderson
2020-12-14 14:41 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 13+ messages in thread
From: Richard Henderson @ 2020-12-08 22:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Laurent Vivier, Huacai Chen, kvm
On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
> Some FPU translation functions / registers can be used by
> ISA / ASE / extensions out of the big translate.c file.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/fpu_translate.h | 25 +++++++++++++++++++++++++
> target/mips/translate.c | 14 ++++++++------
> 2 files changed, 33 insertions(+), 6 deletions(-)
> create mode 100644 target/mips/fpu_translate.h
Is there a good reason for not putting these in translate.h?
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 6/7] target/mips: Declare generic FPU functions in 'fpu_translate.h'
2020-12-08 22:54 ` Richard Henderson
@ 2020-12-14 14:41 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-14 14:41 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Aleksandar Rikalo, kvm, Huacai Chen, Laurent Vivier,
Paolo Bonzini, Aurelien Jarno
On 12/8/20 11:54 PM, Richard Henderson wrote:
> On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
>> Some FPU translation functions / registers can be used by
>> ISA / ASE / extensions out of the big translate.c file.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> target/mips/fpu_translate.h | 25 +++++++++++++++++++++++++
>> target/mips/translate.c | 14 ++++++++------
>> 2 files changed, 33 insertions(+), 6 deletions(-)
>> create mode 100644 target/mips/fpu_translate.h
>
> Is there a good reason for not putting these in translate.h?
None :)
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 7/7] target/mips: Extract FPU specific definitions to fpu_translate.h
2020-12-07 23:55 [PATCH 0/7] target/mips: Add translate.h and fpu_translate.h headers Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2020-12-07 23:55 ` [PATCH 6/7] target/mips: Declare generic FPU functions in 'fpu_translate.h' Philippe Mathieu-Daudé
@ 2020-12-07 23:55 ` Philippe Mathieu-Daudé
6 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-07 23:55 UTC (permalink / raw)
To: qemu-devel
Cc: Jiaxun Yang, Paolo Bonzini, Aurelien Jarno, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Laurent Vivier, Richard Henderson, Huacai Chen, kvm
Extract FPU specific definitions that can be used by
ISA / ASE / extensions to fpu_translate.h header.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/fpu_translate.h | 71 +++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 70 ------------------------------------
2 files changed, 71 insertions(+), 70 deletions(-)
diff --git a/target/mips/fpu_translate.h b/target/mips/fpu_translate.h
index 430e0b77537..f45314d2ec2 100644
--- a/target/mips/fpu_translate.h
+++ b/target/mips/fpu_translate.h
@@ -12,6 +12,77 @@
#include "exec/translator.h"
#include "translate.h"
+#define OPC_CP1 (0x11 << 26)
+
+/* Coprocessor 1 (rs field) */
+#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
+
+/* Values for the fmt field in FP instructions */
+enum {
+ /* 0 - 15 are reserved */
+ FMT_S = 16, /* single fp */
+ FMT_D = 17, /* double fp */
+ FMT_E = 18, /* extended fp */
+ FMT_Q = 19, /* quad fp */
+ FMT_W = 20, /* 32-bit fixed */
+ FMT_L = 21, /* 64-bit fixed */
+ FMT_PS = 22, /* paired single fp */
+ /* 23 - 31 are reserved */
+};
+
+enum {
+ OPC_MFC1 = (0x00 << 21) | OPC_CP1,
+ OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
+ OPC_CFC1 = (0x02 << 21) | OPC_CP1,
+ OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
+ OPC_MTC1 = (0x04 << 21) | OPC_CP1,
+ OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
+ OPC_CTC1 = (0x06 << 21) | OPC_CP1,
+ OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
+ OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
+ OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
+ OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
+ OPC_BZ_V = (0x0B << 21) | OPC_CP1,
+ OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
+ OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
+ OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
+ OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
+ OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1,
+ OPC_W_FMT = (FMT_W << 21) | OPC_CP1,
+ OPC_L_FMT = (FMT_L << 21) | OPC_CP1,
+ OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
+ OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
+ OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
+ OPC_BZ_B = (0x18 << 21) | OPC_CP1,
+ OPC_BZ_H = (0x19 << 21) | OPC_CP1,
+ OPC_BZ_W = (0x1A << 21) | OPC_CP1,
+ OPC_BZ_D = (0x1B << 21) | OPC_CP1,
+ OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
+ OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
+ OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
+ OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
+};
+
+#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
+#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16)))
+
+enum {
+ OPC_BC1F = (0x00 << 16) | OPC_BC1,
+ OPC_BC1T = (0x01 << 16) | OPC_BC1,
+ OPC_BC1FL = (0x02 << 16) | OPC_BC1,
+ OPC_BC1TL = (0x03 << 16) | OPC_BC1,
+};
+
+enum {
+ OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
+ OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
+};
+
+enum {
+ OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
+ OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
+};
+
extern TCGv_i32 fpu_fcr0, fpu_fcr31;
extern TCGv_i64 fpu_f64[32];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bc54eb58c70..80c9c17819f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -49,7 +49,6 @@ enum {
OPC_SPECIAL = (0x00 << 26),
OPC_REGIMM = (0x01 << 26),
OPC_CP0 = (0x10 << 26),
- OPC_CP1 = (0x11 << 26),
OPC_CP2 = (0x12 << 26),
OPC_CP3 = (0x13 << 26),
OPC_SPECIAL2 = (0x1C << 26),
@@ -1002,75 +1001,6 @@ enum {
OPC_WAIT = 0x20 | OPC_C0,
};
-/* Coprocessor 1 (rs field) */
-#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
-
-/* Values for the fmt field in FP instructions */
-enum {
- /* 0 - 15 are reserved */
- FMT_S = 16, /* single fp */
- FMT_D = 17, /* double fp */
- FMT_E = 18, /* extended fp */
- FMT_Q = 19, /* quad fp */
- FMT_W = 20, /* 32-bit fixed */
- FMT_L = 21, /* 64-bit fixed */
- FMT_PS = 22, /* paired single fp */
- /* 23 - 31 are reserved */
-};
-
-enum {
- OPC_MFC1 = (0x00 << 21) | OPC_CP1,
- OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
- OPC_CFC1 = (0x02 << 21) | OPC_CP1,
- OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
- OPC_MTC1 = (0x04 << 21) | OPC_CP1,
- OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
- OPC_CTC1 = (0x06 << 21) | OPC_CP1,
- OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
- OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
- OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
- OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
- OPC_BZ_V = (0x0B << 21) | OPC_CP1,
- OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
- OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
- OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
- OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
- OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1,
- OPC_W_FMT = (FMT_W << 21) | OPC_CP1,
- OPC_L_FMT = (FMT_L << 21) | OPC_CP1,
- OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
- OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
- OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
- OPC_BZ_B = (0x18 << 21) | OPC_CP1,
- OPC_BZ_H = (0x19 << 21) | OPC_CP1,
- OPC_BZ_W = (0x1A << 21) | OPC_CP1,
- OPC_BZ_D = (0x1B << 21) | OPC_CP1,
- OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
- OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
- OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
- OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
-};
-
-#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
-#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16)))
-
-enum {
- OPC_BC1F = (0x00 << 16) | OPC_BC1,
- OPC_BC1T = (0x01 << 16) | OPC_BC1,
- OPC_BC1FL = (0x02 << 16) | OPC_BC1,
- OPC_BC1TL = (0x03 << 16) | OPC_BC1,
-};
-
-enum {
- OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
- OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
-};
-
-enum {
- OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
- OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
-};
-
#define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
enum {
--
2.26.2
^ permalink raw reply related [flat|nested] 13+ messages in thread