* [PATCH 00/17] target/mips: Convert MSA ASE to decodetree
@ 2020-12-08 0:36 Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 01/17] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé
` (17 more replies)
0 siblings, 18 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
Finally, we use decodetree with the MIPS target.
Starting easy with the MSA ASE. 2700+ lines extracted
from helper.h and translate.c, now built as an new
object: mod-msa_translate.o.
While the diff stat is positive by 86 lines, we actually
(re)moved code, but added (C) notices.
The most interesting patches are the 2 last ones.
Please review,
Phil.
Based-on: <20201207224335.4030582-1-f4bug@amsat.org>
(linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3A)
Based-on: <20201207235539.4070364-1-f4bug@amsat.org>
(target/mips: Add translate.h and fpu_translate.h headers)
Philippe Mathieu-Daudé (17):
target/mips: Introduce ase_msa_available() helper
target/mips: Simplify msa_reset()
target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
target/mips: Simplify MSA TCG logic
target/mips: Remove now unused ASE_MSA definition
target/mips: Alias MSA vector registers on FPU scalar registers
target/mips: Extract msa_translate_init() from mips_tcg_init()
target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
target/mips: Rename msa_helper.c as mod-msa_helper.c
target/mips: Move msa_reset() to mod-msa_helper.c
target/mips: Extract MSA helpers from op_helper.c
target/mips: Extract MSA helper definitions
target/mips: Declare gen_msa/_branch() in 'translate.h'
target/mips: Extract MSA translation routines
target/mips: Introduce decode tree bindings for MSA opcodes
target/mips: Use decode_msa32() generated from decodetree
target/mips/cpu.h | 6 +
target/mips/fpu_translate.h | 10 -
target/mips/helper.h | 436 +---
target/mips/internal.h | 4 +-
target/mips/mips-defs.h | 1 -
target/mips/translate.h | 4 +
target/mips/mod-msa32.decode | 24 +
target/mips/kvm.c | 12 +-
.../mips/{msa_helper.c => mod-msa_helper.c} | 429 ++++
target/mips/mod-msa_translate.c | 2270 +++++++++++++++++
target/mips/op_helper.c | 394 ---
target/mips/translate.c | 2264 +---------------
target/mips/meson.build | 9 +-
target/mips/mod-msa_helper.h.inc | 443 ++++
target/mips/translate_init.c.inc | 38 +-
15 files changed, 3215 insertions(+), 3129 deletions(-)
create mode 100644 target/mips/mod-msa32.decode
rename target/mips/{msa_helper.c => mod-msa_helper.c} (93%)
create mode 100644 target/mips/mod-msa_translate.c
create mode 100644 target/mips/mod-msa_helper.h.inc
--
2.26.2
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 01/17] target/mips: Introduce ase_msa_available() helper
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 02/17] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé
` (16 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 6 ++++++
target/mips/kvm.c | 12 ++++++------
target/mips/translate.c | 8 +++-----
3 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7b3ff2fd6fb..6d4c8d63930 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1296,6 +1296,12 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
bool cpu_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
+/* Check presence of MSA implementation */
+static inline bool ase_msa_available(CPUMIPSState *env)
+{
+ return env->CP0_Config3 & (1 << CP0C3_MSAP);
+}
+
/* Check presence of multi-threading ASE implementation */
static inline bool ase_mt_available(CPUMIPSState *env)
{
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 3ca3a0da93f..c511a1303c6 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -82,7 +82,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
}
}
- if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (kvm_mips_msa_cap && ase_msa_available(env)) {
ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0);
if (ret < 0) {
/* mark unsupported so it gets disabled on reset */
@@ -108,7 +108,7 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu)
warn_report("KVM does not support FPU, disabling");
env->CP0_Config1 &= ~(1 << CP0C1_FP);
}
- if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (!kvm_mips_msa_cap && ase_msa_available(env)) {
warn_report("KVM does not support MSA, disabling");
env->CP0_Config3 &= ~(1 << CP0C3_MSAP);
}
@@ -621,7 +621,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
* FPU register state is a subset of MSA vector state, so don't put FPU
* registers if we're emulating a CPU with MSA.
*/
- if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if (!ase_msa_available(env)) {
/* Floating point registers */
for (i = 0; i < 32; ++i) {
if (env->CP0_Status & (1 << CP0St_FR)) {
@@ -640,7 +640,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int level)
}
/* Only put MSA state if we're emulating a CPU with MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
/* MSA Control Registers */
if (level == KVM_PUT_FULL_STATE) {
err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR,
@@ -701,7 +701,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
* FPU register state is a subset of MSA vector state, so don't save FPU
* registers if we're emulating a CPU with MSA.
*/
- if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if (!ase_msa_available(env)) {
/* Floating point registers */
for (i = 0; i < 32; ++i) {
if (env->CP0_Status & (1 << CP0St_FR)) {
@@ -720,7 +720,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
}
/* Only get MSA state if we're emulating a CPU with MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
/* MSA Control Registers */
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR,
&env->msair);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 80c9c17819f..cb822e52c4b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24928,8 +24928,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
gen_trap(ctx, op1, rs, rt, -1);
break;
case OPC_LSA: /* OPC_PMON */
- if ((ctx->insn_flags & ISA_MIPS32R6) ||
- (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
} else {
/* Pmon entry point, also R4010 selsl */
@@ -25031,8 +25030,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_DLSA:
- if ((ctx->insn_flags & ISA_MIPS32R6) ||
- (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
}
break;
@@ -31879,7 +31877,7 @@ void cpu_state_reset(CPUMIPSState *env)
}
/* MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
msa_reset(env);
}
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 02/17] target/mips: Simplify msa_reset()
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 01/17] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 03/17] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé
` (15 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 5 +----
target/mips/translate_init.c.inc | 4 ++++
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cb822e52c4b..b20cf1b52d9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31876,10 +31876,7 @@ void cpu_state_reset(CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_M16;
}
- /* MSA */
- if (ase_msa_available(env)) {
- msa_reset(env);
- }
+ msa_reset(env);
compute_hflags(env);
restore_fp_status(env);
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index cac3d241831..3c9ec7e940a 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -1024,6 +1024,10 @@ static void mvp_init(CPUMIPSState *env)
static void msa_reset(CPUMIPSState *env)
{
+ if (!ase_msa_available(env)) {
+ return;
+ }
+
#ifdef CONFIG_USER_ONLY
/* MSA access enabled */
env->CP0_Config5 |= 1 << CP0C5_MSAEn;
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 03/17] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 01/17] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 02/17] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 04/17] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
` (14 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
MSA presence is expressed by the MSAP bit of CP0_Config3.
We don't need to check anything else.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 6b9d1d4b93b..3bd41239b1d 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -379,7 +379,7 @@ static inline void compute_hflags(CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_COP1X;
}
}
- if (env->insn_flags & ASE_MSA) {
+ if (ase_msa_available(env)) {
if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
env->hflags |= MIPS_HFLAG_MSA;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 04/17] target/mips: Simplify MSA TCG logic
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 03/17] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 05/17] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé
` (13 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
Only decode MSA opcodes if MSA is present (implemented).
Now than check_msa_access() will only be called if MSA is
present, the only way to have MIPS_HFLAG_MSA unset is if
MSA is disabled (bit CP0C5_MSAEn cleared, see previous
commit). Therefore we can remove the 'reserved instruction'
exception.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b20cf1b52d9..da0cb98df09 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28576,13 +28576,8 @@ static inline int check_msa_access(DisasContext *ctx)
}
if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
- if (ctx->insn_flags & ASE_MSA) {
- generate_exception_end(ctx, EXCP_MSADIS);
- return 0;
- } else {
- generate_exception_end(ctx, EXCP_RI);
- return 0;
- }
+ generate_exception_end(ctx, EXCP_MSADIS);
+ return 0;
}
return 1;
}
@@ -30426,7 +30421,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
- check_insn(ctx, ASE_MSA);
+
check_msa_access(ctx);
switch (MASK_MSA_MINOR(opcode)) {
@@ -31073,9 +31068,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_BNZ_H:
case OPC_BNZ_W:
case OPC_BNZ_D:
- check_insn(ctx, ASE_MSA);
- gen_msa_branch(env, ctx, op1);
- break;
+ if (ase_msa_available(env)) {
+ gen_msa_branch(env, ctx, op1);
+ break;
+ }
default:
MIPS_INVAL("cp1");
generate_exception_end(ctx, EXCP_RI);
@@ -31264,7 +31260,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#endif
} else {
/* MDMX: Not implemented. */
- gen_msa(env, ctx);
+ if (ase_msa_available(env)) {
+ gen_msa(env, ctx);
+ }
}
break;
case OPC_PCREL:
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 05/17] target/mips: Remove now unused ASE_MSA definition
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 04/17] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé
` (12 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 1 -
target/mips/translate_init.c.inc | 8 ++++----
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index ed6a7a9e545..805034b8956 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -45,7 +45,6 @@
#define ASE_MT 0x0000000040000000ULL
#define ASE_SMARTMIPS 0x0000000080000000ULL
#define ASE_MICROMIPS 0x0000000100000000ULL
-#define ASE_MSA 0x0000000200000000ULL
/*
* bits 40-51: vendor-specific base instruction sets
*/
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 3c9ec7e940a..f6752d00afe 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -408,7 +408,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 32,
.PABITS = 40,
- .insn_flags = CPU_MIPS32R5 | ASE_MSA,
+ .insn_flags = CPU_MIPS32R5,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -721,7 +721,7 @@ const mips_def_t mips_defs[] =
.MSAIR = 0x03 << MSAIR_ProcID,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+ .insn_flags = CPU_MIPS64R6,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -761,7 +761,7 @@ const mips_def_t mips_defs[] =
.MSAIR = 0x03 << MSAIR_ProcID,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+ .insn_flags = CPU_MIPS64R6,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -887,7 +887,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_LOONGSON3A | ASE_MSA,
+ .insn_flags = CPU_LOONGSON3A,
.mmu_type = MMU_TYPE_R4000,
},
{
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar registers
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 05/17] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé
` (11 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
Commits 863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.
While this might be the case for CPU implementing MSA, this makes
QEMU code incoherent for CPU not implementing it. It is simpler
to inverse the logic and alias the MSA vector registers on the
FPU scalar ones.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index da0cb98df09..95d07e837c0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31561,16 +31561,20 @@ void mips_tcg_init(void)
offsetof(CPUMIPSState,
active_tc.gpr[i]),
regnames[i]);
-
for (i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
- msa_wr_d[i * 2] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]);
+
+ fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
+ }
+ /* MSA */
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+
/*
- * The scalar floating-point unit (FPU) registers are mapped on
- * the MSA vector registers.
+ * The MSA vector registers are mapped on the
+ * scalar floating-point unit (FPU) registers.
*/
- fpu_f64[i] = msa_wr_d[i * 2];
+ msa_wr_d[i * 2] = fpu_f64[i];
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_init()
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 08/17] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé
` (10 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
Extract the logic initialization of the MSA registers from
the generic initialization.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 3 +++
target/mips/translate.c | 33 +++++++++++++++++++--------------
2 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index dbf7df7ba6d..765018beeea 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -80,4 +80,7 @@ extern TCGv bcond;
} \
} while (0)
+/* MSA */
+void msa_translate_init(void);
+
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 95d07e837c0..bbe06240510 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31551,6 +31551,24 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
+static void msa_translate_init(void)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+
+ /*
+ * The MSA vector registers are mapped on the
+ * scalar floating-point unit (FPU) registers.
+ */
+ msa_wr_d[i * 2] = fpu_f64[i];
+ off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
+ msa_wr_d[i * 2 + 1] =
+ tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
+ }
+}
+
void mips_tcg_init(void)
{
int i;
@@ -31566,20 +31584,7 @@ void mips_tcg_init(void)
fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
}
- /* MSA */
- for (i = 0; i < 32; i++) {
- int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
-
- /*
- * The MSA vector registers are mapped on the
- * scalar floating-point unit (FPU) registers.
- */
- msa_wr_d[i * 2] = fpu_f64[i];
- off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
- msa_wr_d[i * 2 + 1] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
- }
-
+ msa_translate_init();
cpu_PC = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.PC), "PC");
for (i = 0; i < MIPS_DSP_ACC; i++) {
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 08/17] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 09/17] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé
` (9 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
The gen_msa*() methods don't use the "CPUMIPSState *env"
argument. Remove it to simplify.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 57 ++++++++++++++++++++---------------------
1 file changed, 28 insertions(+), 29 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bbe06240510..5ed7072f275 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28623,7 +28623,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
tcg_temp_free_i64(t1);
}
-static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
+static void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
@@ -28668,7 +28668,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
ctx->hflags |= MIPS_HFLAG_BDS32;
}
-static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_i8(DisasContext *ctx)
{
#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
uint8_t i8 = (ctx->opcode >> 16) & 0xff;
@@ -28726,7 +28726,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(ti8);
}
-static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_i5(DisasContext *ctx)
{
#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t df = (ctx->opcode >> 21) & 0x3;
@@ -28799,7 +28799,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(timm);
}
-static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_bit(DisasContext *ctx)
{
#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
@@ -28883,7 +28883,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tws);
}
-static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_3r(DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
uint8_t df = (ctx->opcode >> 21) & 0x3;
@@ -29865,7 +29865,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}
-static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_elm_3e(DisasContext *ctx)
{
#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
uint8_t source = (ctx->opcode >> 11) & 0x1f;
@@ -29897,8 +29897,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tsr);
}
-static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
- uint32_t n)
+static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
{
#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
@@ -30008,7 +30007,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
tcg_temp_free_i32(tdf);
}
-static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_elm(DisasContext *ctx)
{
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
uint32_t df = 0, n = 0;
@@ -30027,17 +30026,17 @@ static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
df = DF_DOUBLE;
} else if (dfn == 0x3E) {
/* CTCMSA, CFCMSA, MOVE.V */
- gen_msa_elm_3e(env, ctx);
+ gen_msa_elm_3e(ctx);
return;
} else {
generate_exception_end(ctx, EXCP_RI);
return;
}
- gen_msa_elm_df(env, ctx, df, n);
+ gen_msa_elm_df(ctx, df, n);
}
-static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_3rf(DisasContext *ctx)
{
#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
uint8_t df = (ctx->opcode >> 21) & 0x1;
@@ -30195,7 +30194,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}
-static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_2r(DisasContext *ctx)
{
#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0x7 << 18)))
@@ -30279,7 +30278,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}
-static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_2rf(DisasContext *ctx)
{
#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0xf << 17)))
@@ -30350,7 +30349,7 @@ static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(tdf);
}
-static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_vec_v(DisasContext *ctx)
{
#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
@@ -30393,7 +30392,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free_i32(twt);
}
-static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa_vec(DisasContext *ctx)
{
switch (MASK_MSA_VEC(ctx->opcode)) {
case OPC_AND_V:
@@ -30403,13 +30402,13 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
case OPC_BMNZ_V:
case OPC_BMZ_V:
case OPC_BSEL_V:
- gen_msa_vec_v(env, ctx);
+ gen_msa_vec_v(ctx);
break;
case OPC_MSA_2R:
- gen_msa_2r(env, ctx);
+ gen_msa_2r(ctx);
break;
case OPC_MSA_2RF:
- gen_msa_2rf(env, ctx);
+ gen_msa_2rf(ctx);
break;
default:
MIPS_INVAL("MSA instruction");
@@ -30418,7 +30417,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
}
}
-static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
+static void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
@@ -30428,15 +30427,15 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
case OPC_MSA_I8_00:
case OPC_MSA_I8_01:
case OPC_MSA_I8_02:
- gen_msa_i8(env, ctx);
+ gen_msa_i8(ctx);
break;
case OPC_MSA_I5_06:
case OPC_MSA_I5_07:
- gen_msa_i5(env, ctx);
+ gen_msa_i5(ctx);
break;
case OPC_MSA_BIT_09:
case OPC_MSA_BIT_0A:
- gen_msa_bit(env, ctx);
+ gen_msa_bit(ctx);
break;
case OPC_MSA_3R_0D:
case OPC_MSA_3R_0E:
@@ -30447,18 +30446,18 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
case OPC_MSA_3R_13:
case OPC_MSA_3R_14:
case OPC_MSA_3R_15:
- gen_msa_3r(env, ctx);
+ gen_msa_3r(ctx);
break;
case OPC_MSA_ELM:
- gen_msa_elm(env, ctx);
+ gen_msa_elm(ctx);
break;
case OPC_MSA_3RF_1A:
case OPC_MSA_3RF_1B:
case OPC_MSA_3RF_1C:
- gen_msa_3rf(env, ctx);
+ gen_msa_3rf(ctx);
break;
case OPC_MSA_VEC:
- gen_msa_vec(env, ctx);
+ gen_msa_vec(ctx);
break;
case OPC_LD_B:
case OPC_LD_H:
@@ -31069,7 +31068,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_BNZ_W:
case OPC_BNZ_D:
if (ase_msa_available(env)) {
- gen_msa_branch(env, ctx, op1);
+ gen_msa_branch(ctx, op1);
break;
}
default:
@@ -31261,7 +31260,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
} else {
/* MDMX: Not implemented. */
if (ase_msa_available(env)) {
- gen_msa(env, ctx);
+ gen_msa(ctx);
}
}
break;
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 09/17] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 08/17] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 10/17] target/mips: Rename msa_helper.c as mod-msa_helper.c Philippe Mathieu-Daudé
` (8 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
In preparation of using the decodetree script, explode
gen_msa_branch() as following:
- OPC_BZ_V -> BxZ_V(EQ)
- OPC_BNZ_V -> BxZ_V(NE)
- OPC_BZ_[BHWD] -> BxZ(false)
- OPC_BNZ_[BHWD] -> BxZ(true)
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 71 ++++++++++++++++++++++++++++-------------
1 file changed, 49 insertions(+), 22 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5ed7072f275..8b1019506fe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28623,49 +28623,76 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
tcg_temp_free_i64(t1);
}
+static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
+{
+ TCGv_i64 t0;
+
+ check_msa_access(ctx);
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ generate_exception_end(ctx, EXCP_RI);
+ return true;
+ }
+ t0 = tcg_temp_new_i64();
+ tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
+ tcg_gen_setcondi_i64(cond, t0, t0, 0);
+ tcg_gen_trunc_i64_tl(bcond, t0);
+ tcg_temp_free_i64(t0);
+
+ ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ return true;
+}
+
+static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
+{
+ check_msa_access(ctx);
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ generate_exception_end(ctx, EXCP_RI);
+ return true;
+ }
+
+ gen_check_zero_element(bcond, df, wt);
+ if (if_not) {
+ tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
+ }
+
+ ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ return true;
+}
+
static void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
int64_t s16 = (int16_t)ctx->opcode;
- check_msa_access(ctx);
-
- if (ctx->hflags & MIPS_HFLAG_BMASK) {
- generate_exception_end(ctx, EXCP_RI);
- return;
- }
switch (op1) {
case OPC_BZ_V:
case OPC_BNZ_V:
- {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
- tcg_gen_setcondi_i64((op1 == OPC_BZ_V) ?
- TCG_COND_EQ : TCG_COND_NE, t0, t0, 0);
- tcg_gen_trunc_i64_tl(bcond, t0);
- tcg_temp_free_i64(t0);
- }
+ gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
+ TCG_COND_EQ : TCG_COND_NE);
break;
case OPC_BZ_B:
case OPC_BZ_H:
case OPC_BZ_W:
case OPC_BZ_D:
- gen_check_zero_element(bcond, df, wt);
+ gen_msa_BxZ(ctx, df, wt, s16, false);
break;
case OPC_BNZ_B:
case OPC_BNZ_H:
case OPC_BNZ_W:
case OPC_BNZ_D:
- gen_check_zero_element(bcond, df, wt);
- tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
+ gen_msa_BxZ(ctx, df, wt, s16, true);
break;
}
-
- ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
-
- ctx->hflags |= MIPS_HFLAG_BC;
- ctx->hflags |= MIPS_HFLAG_BDS32;
}
static void gen_msa_i8(DisasContext *ctx)
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 10/17] target/mips: Rename msa_helper.c as mod-msa_helper.c
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 09/17] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c Philippe Mathieu-Daudé
` (7 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
MSA means 'MIPS SIMD Architecture' and is defined as a Module by
MIPS.
To keep the directory sorted, we use the 'mod' prefix for MIPS
modules. Rename msa_helper.c as mod-msa_helper.c.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201123204448.3260804-4-f4bug@amsat.org>
---
target/mips/{msa_helper.c => mod-msa_helper.c} | 0
target/mips/meson.build | 3 ++-
2 files changed, 2 insertions(+), 1 deletion(-)
rename target/mips/{msa_helper.c => mod-msa_helper.c} (100%)
diff --git a/target/mips/msa_helper.c b/target/mips/mod-msa_helper.c
similarity index 100%
rename from target/mips/msa_helper.c
rename to target/mips/mod-msa_helper.c
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 681a5524c0e..35dbbbf6519 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -6,8 +6,9 @@
'gdbstub.c',
'helper.c',
'lmmi_helper.c',
- 'msa_helper.c',
'op_helper.c',
+ 'mod-msa_helper.c',
+
'translate.c',
))
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 10/17] target/mips: Rename msa_helper.c as mod-msa_helper.c Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 23:55 ` Richard Henderson
2020-12-08 0:36 ` [PATCH 12/17] target/mips: Extract MSA helpers from op_helper.c Philippe Mathieu-Daudé
` (6 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
translate_init.c.inc mostly contains CPU definitions.
msa_reset() doesn't belong here, move it with the MSA
helpers.
One comment style is updated to avoid checkpatch.pl warning.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 2 ++
target/mips/mod-msa_helper.c | 36 ++++++++++++++++++++++++++++++++
target/mips/translate_init.c.inc | 34 ------------------------------
3 files changed, 38 insertions(+), 34 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 3bd41239b1d..7813eb224c9 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -201,6 +201,8 @@ void mips_tcg_init(void);
void cpu_state_reset(CPUMIPSState *s);
void cpu_mips_realize_env(CPUMIPSState *env);
+void msa_reset(CPUMIPSState *env);
+
/* cp0_timer.c */
uint32_t cpu_mips_get_count(CPUMIPSState *env);
void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
diff --git a/target/mips/mod-msa_helper.c b/target/mips/mod-msa_helper.c
index b89b4c44902..f0d728c03f0 100644
--- a/target/mips/mod-msa_helper.c
+++ b/target/mips/mod-msa_helper.c
@@ -8201,3 +8201,39 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_move_v(pwd, pwx);
}
+
+void msa_reset(CPUMIPSState *env)
+{
+ if (!ase_msa_available(env)) {
+ return;
+ }
+
+#ifdef CONFIG_USER_ONLY
+ /* MSA access enabled */
+ env->CP0_Config5 |= 1 << CP0C5_MSAEn;
+ env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
+#endif
+
+ /*
+ * MSA CSR:
+ * - non-signaling floating point exception mode off (NX bit is 0)
+ * - Cause, Enables, and Flags are all 0
+ * - round to nearest / ties to even (RM bits are 0)
+ */
+ env->active_tc.msacsr = 0;
+
+ restore_msa_fp_status(env);
+
+ /* tininess detected after rounding.*/
+ set_float_detect_tininess(float_tininess_after_rounding,
+ &env->active_tc.msa_fp_status);
+
+ /* clear float_status exception flags */
+ set_float_exception_flags(0, &env->active_tc.msa_fp_status);
+
+ /* clear float_status nan mode */
+ set_default_nan_mode(0, &env->active_tc.msa_fp_status);
+
+ /* set proper signanling bit meaning ("1" means "quiet") */
+ set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
+}
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index f6752d00afe..4856f4c5a4a 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -1021,37 +1021,3 @@ static void mvp_init(CPUMIPSState *env)
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
(0x1 << CP0MVPC1_PCP1);
}
-
-static void msa_reset(CPUMIPSState *env)
-{
- if (!ase_msa_available(env)) {
- return;
- }
-
-#ifdef CONFIG_USER_ONLY
- /* MSA access enabled */
- env->CP0_Config5 |= 1 << CP0C5_MSAEn;
- env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
-#endif
-
- /* MSA CSR:
- - non-signaling floating point exception mode off (NX bit is 0)
- - Cause, Enables, and Flags are all 0
- - round to nearest / ties to even (RM bits are 0) */
- env->active_tc.msacsr = 0;
-
- restore_msa_fp_status(env);
-
- /* tininess detected after rounding.*/
- set_float_detect_tininess(float_tininess_after_rounding,
- &env->active_tc.msa_fp_status);
-
- /* clear float_status exception flags */
- set_float_exception_flags(0, &env->active_tc.msa_fp_status);
-
- /* clear float_status nan mode */
- set_default_nan_mode(0, &env->active_tc.msa_fp_status);
-
- /* set proper signanling bit meaning ("1" means "quiet") */
- set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
-}
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 12/17] target/mips: Extract MSA helpers from op_helper.c
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 13/17] target/mips: Extract MSA helper definitions Philippe Mathieu-Daudé
` (5 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
We have ~400 lines of MSA helpers in the generic op_helper.c,
move them with the other helpers in 'mod-msa_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201123204448.3260804-5-f4bug@amsat.org>
---
target/mips/mod-msa_helper.c | 393 ++++++++++++++++++++++++++++++++++
target/mips/op_helper.c | 394 -----------------------------------
2 files changed, 393 insertions(+), 394 deletions(-)
diff --git a/target/mips/mod-msa_helper.c b/target/mips/mod-msa_helper.c
index f0d728c03f0..1298a1917ce 100644
--- a/target/mips/mod-msa_helper.c
+++ b/target/mips/mod-msa_helper.c
@@ -22,6 +22,7 @@
#include "internal.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
+#include "exec/memop.h"
#include "fpu/softfloat.h"
#include "fpu_helper.h"
@@ -8202,6 +8203,398 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_move_v(pwd, pwx);
}
+/* Data format min and max values */
+#define DF_BITS(df) (1 << ((df) + 3))
+
+/* Element-by-element access macros */
+#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
+
+#if !defined(CONFIG_USER_ONLY)
+#define MEMOP_IDX(DF) \
+ TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
+ cpu_mmu_index(env, false));
+#else
+#define MEMOP_IDX(DF)
+#endif
+
+void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_BYTE)
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
+ pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
+ pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
+ pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
+ pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
+ pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
+ pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
+ pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
+ pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
+ pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
+ pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
+ pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
+ pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
+ pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
+ pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
+ pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
+#else
+ pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
+ pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
+ pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
+ pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
+ pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
+ pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
+ pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
+ pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
+ pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
+ pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
+ pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
+ pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
+ pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
+ pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
+ pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
+ pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
+ pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
+ pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
+ pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
+ pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
+ pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
+ pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
+ pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
+ pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
+ pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
+ pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
+ pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
+ pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
+ pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
+ pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
+ pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
+#else
+ pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
+ pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
+ pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
+ pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
+ pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
+ pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
+ pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
+ pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
+ pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
+ pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
+ pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
+ pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
+ pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
+ pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
+ pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
+ pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
+#endif
+#endif
+}
+
+void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_HALF)
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
+ pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
+ pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
+ pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
+ pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
+ pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
+ pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
+ pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
+#else
+ pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
+ pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
+ pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
+ pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
+ pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
+ pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
+ pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
+ pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
+ pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
+ pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
+ pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
+ pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
+ pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
+ pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
+ pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
+#else
+ pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
+ pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
+ pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
+ pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
+ pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
+ pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
+ pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
+ pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
+#endif
+#endif
+}
+
+void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_WORD)
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
+ pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
+ pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
+ pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
+#else
+ pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
+ pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
+ pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
+ pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
+ pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
+ pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
+ pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
+#else
+ pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
+ pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
+ pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
+ pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
+#endif
+#endif
+}
+
+void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_DOUBLE)
+#if !defined(CONFIG_USER_ONLY)
+ pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
+ pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
+#else
+ pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
+ pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
+#endif
+}
+
+#define MSA_PAGESPAN(x) \
+ ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)
+
+static inline void ensure_writable_pages(CPUMIPSState *env,
+ target_ulong addr,
+ int mmu_idx,
+ uintptr_t retaddr)
+{
+ /* FIXME: Probe the actual accesses (pass and use a size) */
+ if (unlikely(MSA_PAGESPAN(addr))) {
+ /* first page */
+ probe_write(env, addr, 0, mmu_idx, retaddr);
+ /* second page */
+ addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
+ probe_write(env, addr, 0, mmu_idx, retaddr);
+ }
+}
+
+void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_BYTE)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
+#else
+ helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
+ cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
+ cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
+ cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
+ cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
+ cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
+ cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
+ cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
+ cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
+ cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
+ cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
+ cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
+ cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
+ cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
+ cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
+ cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
+#else
+ cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
+ cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
+ cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
+ cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
+ cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
+ cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
+ cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
+ cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
+ cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
+ cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
+ cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
+ cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
+ cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
+ cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
+ cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
+ cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
+#endif
+#endif
+}
+
+void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_HALF)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
+#else
+ helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
+ cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
+ cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
+ cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
+ cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
+ cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
+ cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
+ cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
+#else
+ cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
+ cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
+ cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
+ cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
+ cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
+ cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
+ cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
+ cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
+#endif
+#endif
+}
+
+void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_WORD)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
+#else
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
+ cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
+ cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
+ cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
+#else
+ cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
+ cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
+ cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
+ cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
+#endif
+#endif
+}
+
+void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_DOUBLE)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+ helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
+ helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
+#else
+ cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
+ cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
+#endif
+}
+
void msa_reset(CPUMIPSState *env)
{
if (!ase_msa_available(env)) {
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 72613706188..dd09a4c714a 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -28,7 +28,6 @@
#include "exec/cpu_ldst.h"
#include "exec/memop.h"
#include "sysemu/kvm.h"
-#include "fpu_helper.h"
/*****************************************************************************/
@@ -1179,399 +1178,6 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
#endif /* !CONFIG_USER_ONLY */
-/* MSA */
-/* Data format min and max values */
-#define DF_BITS(df) (1 << ((df) + 3))
-
-/* Element-by-element access macros */
-#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
-
-#if !defined(CONFIG_USER_ONLY)
-#define MEMOP_IDX(DF) \
- TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
- cpu_mmu_index(env, false));
-#else
-#define MEMOP_IDX(DF)
-#endif
-
-void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_BYTE)
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
- pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
- pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
- pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
- pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
- pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
- pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
- pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
- pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
- pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
- pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
- pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
- pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
- pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
- pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
- pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
-#else
- pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
- pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
- pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
- pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
- pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
- pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
- pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
- pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
- pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
- pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
- pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
- pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
- pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
- pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
- pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
- pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
- pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
- pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
- pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
- pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
- pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
- pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
- pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
- pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
- pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
- pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
- pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
- pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
- pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
- pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
- pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
-#else
- pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
- pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
- pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
- pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
- pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
- pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
- pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
- pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
- pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
- pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
- pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
- pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
- pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
- pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
- pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
- pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
-#endif
-#endif
-}
-
-void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_HALF)
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
- pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
- pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
- pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
- pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
- pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
- pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
- pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
-#else
- pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
- pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
- pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
- pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
- pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
- pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
- pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
- pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
- pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
- pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
- pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
- pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
- pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
- pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
- pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
-#else
- pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
- pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
- pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
- pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
- pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
- pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
- pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
- pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
-#endif
-#endif
-}
-
-void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_WORD)
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
- pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
- pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
- pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
-#else
- pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
- pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
- pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
- pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
- pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
- pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
- pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
-#else
- pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
- pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
- pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
- pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
-#endif
-#endif
-}
-
-void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_DOUBLE)
-#if !defined(CONFIG_USER_ONLY)
- pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
- pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
-#else
- pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
- pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
-#endif
-}
-
-#define MSA_PAGESPAN(x) \
- ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)
-
-static inline void ensure_writable_pages(CPUMIPSState *env,
- target_ulong addr,
- int mmu_idx,
- uintptr_t retaddr)
-{
- /* FIXME: Probe the actual accesses (pass and use a size) */
- if (unlikely(MSA_PAGESPAN(addr))) {
- /* first page */
- probe_write(env, addr, 0, mmu_idx, retaddr);
- /* second page */
- addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
- probe_write(env, addr, 0, mmu_idx, retaddr);
- }
-}
-
-void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- int mmu_idx = cpu_mmu_index(env, false);
-
- MEMOP_IDX(DF_BYTE)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
-#else
- helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
- cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
- cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
- cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
- cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
- cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
- cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
- cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
- cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
- cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
- cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
- cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
- cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
- cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
- cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
- cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
-#else
- cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
- cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
- cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
- cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
- cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
- cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
- cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
- cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
- cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
- cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
- cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
- cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
- cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
- cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
- cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
- cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
-#endif
-#endif
-}
-
-void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- int mmu_idx = cpu_mmu_index(env, false);
-
- MEMOP_IDX(DF_HALF)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
-#else
- helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
- cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
- cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
- cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
- cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
- cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
- cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
- cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
-#else
- cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
- cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
- cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
- cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
- cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
- cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
- cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
- cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
-#endif
-#endif
-}
-
-void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- int mmu_idx = cpu_mmu_index(env, false);
-
- MEMOP_IDX(DF_WORD)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
-#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
-#else
- helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
- cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
- cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
- cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
-#else
- cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
- cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
- cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
- cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
-#endif
-#endif
-}
-
-void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
- target_ulong addr)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- int mmu_idx = cpu_mmu_index(env, false);
-
- MEMOP_IDX(DF_DOUBLE)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
- helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
- helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
-#else
- cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
- cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
-#endif
-}
-
void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
{
#ifndef CONFIG_USER_ONLY
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 13/17] target/mips: Extract MSA helper definitions
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 12/17] target/mips: Extract MSA helpers from op_helper.c Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h' Philippe Mathieu-Daudé
` (4 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
Keep all MSA-related code altogether.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201120210844.2625602-4-f4bug@amsat.org>
---
target/mips/helper.h | 436 +-----------------------------
target/mips/mod-msa_helper.h.inc | 443 +++++++++++++++++++++++++++++++
2 files changed, 445 insertions(+), 434 deletions(-)
create mode 100644 target/mips/mod-msa_helper.h.inc
diff --git a/target/mips/helper.h b/target/mips/helper.h
index e97655dc0eb..80eb675fa64 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -781,438 +781,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env)
DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env)
DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
-/* MIPS SIMD Architecture */
-
-DEF_HELPER_3(msa_nloc_b, void, env, i32, i32)
-DEF_HELPER_3(msa_nloc_h, void, env, i32, i32)
-DEF_HELPER_3(msa_nloc_w, void, env, i32, i32)
-DEF_HELPER_3(msa_nloc_d, void, env, i32, i32)
-
-DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32)
-DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32)
-DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32)
-DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32)
-
-DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32)
-DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32)
-DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32)
-DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32)
-
-DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32)
-
-DEF_HELPER_3(msa_move_v, void, env, i32, i32)
-
-DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32)
-DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32)
-
-DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32)
-DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
-DEF_HELPER_2(msa_cfcmsa, tl, env, i32)
-
-DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32)
-
-DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)
-
-#define MSALDST_PROTO(type) \
-DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \
-DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)
-MSALDST_PROTO(b)
-MSALDST_PROTO(h)
-MSALDST_PROTO(w)
-MSALDST_PROTO(d)
-#undef MSALDST_PROTO
-
DEF_HELPER_3(cache, void, env, tl, i32)
+
+#include "mod-msa_helper.h.inc"
diff --git a/target/mips/mod-msa_helper.h.inc b/target/mips/mod-msa_helper.h.inc
new file mode 100644
index 00000000000..4963d1553a0
--- /dev/null
+++ b/target/mips/mod-msa_helper.h.inc
@@ -0,0 +1,443 @@
+/*
+ * MIPS SIMD Architecture Module (MSA) helpers for QEMU.
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
+ * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+DEF_HELPER_3(msa_nloc_b, void, env, i32, i32)
+DEF_HELPER_3(msa_nloc_h, void, env, i32, i32)
+DEF_HELPER_3(msa_nloc_w, void, env, i32, i32)
+DEF_HELPER_3(msa_nloc_d, void, env, i32, i32)
+
+DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32)
+DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32)
+DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32)
+DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32)
+
+DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32)
+DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32)
+DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32)
+DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32)
+
+DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32)
+
+DEF_HELPER_3(msa_move_v, void, env, i32, i32)
+
+DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32)
+DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32)
+DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32)
+
+DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32)
+DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
+DEF_HELPER_2(msa_cfcmsa, tl, env, i32)
+
+DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)
+
+#define MSALDST_PROTO(type) \
+DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \
+DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)
+MSALDST_PROTO(b)
+MSALDST_PROTO(h)
+MSALDST_PROTO(w)
+MSALDST_PROTO(d)
+#undef MSALDST_PROTO
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h'
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 13/17] target/mips: Extract MSA helper definitions Philippe Mathieu-Daudé
@ 2020-12-08 0:36 ` Philippe Mathieu-Daudé
2020-12-08 23:56 ` Richard Henderson
2020-12-08 0:37 ` [PATCH 16/17] target/mips: Introduce decode tree bindings for MSA opcodes Philippe Mathieu-Daudé
` (3 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:36 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
Make gen_msa() and gen_msa_branch() public declarations
so we can keep calling them once extracted from the big
translate.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 2 ++
target/mips/translate.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 765018beeea..c26b0d9155d 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -82,5 +82,7 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
+void gen_msa(DisasContext *ctx);
+void gen_msa_branch(DisasContext *ctx, uint32_t op1);
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8b1019506fe..d8553c626f3 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28668,7 +28668,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
return true;
}
-static void gen_msa_branch(DisasContext *ctx, uint32_t op1)
+void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
@@ -30444,7 +30444,7 @@ static void gen_msa_vec(DisasContext *ctx)
}
}
-static void gen_msa(DisasContext *ctx)
+void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 16/17] target/mips: Introduce decode tree bindings for MSA opcodes
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2020-12-08 0:36 ` [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h' Philippe Mathieu-Daudé
@ 2020-12-08 0:37 ` Philippe Mathieu-Daudé
2020-12-09 0:05 ` Richard Henderson
2020-12-09 4:09 ` Jiaxun Yang
2020-12-08 0:37 ` [PATCH 17/17] target/mips: Use decode_msa32() generated from decodetree Philippe Mathieu-Daudé
` (2 subsequent siblings)
17 siblings, 2 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:37 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE.
We decode the branch instructions, and all instructions based
on the MSA opcode.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 1 +
target/mips/mod-msa32.decode | 24 ++++++++++++++++++++++++
target/mips/mod-msa_translate.c | 31 +++++++++++++++++++++++++++++++
target/mips/meson.build | 5 +++++
4 files changed, 61 insertions(+)
create mode 100644 target/mips/mod-msa32.decode
diff --git a/target/mips/translate.h b/target/mips/translate.h
index c26b0d9155d..c4fe18d187e 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -84,5 +84,6 @@ extern TCGv bcond;
void msa_translate_init(void);
void gen_msa(DisasContext *ctx);
void gen_msa_branch(DisasContext *ctx, uint32_t op1);
+bool decode_msa32(DisasContext *ctx, uint32_t insn);
#endif
diff --git a/target/mips/mod-msa32.decode b/target/mips/mod-msa32.decode
new file mode 100644
index 00000000000..d69675132b8
--- /dev/null
+++ b/target/mips/mod-msa32.decode
@@ -0,0 +1,24 @@
+# MIPS SIMD Architecture Module instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume IV-j
+# The MIPS32 SIMD Architecture Module, Revision 1.12
+# (Document Number: MD00866-2B-MSA32-AFP-01.12)
+#
+
+&msa_bz df wt s16
+
+@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
+@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
+
+BZ_V 010001 01011 ..... ................ @bz
+BNZ_V 010001 01111 ..... ................ @bz
+
+BZ_x 010001 110 .. ..... ................ @bz_df
+BNZ_x 010001 111 .. ..... ................ @bz_df
+
+MSA 011110 --------------------------
diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translate.c
index 55c2a2f1acc..02df39c6b6c 100644
--- a/target/mips/mod-msa_translate.c
+++ b/target/mips/mod-msa_translate.c
@@ -6,6 +6,7 @@
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
@@ -17,6 +18,9 @@
#include "fpu_helper.h"
#include "internal.h"
+/* Include the auto-generated decoder. */
+#include "decode-mod-msa32.c.inc"
+
#define OPC_MSA (0x1E << 26)
#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
@@ -370,6 +374,16 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
return true;
}
+static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
+}
+
+static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
+}
+
static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
{
check_msa_access(ctx);
@@ -391,6 +405,16 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
return true;
}
+static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
+}
+
+static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
+}
+
void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
@@ -2264,3 +2288,10 @@ void gen_msa(DisasContext *ctx)
break;
}
}
+
+static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
+{
+ gen_msa(ctx);
+
+ return true;
+}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index b6697e2fd72..7d0414bbe23 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,4 +1,9 @@
+gen = [
+ decodetree.process('mod-msa32.decode', extra_args: [ '--decode=decode_msa32' ]),
+]
+
mips_ss = ss.source_set()
+mips_ss.add(gen)
mips_ss.add(files(
'cpu.c',
'dsp_helper.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 17/17] target/mips: Use decode_msa32() generated from decodetree
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2020-12-08 0:37 ` [PATCH 16/17] target/mips: Introduce decode tree bindings for MSA opcodes Philippe Mathieu-Daudé
@ 2020-12-08 0:37 ` Philippe Mathieu-Daudé
2020-12-09 0:06 ` Richard Henderson
2020-12-08 0:39 ` [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
2020-12-09 4:07 ` Jiaxun Yang
17 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:37 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, Philippe Mathieu-Daudé,
kvm, Richard Henderson, Aurelien Jarno, Huacai Chen, Jiaxun Yang
Now that we can decode the MSA ASE opcodes with decode_msa32(),
use it and remove the unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/fpu_translate.h | 10 ----------
target/mips/translate.h | 2 --
target/mips/mod-msa_translate.c | 29 +----------------------------
target/mips/translate.c | 31 ++++++++++---------------------
4 files changed, 11 insertions(+), 61 deletions(-)
diff --git a/target/mips/fpu_translate.h b/target/mips/fpu_translate.h
index f45314d2ec2..58e5e768c99 100644
--- a/target/mips/fpu_translate.h
+++ b/target/mips/fpu_translate.h
@@ -42,8 +42,6 @@ enum {
OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
- OPC_BZ_V = (0x0B << 21) | OPC_CP1,
- OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
@@ -53,14 +51,6 @@ enum {
OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
- OPC_BZ_B = (0x18 << 21) | OPC_CP1,
- OPC_BZ_H = (0x19 << 21) | OPC_CP1,
- OPC_BZ_W = (0x1A << 21) | OPC_CP1,
- OPC_BZ_D = (0x1B << 21) | OPC_CP1,
- OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
- OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
- OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
- OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
};
#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
diff --git a/target/mips/translate.h b/target/mips/translate.h
index c4fe18d187e..cba28f49753 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -82,8 +82,6 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
-void gen_msa(DisasContext *ctx);
-void gen_msa_branch(DisasContext *ctx, uint32_t op1);
bool decode_msa32(DisasContext *ctx, uint32_t insn);
#endif
diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translate.c
index 02df39c6b6c..7e7fc0644ff 100644
--- a/target/mips/mod-msa_translate.c
+++ b/target/mips/mod-msa_translate.c
@@ -415,33 +415,6 @@ static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
}
-void gen_msa_branch(DisasContext *ctx, uint32_t op1)
-{
- uint8_t df = (ctx->opcode >> 21) & 0x3;
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- int64_t s16 = (int16_t)ctx->opcode;
-
- switch (op1) {
- case OPC_BZ_V:
- case OPC_BNZ_V:
- gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
- TCG_COND_EQ : TCG_COND_NE);
- break;
- case OPC_BZ_B:
- case OPC_BZ_H:
- case OPC_BZ_W:
- case OPC_BZ_D:
- gen_msa_BxZ(ctx, df, wt, s16, false);
- break;
- case OPC_BNZ_B:
- case OPC_BNZ_H:
- case OPC_BNZ_W:
- case OPC_BNZ_D:
- gen_msa_BxZ(ctx, df, wt, s16, true);
- break;
- }
-}
-
static void gen_msa_i8(DisasContext *ctx)
{
#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
@@ -2191,7 +2164,7 @@ static void gen_msa_vec(DisasContext *ctx)
}
}
-void gen_msa(DisasContext *ctx)
+static void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5cd67459304..41c0b59a473 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6,6 +6,7 @@
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -141,8 +142,6 @@ enum {
OPC_JIALC = (0x3E << 26),
/* MDMX ASE specific */
OPC_MDMX = (0x1E << 26),
- /* MSA ASE, same as MDMX */
- OPC_MSA = OPC_MDMX,
/* Cache and prefetch */
OPC_CACHE = (0x2F << 26),
OPC_PREF = (0x33 << 26),
@@ -28336,6 +28335,13 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_set_label(l1);
}
+ /* Transition to the auto-generated decoder. */
+
+ /* ISA Extensions */
+ if (ase_msa_available(env) && decode_msa32(ctx, ctx->opcode)) {
+ return;
+ }
+
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
@@ -28853,20 +28859,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
}
- case OPC_BZ_V:
- case OPC_BNZ_V:
- case OPC_BZ_B:
- case OPC_BZ_H:
- case OPC_BZ_W:
- case OPC_BZ_D:
- case OPC_BNZ_B:
- case OPC_BNZ_H:
- case OPC_BNZ_W:
- case OPC_BNZ_D:
- if (ase_msa_available(env)) {
- gen_msa_branch(ctx, op1);
- break;
- }
default:
MIPS_INVAL("cp1");
generate_exception_end(ctx, EXCP_RI);
@@ -29048,16 +29040,13 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
}
break;
- case OPC_MSA: /* OPC_MDMX */
+ case OPC_MDMX: /* MMI_OPC_LQ */
if (ctx->insn_flags & INSN_R5900) {
#if defined(TARGET_MIPS64)
- gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */
+ gen_mmi_lq(env, ctx);
#endif
} else {
/* MDMX: Not implemented. */
- if (ase_msa_available(env)) {
- gen_msa(ctx);
- }
}
break;
case OPC_PCREL:
--
2.26.2
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH 00/17] target/mips: Convert MSA ASE to decodetree
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2020-12-08 0:37 ` [PATCH 17/17] target/mips: Use decode_msa32() generated from decodetree Philippe Mathieu-Daudé
@ 2020-12-08 0:39 ` Philippe Mathieu-Daudé
2020-12-08 16:30 ` Philippe Mathieu-Daudé
2020-12-09 4:07 ` Jiaxun Yang
17 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 0:39 UTC (permalink / raw)
To: qemu-devel@nongnu.org Developers
Cc: Aleksandar Rikalo, Paolo Bonzini, kvm, Richard Henderson,
Aurelien Jarno, Huacai Chen, Jiaxun Yang
On Tue, Dec 8, 2020 at 1:37 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Finally, we use decodetree with the MIPS target.
>
> Starting easy with the MSA ASE. 2700+ lines extracted
> from helper.h and translate.c, now built as an new
> object: mod-msa_translate.o.
>
> While the diff stat is positive by 86 lines, we actually
> (re)moved code, but added (C) notices.
>
> The most interesting patches are the 2 last ones.
>
> Please review,
I forgot to mention, only 4/17 patches miss review!
- 11, 14, 16, 17
>
> Phil.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 00/17] target/mips: Convert MSA ASE to decodetree
2020-12-08 0:39 ` [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
@ 2020-12-08 16:30 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-08 16:30 UTC (permalink / raw)
To: qemu-devel@nongnu.org Developers
Cc: Aleksandar Rikalo, kvm, Huacai Chen, Richard Henderson,
Paolo Bonzini, Aurelien Jarno, Jiaxun Yang
On 12/8/20 1:39 AM, Philippe Mathieu-Daudé wrote:
> On Tue, Dec 8, 2020 at 1:37 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> Finally, we use decodetree with the MIPS target.
>>
>> Starting easy with the MSA ASE. 2700+ lines extracted
>> from helper.h and translate.c, now built as an new
>> object: mod-msa_translate.o.
>>
>> While the diff stat is positive by 86 lines, we actually
>> (re)moved code, but added (C) notices.
>>
>> The most interesting patches are the 2 last ones.
>>
>> Please review,
>
> I forgot to mention, only 4/17 patches miss review!
> - 11, 14, 16, 17
Full series available here:
https://gitlab.com/philmd/qemu/-/tags/20201208003702.4088927-1-f4bug@amsat.org
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c
2020-12-08 0:36 ` [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c Philippe Mathieu-Daudé
@ 2020-12-08 23:55 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-08 23:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, kvm, Aurelien Jarno,
Huacai Chen, Jiaxun Yang
On 12/7/20 6:36 PM, Philippe Mathieu-Daudé wrote:
> translate_init.c.inc mostly contains CPU definitions.
> msa_reset() doesn't belong here, move it with the MSA
> helpers.
>
> One comment style is updated to avoid checkpatch.pl warning.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/internal.h | 2 ++
> target/mips/mod-msa_helper.c | 36 ++++++++++++++++++++++++++++++++
> target/mips/translate_init.c.inc | 34 ------------------------------
> 3 files changed, 38 insertions(+), 34 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h'
2020-12-08 0:36 ` [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h' Philippe Mathieu-Daudé
@ 2020-12-08 23:56 ` Richard Henderson
2020-12-09 0:01 ` Richard Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-12-08 23:56 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, kvm, Aurelien Jarno,
Huacai Chen, Jiaxun Yang
On 12/7/20 6:36 PM, Philippe Mathieu-Daudé wrote:
> Make gen_msa() and gen_msa_branch() public declarations
> so we can keep calling them once extracted from the big
> translate.c in the next commit.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.h | 2 ++
> target/mips/translate.c | 4 ++--
> 2 files changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h'
2020-12-08 23:56 ` Richard Henderson
@ 2020-12-09 0:01 ` Richard Henderson
2020-12-09 0:03 ` Richard Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 0:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, kvm, Aurelien Jarno,
Huacai Chen, Jiaxun Yang
On 12/8/20 5:56 PM, Richard Henderson wrote:
> On 12/7/20 6:36 PM, Philippe Mathieu-Daudé wrote:
>> Make gen_msa() and gen_msa_branch() public declarations
>> so we can keep calling them once extracted from the big
>> translate.c in the next commit.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> target/mips/translate.h | 2 ++
>> target/mips/translate.c | 4 ++--
>> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Actually, I think this should be dropped, and two other patches rearranged.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h'
2020-12-09 0:01 ` Richard Henderson
@ 2020-12-09 0:03 ` Richard Henderson
2020-12-09 9:17 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 0:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, kvm, Aurelien Jarno,
Huacai Chen, Jiaxun Yang
On 12/8/20 6:01 PM, Richard Henderson wrote:
> On 12/8/20 5:56 PM, Richard Henderson wrote:
>> On 12/7/20 6:36 PM, Philippe Mathieu-Daudé wrote:
>>> Make gen_msa() and gen_msa_branch() public declarations
>>> so we can keep calling them once extracted from the big
>>> translate.c in the next commit.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> ---
>>> target/mips/translate.h | 2 ++
>>> target/mips/translate.c | 4 ++--
>>> 2 files changed, 4 insertions(+), 2 deletions(-)
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Actually, I think this should be dropped, and two other patches rearranged.
Actually, nevermind, you already get the right result in the end; there's no
point re-rearranging.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 16/17] target/mips: Introduce decode tree bindings for MSA opcodes
2020-12-08 0:37 ` [PATCH 16/17] target/mips: Introduce decode tree bindings for MSA opcodes Philippe Mathieu-Daudé
@ 2020-12-09 0:05 ` Richard Henderson
2020-12-09 4:09 ` Jiaxun Yang
1 sibling, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 0:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, kvm, Aurelien Jarno,
Huacai Chen, Jiaxun Yang
On 12/7/20 6:37 PM, Philippe Mathieu-Daudé wrote:
> Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE.
>
> We decode the branch instructions, and all instructions based
> on the MSA opcode.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.h | 1 +
> target/mips/mod-msa32.decode | 24 ++++++++++++++++++++++++
> target/mips/mod-msa_translate.c | 31 +++++++++++++++++++++++++++++++
> target/mips/meson.build | 5 +++++
> 4 files changed, 61 insertions(+)
> create mode 100644 target/mips/mod-msa32.decode
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 17/17] target/mips: Use decode_msa32() generated from decodetree
2020-12-08 0:37 ` [PATCH 17/17] target/mips: Use decode_msa32() generated from decodetree Philippe Mathieu-Daudé
@ 2020-12-09 0:06 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 0:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, kvm, Aurelien Jarno,
Huacai Chen, Jiaxun Yang
On 12/7/20 6:37 PM, Philippe Mathieu-Daudé wrote:
> Now that we can decode the MSA ASE opcodes with decode_msa32(),
> use it and remove the unreachable code.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/fpu_translate.h | 10 ----------
> target/mips/translate.h | 2 --
> target/mips/mod-msa_translate.c | 29 +----------------------------
> target/mips/translate.c | 31 ++++++++++---------------------
> 4 files changed, 11 insertions(+), 61 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 00/17] target/mips: Convert MSA ASE to decodetree
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2020-12-08 0:39 ` [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
@ 2020-12-09 4:07 ` Jiaxun Yang
17 siblings, 0 replies; 29+ messages in thread
From: Jiaxun Yang @ 2020-12-09 4:07 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, kvm, Richard Henderson,
Aurelien Jarno, Huacai Chen
在 2020/12/8 上午8:36, Philippe Mathieu-Daudé 写道:
> Finally, we use decodetree with the MIPS target.
>
> Starting easy with the MSA ASE. 2700+ lines extracted
> from helper.h and translate.c, now built as an new
> object: mod-msa_translate.o.
>
> While the diff stat is positive by 86 lines, we actually
> (re)moved code, but added (C) notices.
>
> The most interesting patches are the 2 last ones.
>
> Please review,
>
> Phil.
>
> Based-on: <20201207224335.4030582-1-f4bug@amsat.org>
> (linux-user: Rework get_elf_hwcap() and support MIPS Loongson 2F/3A)
> Based-on: <20201207235539.4070364-1-f4bug@amsat.org>
> (target/mips: Add translate.h and fpu_translate.h headers)
Great work!
For the whole series:
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> Philippe Mathieu-Daudé (17):
> target/mips: Introduce ase_msa_available() helper
> target/mips: Simplify msa_reset()
> target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
> target/mips: Simplify MSA TCG logic
> target/mips: Remove now unused ASE_MSA definition
> target/mips: Alias MSA vector registers on FPU scalar registers
> target/mips: Extract msa_translate_init() from mips_tcg_init()
> target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
> target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
> target/mips: Rename msa_helper.c as mod-msa_helper.c
> target/mips: Move msa_reset() to mod-msa_helper.c
> target/mips: Extract MSA helpers from op_helper.c
> target/mips: Extract MSA helper definitions
> target/mips: Declare gen_msa/_branch() in 'translate.h'
> target/mips: Extract MSA translation routines
> target/mips: Introduce decode tree bindings for MSA opcodes
> target/mips: Use decode_msa32() generated from decodetree
>
> target/mips/cpu.h | 6 +
> target/mips/fpu_translate.h | 10 -
> target/mips/helper.h | 436 +---
> target/mips/internal.h | 4 +-
> target/mips/mips-defs.h | 1 -
> target/mips/translate.h | 4 +
> target/mips/mod-msa32.decode | 24 +
> target/mips/kvm.c | 12 +-
> .../mips/{msa_helper.c => mod-msa_helper.c} | 429 ++++
> target/mips/mod-msa_translate.c | 2270 +++++++++++++++++
> target/mips/op_helper.c | 394 ---
> target/mips/translate.c | 2264 +---------------
> target/mips/meson.build | 9 +-
> target/mips/mod-msa_helper.h.inc | 443 ++++
> target/mips/translate_init.c.inc | 38 +-
> 15 files changed, 3215 insertions(+), 3129 deletions(-)
> create mode 100644 target/mips/mod-msa32.decode
> rename target/mips/{msa_helper.c => mod-msa_helper.c} (93%)
> create mode 100644 target/mips/mod-msa_translate.c
> create mode 100644 target/mips/mod-msa_helper.h.inc
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 16/17] target/mips: Introduce decode tree bindings for MSA opcodes
2020-12-08 0:37 ` [PATCH 16/17] target/mips: Introduce decode tree bindings for MSA opcodes Philippe Mathieu-Daudé
2020-12-09 0:05 ` Richard Henderson
@ 2020-12-09 4:09 ` Jiaxun Yang
1 sibling, 0 replies; 29+ messages in thread
From: Jiaxun Yang @ 2020-12-09 4:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, Paolo Bonzini, kvm, Richard Henderson,
Aurelien Jarno, Huacai Chen
在 2020/12/8 上午8:37, Philippe Mathieu-Daudé 写道:
> Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE.
>
> We decode the branch instructions, and all instructions based
> on the MSA opcode.
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Double checked opcode formats with the manual.
Thanks!
- Jiaxun
> ---
> target/mips/translate.h | 1 +
> target/mips/mod-msa32.decode | 24 ++++++++++++++++++++++++
> target/mips/mod-msa_translate.c | 31 +++++++++++++++++++++++++++++++
> target/mips/meson.build | 5 +++++
> 4 files changed, 61 insertions(+)
> create mode 100644 target/mips/mod-msa32.decode
>
> diff --git a/target/mips/translate.h b/target/mips/translate.h
> index c26b0d9155d..c4fe18d187e 100644
> --- a/target/mips/translate.h
> +++ b/target/mips/translate.h
> @@ -84,5 +84,6 @@ extern TCGv bcond;
> void msa_translate_init(void);
> void gen_msa(DisasContext *ctx);
> void gen_msa_branch(DisasContext *ctx, uint32_t op1);
> +bool decode_msa32(DisasContext *ctx, uint32_t insn);
>
> #endif
> diff --git a/target/mips/mod-msa32.decode b/target/mips/mod-msa32.decode
> new file mode 100644
> index 00000000000..d69675132b8
> --- /dev/null
> +++ b/target/mips/mod-msa32.decode
> @@ -0,0 +1,24 @@
> +# MIPS SIMD Architecture Module instruction set
> +#
> +# Copyright (C) 2020 Philippe Mathieu-Daudé
> +#
> +# SPDX-License-Identifier: LGPL-2.1-or-later
> +#
> +# Reference:
> +# MIPS Architecture for Programmers Volume IV-j
> +# The MIPS32 SIMD Architecture Module, Revision 1.12
> +# (Document Number: MD00866-2B-MSA32-AFP-01.12)
> +#
> +
> +&msa_bz df wt s16
> +
> +@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
> +@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
> +
> +BZ_V 010001 01011 ..... ................ @bz
> +BNZ_V 010001 01111 ..... ................ @bz
> +
> +BZ_x 010001 110 .. ..... ................ @bz_df
> +BNZ_x 010001 111 .. ..... ................ @bz_df
> +
> +MSA 011110 --------------------------
> diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translate.c
> index 55c2a2f1acc..02df39c6b6c 100644
> --- a/target/mips/mod-msa_translate.c
> +++ b/target/mips/mod-msa_translate.c
> @@ -6,6 +6,7 @@
> * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
> * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
> * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
> + * Copyright (c) 2020 Philippe Mathieu-Daudé
> *
> * SPDX-License-Identifier: LGPL-2.1-or-later
> */
> @@ -17,6 +18,9 @@
> #include "fpu_helper.h"
> #include "internal.h"
>
> +/* Include the auto-generated decoder. */
> +#include "decode-mod-msa32.c.inc"
> +
> #define OPC_MSA (0x1E << 26)
>
> #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
> @@ -370,6 +374,16 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
> return true;
> }
>
> +static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
> +{
> + return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
> +}
> +
> +static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
> +{
> + return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
> +}
> +
> static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
> {
> check_msa_access(ctx);
> @@ -391,6 +405,16 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
> return true;
> }
>
> +static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
> +{
> + return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
> +}
> +
> +static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
> +{
> + return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
> +}
> +
> void gen_msa_branch(DisasContext *ctx, uint32_t op1)
> {
> uint8_t df = (ctx->opcode >> 21) & 0x3;
> @@ -2264,3 +2288,10 @@ void gen_msa(DisasContext *ctx)
> break;
> }
> }
> +
> +static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
> +{
> + gen_msa(ctx);
> +
> + return true;
> +}
> diff --git a/target/mips/meson.build b/target/mips/meson.build
> index b6697e2fd72..7d0414bbe23 100644
> --- a/target/mips/meson.build
> +++ b/target/mips/meson.build
> @@ -1,4 +1,9 @@
> +gen = [
> + decodetree.process('mod-msa32.decode', extra_args: [ '--decode=decode_msa32' ]),
> +]
> +
> mips_ss = ss.source_set()
> +mips_ss.add(gen)
> mips_ss.add(files(
> 'cpu.c',
> 'dsp_helper.c',
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h'
2020-12-09 0:03 ` Richard Henderson
@ 2020-12-09 9:17 ` Philippe Mathieu-Daudé
2020-12-09 15:25 ` Richard Henderson
0 siblings, 1 reply; 29+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-09 9:17 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Aleksandar Rikalo, kvm, Huacai Chen, Paolo Bonzini, Aurelien Jarno
Hi Richard,
On 12/9/20 1:03 AM, Richard Henderson wrote:
> On 12/8/20 6:01 PM, Richard Henderson wrote:
>> On 12/8/20 5:56 PM, Richard Henderson wrote:
>>> On 12/7/20 6:36 PM, Philippe Mathieu-Daudé wrote:
>>>> Make gen_msa() and gen_msa_branch() public declarations
>>>> so we can keep calling them once extracted from the big
>>>> translate.c in the next commit.
>>>>
>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>> ---
>>>> target/mips/translate.h | 2 ++
>>>> target/mips/translate.c | 4 ++--
>>>> 2 files changed, 4 insertions(+), 2 deletions(-)
>>>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>
>> Actually, I think this should be dropped, and two other patches rearranged.
>
> Actually, nevermind, you already get the right result in the end; there's no
> point re-rearranging.
I'm interested in looking at your idea to see if I can follow it
for the next conversions after the MSA ASE. The criteria I'm using
is (in this order):
- keep bisectability working
- keep patches trivial enough to review
- avoid moving things twice
In a previous version I tried to directly pass from
static void gen_msa(DisasContext *ctx) ...
to:
static bool trans_MSA(DisasContext *ctx, arg_MSA *a) ...
without declaring the intermediate 'void gen_msa(DisasContext)'
in "translate.h" (this patch). The result was less trivial to
review, so I went back to using an intermediate patch for
simplicity.
Is that what you were thinking about?
Thanks,
Phil.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h'
2020-12-09 9:17 ` Philippe Mathieu-Daudé
@ 2020-12-09 15:25 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2020-12-09 15:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Aleksandar Rikalo, kvm, Huacai Chen, Paolo Bonzini, Aurelien Jarno
On 12/9/20 3:17 AM, Philippe Mathieu-Daudé wrote:
> Hi Richard,
>
> On 12/9/20 1:03 AM, Richard Henderson wrote:
> In a previous version I tried to directly pass from
>
> static void gen_msa(DisasContext *ctx) ...
>
> to:
>
> static bool trans_MSA(DisasContext *ctx, arg_MSA *a) ...
>
> without declaring the intermediate 'void gen_msa(DisasContext)'
> in "translate.h" (this patch). The result was less trivial to
> review, so I went back to using an intermediate patch for
> simplicity.
>
> Is that what you were thinking about?
Yes, exactly that.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2020-12-09 15:26 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-08 0:36 [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 01/17] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 02/17] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 03/17] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 04/17] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 05/17] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 08/17] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 09/17] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 10/17] target/mips: Rename msa_helper.c as mod-msa_helper.c Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c Philippe Mathieu-Daudé
2020-12-08 23:55 ` Richard Henderson
2020-12-08 0:36 ` [PATCH 12/17] target/mips: Extract MSA helpers from op_helper.c Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 13/17] target/mips: Extract MSA helper definitions Philippe Mathieu-Daudé
2020-12-08 0:36 ` [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h' Philippe Mathieu-Daudé
2020-12-08 23:56 ` Richard Henderson
2020-12-09 0:01 ` Richard Henderson
2020-12-09 0:03 ` Richard Henderson
2020-12-09 9:17 ` Philippe Mathieu-Daudé
2020-12-09 15:25 ` Richard Henderson
2020-12-08 0:37 ` [PATCH 16/17] target/mips: Introduce decode tree bindings for MSA opcodes Philippe Mathieu-Daudé
2020-12-09 0:05 ` Richard Henderson
2020-12-09 4:09 ` Jiaxun Yang
2020-12-08 0:37 ` [PATCH 17/17] target/mips: Use decode_msa32() generated from decodetree Philippe Mathieu-Daudé
2020-12-09 0:06 ` Richard Henderson
2020-12-08 0:39 ` [PATCH 00/17] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
2020-12-08 16:30 ` Philippe Mathieu-Daudé
2020-12-09 4:07 ` Jiaxun Yang
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