From: Marc Zyngier <maz@kernel.org> To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>, Richard Henderson <richard.henderson@linaro.org>, kvmarm@lists.cs.columbia.edu Subject: [PATCH v2 3/5] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions Date: Sun, 1 Dec 2019 12:20:16 +0000 Message-ID: <20191201122018.25808-4-maz@kernel.org> (raw) In-Reply-To: <20191201122018.25808-1-maz@kernel.org> HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to EL2, and HCR_EL2.TID0 does the same for reads of FPSID. In order to handle this, introduce a new TCG helper function that checks for these control bits before executing the VMRC instruction. Tested with a hacked-up version of KVM/arm64 that sets the control bits for 32bit guests. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Marc Zyngier <maz@kernel.org> --- target/arm/helper-a64.h | 2 ++ target/arm/translate-vfp.inc.c | 18 +++++++++++++++--- target/arm/vfp_helper.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 3 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a915c1247f..0af44dc814 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -102,3 +102,5 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) + +DEF_HELPER_3(check_hcr_el2_trap, void, env, i32, i32) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 85c5ef897b..bf90ac0e5b 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -761,13 +761,25 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) if (a->l) { /* VMRS, move VFP special register to gp register */ switch (a->reg) { + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + case ARM_VFP_MVFR2: case ARM_VFP_FPSID: + if (s->current_el == 1) { + TCGv_i32 tcg_reg, tcg_rt; + + gen_set_condexec(s); + gen_set_pc_im(s, s->pc_curr); + tcg_reg = tcg_const_i32(a->reg); + tcg_rt = tcg_const_i32(a->rt); + gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg); + tcg_temp_free_i32(tcg_reg); + tcg_temp_free_i32(tcg_rt); + } + /* fall through */ case ARM_VFP_FPEXC: case ARM_VFP_FPINST: case ARM_VFP_FPINST2: - case ARM_VFP_MVFR0: - case ARM_VFP_MVFR1: - case ARM_VFP_MVFR2: tmp = load_cpu_field(vfp.xregs[a->reg]); break; case ARM_VFP_FPSCR: diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 9710ef1c3e..0ae7d4f34a 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -1322,4 +1322,33 @@ float64 HELPER(frint64_d)(float64 f, void *fpst) return frint_d(f, fpst, 64); } +void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg) +{ + uint32_t syndrome; + + switch (reg) { + case ARM_VFP_MVFR0: + case ARM_VFP_MVFR1: + case ARM_VFP_MVFR2: + if (!(arm_hcr_el2_eff(env) & HCR_TID3)) { + return; + } + break; + case ARM_VFP_FPSID: + if (!(arm_hcr_el2_eff(env) & HCR_TID0)) { + return; + } + break; + default: + g_assert_not_reached(); + } + + syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT) + | ARM_EL_IL + | (1 << 24) | (0xe << 20) | (7 << 14) + | (reg << 10) | (rt << 5) | 1); + + raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); +} + #endif -- 2.20.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply index Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-01 12:20 [PATCH v2 0/5] target/arm: More EL2 trapping fixes Marc Zyngier 2019-12-01 12:20 ` [PATCH v2 1/5] target/arm: Honor HCR_EL2.TID2 trapping requirements Marc Zyngier 2019-12-02 13:52 ` Edgar E. Iglesias 2019-12-02 15:10 ` Richard Henderson 2019-12-01 12:20 ` [PATCH v2 2/5] target/arm: Honor HCR_EL2.TID1 " Marc Zyngier 2019-12-02 15:22 ` Richard Henderson 2019-12-01 12:20 ` Marc Zyngier [this message] 2019-12-02 15:35 ` [PATCH v2 3/5] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions Richard Henderson 2019-12-02 16:45 ` Marc Zyngier 2019-12-02 16:56 ` Richard Henderson 2019-12-02 17:15 ` Marc Zyngier 2019-12-06 14:08 ` Peter Maydell 2019-12-06 14:14 ` Marc Zyngier 2019-12-06 17:45 ` Richard Henderson 2019-12-01 12:20 ` [PATCH v2 4/5] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 Marc Zyngier 2019-12-02 15:52 ` Richard Henderson 2019-12-01 12:20 ` [PATCH v2 5/5] target/arm: Add support for missing Jazelle system registers Marc Zyngier 2019-12-02 14:07 ` Edgar E. Iglesias 2019-12-02 15:57 ` Richard Henderson 2019-12-06 13:56 ` Peter Maydell 2019-12-06 14:13 ` [PATCH v2 0/5] target/arm: More EL2 trapping fixes Peter Maydell 2019-12-06 14:19 ` Marc Zyngier
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