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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Marc Zyngier <maz@kernel.org>
Cc: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v2 5/5] target/arm: Add support for missing Jazelle system registers
Date: Mon, 2 Dec 2019 15:07:00 +0100
Message-ID: <20191202140700.GF25295@toto> (raw)
In-Reply-To: <20191201122018.25808-6-maz@kernel.org>

On Sun, Dec 01, 2019 at 12:20:18PM +0000, Marc Zyngier wrote:
> QEMU lacks the minimum Jazelle implementation that is required
> by the architecture (everything is RAZ or RAZ/WI). Add it
> together with the HCR_EL2.TID0 trapping that goes with it.


Looks good to me:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>


> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  target/arm/helper.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 0ba08d550a..d6fc198a97 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6040,6 +6040,16 @@ static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
>      return CP_ACCESS_OK;
>  }
>  
> +static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri,
> +                                     bool isread)
> +{
> +    if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) {
> +        return CP_ACCESS_TRAP_EL2;
> +    }
> +
> +    return CP_ACCESS_OK;
> +}
> +
>  void register_cp_regs_for_features(ARMCPU *cpu)
>  {
>      /* Register all the coprocessor registers based on feature bits */
> @@ -6057,6 +6067,23 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>          define_arm_cp_regs(cpu, not_v8_cp_reginfo);
>      }
>  
> +    if (cpu_isar_feature(jazelle, cpu)) {
> +        ARMCPRegInfo jazelle_regs[] = {
> +            { .name = "JIDR",
> +              .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0,
> +              .access = PL1_R, .accessfn = access_jazelle,
> +              .type = ARM_CP_CONST, .resetvalue = 0 },
> +            { .name = "JOSCR",
> +              .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0,
> +              .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +            { .name = "JMCR",
> +              .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
> +              .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +            REGINFO_SENTINEL
> +        };
> +
> +        define_arm_cp_regs(cpu, jazelle_regs);
> +    }
>      if (arm_feature(env, ARM_FEATURE_V6)) {
>          /* The ID registers all have impdef reset values */
>          ARMCPRegInfo v6_idregs[] = {
> -- 
> 2.20.1
> 
> 
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Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-01 12:20 [PATCH v2 0/5] target/arm: More EL2 trapping fixes Marc Zyngier
2019-12-01 12:20 ` [PATCH v2 1/5] target/arm: Honor HCR_EL2.TID2 trapping requirements Marc Zyngier
2019-12-02 13:52   ` Edgar E. Iglesias
2019-12-02 15:10   ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 2/5] target/arm: Honor HCR_EL2.TID1 " Marc Zyngier
2019-12-02 15:22   ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 3/5] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions Marc Zyngier
2019-12-02 15:35   ` Richard Henderson
2019-12-02 16:45     ` Marc Zyngier
2019-12-02 16:56       ` Richard Henderson
2019-12-02 17:15         ` Marc Zyngier
2019-12-06 14:08   ` Peter Maydell
2019-12-06 14:14     ` Marc Zyngier
2019-12-06 17:45     ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 4/5] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 Marc Zyngier
2019-12-02 15:52   ` Richard Henderson
2019-12-01 12:20 ` [PATCH v2 5/5] target/arm: Add support for missing Jazelle system registers Marc Zyngier
2019-12-02 14:07   ` Edgar E. Iglesias [this message]
2019-12-02 15:57   ` Richard Henderson
2019-12-06 13:56     ` Peter Maydell
2019-12-06 14:13 ` [PATCH v2 0/5] target/arm: More EL2 trapping fixes Peter Maydell
2019-12-06 14:19   ` Marc Zyngier

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