From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> To: Marc Zyngier <maz@kernel.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>, Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu Subject: Re: [PATCH v2 1/5] target/arm: Honor HCR_EL2.TID2 trapping requirements Date: Mon, 2 Dec 2019 14:52:18 +0100 Message-ID: <20191202135218.GE25295@toto> (raw) In-Reply-To: <20191201122018.25808-2-maz@kernel.org> On Sun, Dec 01, 2019 at 12:20:14PM +0000, Marc Zyngier wrote: > HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1, > CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU > completely ignores it, making it impossible for hypervisors to > virtualize the cache hierarchy. > > Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > target/arm/helper.c | 31 +++++++++++++++++++++++++++---- > 1 file changed, 27 insertions(+), 4 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0bf8f53d4b..1e546096b8 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -1910,6 +1910,17 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > raw_write(env, ri, value); > } > > +static CPAccessResult access_aa64_tid2(CPUARMState *env, > + const ARMCPRegInfo *ri, > + bool isread) > +{ > + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) { > + return CP_ACCESS_TRAP_EL2; > + } > + > + return CP_ACCESS_OK; > +} > + > static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) > { > ARMCPU *cpu = env_archcpu(env); > @@ -2110,10 +2121,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { > .writefn = pmintenclr_write }, > { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, > - .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, > + .access = PL1_R, > + .accessfn = access_aa64_tid2, > + .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, > { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, > - .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, > + .access = PL1_RW, > + .accessfn = access_aa64_tid2, > + .writefn = csselr_write, .resetvalue = 0, > .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), > offsetof(CPUARMState, cp15.csselr_ns) } }, > /* Auxiliary ID register: this actually has an IMPDEF value but for now > @@ -5204,6 +5219,11 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, > if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { > return CP_ACCESS_TRAP; > } > + > + if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { > + return CP_ACCESS_TRAP_EL2; > + } > + > return CP_ACCESS_OK; > } > > @@ -6184,7 +6204,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) > ARMCPRegInfo clidr = { > .name = "CLIDR", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, > - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr > + .access = PL1_R, .type = ARM_CP_CONST, > + .accessfn = access_aa64_tid2, > + .resetvalue = cpu->clidr > }; > define_one_arm_cp_reg(cpu, &clidr); > define_arm_cp_regs(cpu, v7_cp_reginfo); > @@ -6717,7 +6739,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) > /* These are common to v8 and pre-v8 */ > { .name = "CTR", > .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, > - .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, > + .access = PL1_R, .accessfn = ctr_el0_access, > + .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, > { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, > .access = PL0_R, .accessfn = ctr_el0_access, > -- > 2.20.1 > > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply index Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-12-01 12:20 [PATCH v2 0/5] target/arm: More EL2 trapping fixes Marc Zyngier 2019-12-01 12:20 ` [PATCH v2 1/5] target/arm: Honor HCR_EL2.TID2 trapping requirements Marc Zyngier 2019-12-02 13:52 ` Edgar E. Iglesias [this message] 2019-12-02 15:10 ` Richard Henderson 2019-12-01 12:20 ` [PATCH v2 2/5] target/arm: Honor HCR_EL2.TID1 " Marc Zyngier 2019-12-02 15:22 ` Richard Henderson 2019-12-01 12:20 ` [PATCH v2 3/5] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions Marc Zyngier 2019-12-02 15:35 ` Richard Henderson 2019-12-02 16:45 ` Marc Zyngier 2019-12-02 16:56 ` Richard Henderson 2019-12-02 17:15 ` Marc Zyngier 2019-12-06 14:08 ` Peter Maydell 2019-12-06 14:14 ` Marc Zyngier 2019-12-06 17:45 ` Richard Henderson 2019-12-01 12:20 ` [PATCH v2 4/5] target/arm: Handle AArch32 CP15 trapping via HSTR_EL2 Marc Zyngier 2019-12-02 15:52 ` Richard Henderson 2019-12-01 12:20 ` [PATCH v2 5/5] target/arm: Add support for missing Jazelle system registers Marc Zyngier 2019-12-02 14:07 ` Edgar E. Iglesias 2019-12-02 15:57 ` Richard Henderson 2019-12-06 13:56 ` Peter Maydell 2019-12-06 14:13 ` [PATCH v2 0/5] target/arm: More EL2 trapping fixes Peter Maydell 2019-12-06 14:19 ` Marc Zyngier
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20191202135218.GE25295@toto \ --to=edgar.iglesias@gmail.com \ --cc=edgar.iglesias@xilinx.com \ --cc=kvmarm@lists.cs.columbia.edu \ --cc=maz@kernel.org \ --cc=qemu-devel@nongnu.org \ --cc=richard.henderson@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
KVM ARM Archive on lore.kernel.org Archives are clonable: git clone --mirror https://lore.kernel.org/kvmarm/0 kvmarm/git/0.git # If you have public-inbox 1.1+ installed, you may # initialize and index your mirror using the following commands: public-inbox-init -V2 kvmarm kvmarm/ https://lore.kernel.org/kvmarm \ kvmarm@lists.cs.columbia.edu public-inbox-index kvmarm Example config snippet for mirrors Newsgroup available over NNTP: nntp://nntp.lore.kernel.org/edu.columbia.cs.lists.kvmarm AGPL code for this site: git clone https://public-inbox.org/public-inbox.git