* [kvm-unit-tests PATCH 01/16] libcflat: Add other size defines
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2020-01-07 7:35 ` Thomas Huth
2019-12-16 14:02 ` [kvm-unit-tests PATCH 02/16] arm: gic: Provide per-IRQ helper functions Eric Auger
` (14 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Introduce additional SZ_256, SZ_8K, SZ_16K macros that will
be used by ITS tests.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
lib/libcflat.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index ea19f61..7092af2 100644
--- a/lib/libcflat.h
+++ b/lib/libcflat.h
@@ -36,7 +36,10 @@
#define ALIGN(x, a) __ALIGN((x), (a))
#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
+#define SZ_256 (1 << 8)
#define SZ_4K (1 << 12)
+#define SZ_8K (1 << 13)
+#define SZ_16K (1 << 14)
#define SZ_64K (1 << 16)
#define SZ_2M (1 << 21)
#define SZ_1G (1 << 30)
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 01/16] libcflat: Add other size defines
2019-12-16 14:02 ` [kvm-unit-tests PATCH 01/16] libcflat: Add other size defines Eric Auger
@ 2020-01-07 7:35 ` Thomas Huth
0 siblings, 0 replies; 28+ messages in thread
From: Thomas Huth @ 2020-01-07 7:35 UTC (permalink / raw)
To: Eric Auger, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara
On 16/12/2019 15.02, Eric Auger wrote:
> Introduce additional SZ_256, SZ_8K, SZ_16K macros that will
> be used by ITS tests.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> ---
> lib/libcflat.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/lib/libcflat.h b/lib/libcflat.h
> index ea19f61..7092af2 100644
> --- a/lib/libcflat.h
> +++ b/lib/libcflat.h
> @@ -36,7 +36,10 @@
> #define ALIGN(x, a) __ALIGN((x), (a))
> #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
>
> +#define SZ_256 (1 << 8)
> #define SZ_4K (1 << 12)
> +#define SZ_8K (1 << 13)
> +#define SZ_16K (1 << 14)
> #define SZ_64K (1 << 16)
> #define SZ_2M (1 << 21)
> #define SZ_1G (1 << 30)
>
Reviewed-by: Thomas Huth <thuth@redhat.com>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [kvm-unit-tests PATCH 02/16] arm: gic: Provide per-IRQ helper functions
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 01/16] libcflat: Add other size defines Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 03/16] arm/arm64: gic: Introduce setup_irq() helper Eric Auger
` (13 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
From: Andre Przywara <andre.przywara@arm.com>
A common theme when accessing per-IRQ parameters in the GIC distributor
is to set fields of a certain bit width in a range of MMIO registers.
Examples are the enabled status (one bit per IRQ), the level/edge
configuration (2 bits per IRQ) or the priority (8 bits per IRQ).
Add a generic helper function which is able to mask and set the
respective number of bits, given the IRQ number and the MMIO offset.
Provide wrappers using this function to easily allow configuring an IRQ.
For now assume that private IRQ numbers always refer to the current CPU.
In a GICv2 accessing the "other" private IRQs is not easily doable (the
registers are banked per CPU on the same MMIO address), so we impose the
same limitation on GICv3, even though those registers are not banked
there anymore.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
initialize reg
---
lib/arm/asm/gic-v3.h | 2 +
lib/arm/asm/gic.h | 9 +++++
lib/arm/gic.c | 90 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 101 insertions(+)
diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
index 347be2f..4a445a5 100644
--- a/lib/arm/asm/gic-v3.h
+++ b/lib/arm/asm/gic-v3.h
@@ -23,6 +23,8 @@
#define GICD_CTLR_ENABLE_G1A (1U << 1)
#define GICD_CTLR_ENABLE_G1 (1U << 0)
+#define GICD_IROUTER 0x6000
+
/* Re-Distributor registers, offsets from RD_base */
#define GICR_TYPER 0x0008
diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
index 1fc10a0..21cdb58 100644
--- a/lib/arm/asm/gic.h
+++ b/lib/arm/asm/gic.h
@@ -15,6 +15,7 @@
#define GICD_IIDR 0x0008
#define GICD_IGROUPR 0x0080
#define GICD_ISENABLER 0x0100
+#define GICD_ICENABLER 0x0180
#define GICD_ISPENDR 0x0200
#define GICD_ICPENDR 0x0280
#define GICD_ISACTIVER 0x0300
@@ -73,5 +74,13 @@ extern void gic_write_eoir(u32 irqstat);
extern void gic_ipi_send_single(int irq, int cpu);
extern void gic_ipi_send_mask(int irq, const cpumask_t *dest);
+void gic_set_irq_bit(int irq, int offset);
+void gic_enable_irq(int irq);
+void gic_disable_irq(int irq);
+void gic_set_irq_priority(int irq, u8 prio);
+void gic_set_irq_target(int irq, int cpu);
+void gic_set_irq_group(int irq, int group);
+int gic_get_irq_group(int irq);
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASMARM_GIC_H_ */
diff --git a/lib/arm/gic.c b/lib/arm/gic.c
index 9430116..aa9cb86 100644
--- a/lib/arm/gic.c
+++ b/lib/arm/gic.c
@@ -146,3 +146,93 @@ void gic_ipi_send_mask(int irq, const cpumask_t *dest)
assert(gic_common_ops && gic_common_ops->ipi_send_mask);
gic_common_ops->ipi_send_mask(irq, dest);
}
+
+enum gic_bit_access {
+ ACCESS_READ,
+ ACCESS_SET,
+ ACCESS_RMW
+};
+
+static u8 gic_masked_irq_bits(int irq, int offset, int bits, u8 value,
+ enum gic_bit_access access)
+{
+ void *base;
+ int split = 32 / bits;
+ int shift = (irq % split) * bits;
+ u32 reg = 0, mask = ((1U << bits) - 1) << shift;
+
+ switch (gic_version()) {
+ case 2:
+ base = gicv2_dist_base();
+ break;
+ case 3:
+ if (irq < 32)
+ base = gicv3_sgi_base();
+ else
+ base = gicv3_dist_base();
+ break;
+ default:
+ return 0;
+ }
+ base += offset + (irq / split) * 4;
+
+ switch (access) {
+ case ACCESS_READ:
+ return (readl(base) & mask) >> shift;
+ case ACCESS_SET:
+ reg = 0;
+ break;
+ case ACCESS_RMW:
+ reg = readl(base) & ~mask;
+ break;
+ }
+
+ writel(reg | ((u32)value << shift), base);
+
+ return 0;
+}
+
+void gic_set_irq_bit(int irq, int offset)
+{
+ gic_masked_irq_bits(irq, offset, 1, 1, ACCESS_SET);
+}
+
+void gic_enable_irq(int irq)
+{
+ gic_set_irq_bit(irq, GICD_ISENABLER);
+}
+
+void gic_disable_irq(int irq)
+{
+ gic_set_irq_bit(irq, GICD_ICENABLER);
+}
+
+void gic_set_irq_priority(int irq, u8 prio)
+{
+ gic_masked_irq_bits(irq, GICD_IPRIORITYR, 8, prio, ACCESS_RMW);
+}
+
+void gic_set_irq_target(int irq, int cpu)
+{
+ if (irq < 32)
+ return;
+
+ if (gic_version() == 2) {
+ gic_masked_irq_bits(irq, GICD_ITARGETSR, 8, 1U << cpu,
+ ACCESS_RMW);
+
+ return;
+ }
+
+ writeq(cpus[cpu], gicv3_dist_base() + GICD_IROUTER + irq * 8);
+}
+
+void gic_set_irq_group(int irq, int group)
+{
+ gic_masked_irq_bits(irq, GICD_IGROUPR, 1, group, ACCESS_RMW);
+}
+
+int gic_get_irq_group(int irq)
+{
+ return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ);
+}
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* [kvm-unit-tests PATCH 03/16] arm/arm64: gic: Introduce setup_irq() helper
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 01/16] libcflat: Add other size defines Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 02/16] arm: gic: Provide per-IRQ helper functions Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 04/16] arm/arm64: gicv3: Add some re-distributor defines Eric Auger
` (12 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
ipi_enable() code would be reusable for other interrupts
than IPI. Let's rename it setup_irq() and pass an interrupt
handler pointer. We also export it to use it in other tests
such as the PMU's one.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
arm/gic.c | 24 +++---------------------
lib/arm/asm/gic.h | 3 +++
lib/arm/gic.c | 11 +++++++++++
3 files changed, 17 insertions(+), 21 deletions(-)
diff --git a/arm/gic.c b/arm/gic.c
index fcf4c1f..ba43ae5 100644
--- a/arm/gic.c
+++ b/arm/gic.c
@@ -215,20 +215,9 @@ static void ipi_test_smp(void)
report_prefix_pop();
}
-static void ipi_enable(void)
-{
- gic_enable_defaults();
-#ifdef __arm__
- install_exception_handler(EXCPTN_IRQ, ipi_handler);
-#else
- install_irq_handler(EL1H_IRQ, ipi_handler);
-#endif
- local_irq_enable();
-}
-
static void ipi_send(void)
{
- ipi_enable();
+ setup_irq(ipi_handler);
wait_on_ready();
ipi_test_self();
ipi_test_smp();
@@ -238,7 +227,7 @@ static void ipi_send(void)
static void ipi_recv(void)
{
- ipi_enable();
+ setup_irq(ipi_handler);
cpumask_set_cpu(smp_processor_id(), &ready);
while (1)
wfi();
@@ -295,14 +284,7 @@ static void ipi_clear_active_handler(struct pt_regs *regs __unused)
static void run_active_clear_test(void)
{
report_prefix_push("active");
- gic_enable_defaults();
-#ifdef __arm__
- install_exception_handler(EXCPTN_IRQ, ipi_clear_active_handler);
-#else
- install_irq_handler(EL1H_IRQ, ipi_clear_active_handler);
-#endif
- local_irq_enable();
-
+ setup_irq(ipi_clear_active_handler);
ipi_test_self();
report_prefix_pop();
}
diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
index 21cdb58..55dd84b 100644
--- a/lib/arm/asm/gic.h
+++ b/lib/arm/asm/gic.h
@@ -82,5 +82,8 @@ void gic_set_irq_target(int irq, int cpu);
void gic_set_irq_group(int irq, int group);
int gic_get_irq_group(int irq);
+typedef void (*handler_t)(struct pt_regs *regs __unused);
+extern void setup_irq(handler_t handler);
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASMARM_GIC_H_ */
diff --git a/lib/arm/gic.c b/lib/arm/gic.c
index aa9cb86..8416dde 100644
--- a/lib/arm/gic.c
+++ b/lib/arm/gic.c
@@ -236,3 +236,14 @@ int gic_get_irq_group(int irq)
{
return gic_masked_irq_bits(irq, GICD_IGROUPR, 1, 0, ACCESS_READ);
}
+
+void setup_irq(handler_t handler)
+{
+ gic_enable_defaults();
+#ifdef __arm__
+ install_exception_handler(EXCPTN_IRQ, handler);
+#else
+ install_irq_handler(EL1H_IRQ, handler);
+#endif
+ local_irq_enable();
+}
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* [kvm-unit-tests PATCH 04/16] arm/arm64: gicv3: Add some re-distributor defines
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (2 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 03/16] arm/arm64: gic: Introduce setup_irq() helper Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests Eric Auger
` (11 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
PROPBASER, PENDBASE and GICR_CTRL will be used for LPI management.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
lib/arm/asm/gic-v3.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
index 4a445a5..d02f4a4 100644
--- a/lib/arm/asm/gic-v3.h
+++ b/lib/arm/asm/gic-v3.h
@@ -18,6 +18,7 @@
* We expect to be run in Non-secure mode, thus we define the
* group1 enable bits with respect to that view.
*/
+#define GICD_CTLR 0x0000
#define GICD_CTLR_RWP (1U << 31)
#define GICD_CTLR_ARE_NS (1U << 4)
#define GICD_CTLR_ENABLE_G1A (1U << 1)
@@ -35,6 +36,11 @@
#define GICR_ISENABLER0 GICD_ISENABLER
#define GICR_IPRIORITYR0 GICD_IPRIORITYR
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
+#define GICR_CTLR GICD_CTLR
+#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
+
#define ICC_SGI1R_AFFINITY_1_SHIFT 16
#define ICC_SGI1R_AFFINITY_2_SHIFT 32
#define ICC_SGI1R_AFFINITY_3_SHIFT 48
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (3 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 04/16] arm/arm64: gicv3: Add some re-distributor defines Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-18 3:46 ` Zenghui Yu
2019-12-16 14:02 ` [kvm-unit-tests PATCH 06/16] arm/arm64: ITS: Test BASER Eric Auger
` (10 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Detect the presence of an ITS as part of the GICv3 init
routine, initialize its base address and read few registers
the IIDR, the TYPER to store its dimensioning parameters.
This is our first ITS test, belonging to a new "its" group.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
arm/Makefile.common | 1 +
arm/gic.c | 34 +++++++++++
arm/unittests.cfg | 6 ++
lib/arm/asm/gic-v3-its.h | 116 +++++++++++++++++++++++++++++++++++++
lib/arm/asm/gic.h | 1 +
lib/arm/gic-v3-its.c | 41 +++++++++++++
lib/arm/gic.c | 31 ++++++++--
lib/arm64/asm/gic-v3-its.h | 1 +
8 files changed, 226 insertions(+), 5 deletions(-)
create mode 100644 lib/arm/asm/gic-v3-its.h
create mode 100644 lib/arm/gic-v3-its.c
create mode 100644 lib/arm64/asm/gic-v3-its.h
diff --git a/arm/Makefile.common b/arm/Makefile.common
index b8988f2..1aae5a3 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -52,6 +52,7 @@ cflatobjs += lib/arm/psci.o
cflatobjs += lib/arm/smp.o
cflatobjs += lib/arm/delay.o
cflatobjs += lib/arm/gic.o lib/arm/gic-v2.o lib/arm/gic-v3.o
+cflatobjs += lib/arm/gic-v3-its.o
OBJDIRS += lib/arm
diff --git a/arm/gic.c b/arm/gic.c
index ba43ae5..adeb981 100644
--- a/arm/gic.c
+++ b/arm/gic.c
@@ -506,6 +506,36 @@ static void gic_test_mmio(void)
test_targets(nr_irqs);
}
+static void test_its_introspection(void)
+{
+ struct its_typer *typer = &its_data.typer;
+
+ if (!gicv3_its_base()) {
+ report_skip("No ITS, skip ...");
+ return;
+ }
+
+ /* IIDR */
+ report(test_readonly_32(gicv3_its_base() + GITS_IIDR, false),
+ "GITS_IIDR is read-only"),
+
+ /* TYPER */
+ report(test_readonly_32(gicv3_its_base() + GITS_TYPER, false),
+ "GITS_TYPER is read-only");
+
+ report(typer->phys_lpi, "ITS supports physical LPIs");
+ report_info("vLPI support: %s", typer->virt_lpi ? "yes" : "no");
+ report_info("ITT entry size = 0x%x", typer->ite_size);
+ report_info("Bit Count: EventID=%d DeviceId=%d CollId=%d",
+ typer->eventid_bits, typer->deviceid_bits,
+ typer->collid_bits);
+ report(typer->eventid_bits && typer->deviceid_bits &&
+ typer->collid_bits, "ID spaces");
+ report(!typer->hw_collections, "collections only in ext memory");
+ report_info("Target address format %s",
+ typer->pta ? "Redist basse address" : "PE #");
+}
+
int main(int argc, char **argv)
{
if (!gic_init()) {
@@ -537,6 +567,10 @@ int main(int argc, char **argv)
report_prefix_push(argv[1]);
gic_test_mmio();
report_prefix_pop();
+ } else if (strcmp(argv[1], "its-introspection") == 0) {
+ report_prefix_push(argv[1]);
+ test_its_introspection();
+ report_prefix_pop();
} else {
report_abort("Unknown subtest '%s'", argv[1]);
}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index daeb5a0..bd20460 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -122,6 +122,12 @@ smp = $MAX_SMP
extra_params = -machine gic-version=3 -append 'active'
groups = gic
+[its-introspection]
+file = gic.flat
+smp = $MAX_SMP
+extra_params = -machine gic-version=3 -append 'its-introspection'
+groups = its
+
# Test PSCI emulation
[psci]
file = psci.flat
diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
new file mode 100644
index 0000000..2ce483e
--- /dev/null
+++ b/lib/arm/asm/gic-v3-its.h
@@ -0,0 +1,116 @@
+/*
+ * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h
+ *
+ * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#ifndef _ASMARM_GIC_V3_ITS_H_
+#define _ASMARM_GIC_V3_ITS_H_
+
+#ifndef __ASSEMBLY__
+
+#define GITS_CTLR 0x0000
+#define GITS_IIDR 0x0004
+#define GITS_TYPER 0x0008
+#define GITS_CBASER 0x0080
+#define GITS_CWRITER 0x0088
+#define GITS_CREADR 0x0090
+#define GITS_BASER 0x0100
+
+#define GITS_TYPER_PLPIS (1UL << 0)
+#define GITS_TYPER_IDBITS_SHIFT 8
+#define GITS_TYPER_DEVBITS_SHIFT 13
+#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
+#define GITS_TYPER_PTA (1UL << 19)
+#define GITS_TYPER_HWCOLLCNT_SHIFT 24
+
+#define GITS_CTLR_ENABLE (1U << 0)
+
+#define GITS_CBASER_VALID (1UL << 63)
+#define GITS_CBASER_SHAREABILITY_SHIFT (10)
+#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
+#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
+#define GITS_CBASER_SHAREABILITY_MASK \
+ GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
+#define GITS_CBASER_INNER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
+#define GITS_CBASER_OUTER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
+#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
+
+#define GITS_CBASER_InnerShareable \
+ GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
+
+#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
+#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
+#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
+#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
+#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
+#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
+#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
+#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
+
+#define GITS_BASER_NR_REGS 8
+
+#define GITS_BASER_VALID (1UL << 63)
+#define GITS_BASER_INDIRECT (1ULL << 62)
+
+#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
+#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
+#define GITS_BASER_CACHEABILITY_MASK 0x7
+
+#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
+
+#define GITS_BASER_TYPE_SHIFT (56)
+#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
+#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
+#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
+#define GITS_BASER_SHAREABILITY_SHIFT (10)
+#define GITS_BASER_InnerShareable \
+ GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
+#define GITS_BASER_PAGE_SIZE_SHIFT (8)
+#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGES_MAX 256
+#define GITS_BASER_PAGES_SHIFT (0)
+#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
+#define GITS_BASER_PHYS_ADDR_MASK 0xFFFFFFFFF000
+
+#define GITS_BASER_TYPE_NONE 0
+#define GITS_BASER_TYPE_DEVICE 1
+#define GITS_BASER_TYPE_VCPU 2
+#define GITS_BASER_TYPE_CPU 3
+#define GITS_BASER_TYPE_COLLECTION 4
+
+#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
+
+struct its_typer {
+ unsigned int ite_size;
+ unsigned int eventid_bits;
+ unsigned int deviceid_bits;
+ unsigned int collid_bits;
+ unsigned int hw_collections;
+ bool pta;
+ bool cil;
+ bool cct;
+ bool phys_lpi;
+ bool virt_lpi;
+};
+
+struct its_data {
+ void *base;
+ struct its_typer typer;
+};
+
+extern struct its_data its_data;
+
+#define gicv3_its_base() (its_data.base)
+
+extern void its_parse_typer(void);
+extern void its_init(void);
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASMARM_GIC_V3_ITS_H_ */
diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
index 55dd84b..b44da9c 100644
--- a/lib/arm/asm/gic.h
+++ b/lib/arm/asm/gic.h
@@ -40,6 +40,7 @@
#include <asm/gic-v2.h>
#include <asm/gic-v3.h>
+#include <asm/gic-v3-its.h>
#define PPI(irq) ((irq) + 16)
#define SPI(irq) ((irq) + GIC_FIRST_SPI)
diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
new file mode 100644
index 0000000..34f4d0e
--- /dev/null
+++ b/lib/arm/gic-v3-its.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2016, Red Hat Inc, Eric Auger <eric.auger@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include <asm/gic.h>
+
+struct its_data its_data;
+
+void its_parse_typer(void)
+{
+ u64 typer = readq(gicv3_its_base() + GITS_TYPER);
+
+ its_data.typer.ite_size = ((typer >> 4) & 0xf) + 1;
+ its_data.typer.pta = typer & GITS_TYPER_PTA;
+ its_data.typer.eventid_bits =
+ ((typer >> GITS_TYPER_IDBITS_SHIFT) & 0x1f) + 1;
+ its_data.typer.deviceid_bits = GITS_TYPER_DEVBITS(typer) + 1;
+
+ its_data.typer.cil = (typer >> 36) & 0x1;
+ if (its_data.typer.cil)
+ its_data.typer.collid_bits = ((typer >> 32) & 0xf) + 1;
+ else
+ its_data.typer.collid_bits = 16;
+
+ its_data.typer.hw_collections =
+ (typer >> GITS_TYPER_HWCOLLCNT_SHIFT) & 0xff;
+
+ its_data.typer.cct = typer & 0x4;
+ its_data.typer.virt_lpi = typer & 0x2;
+ its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS;
+}
+
+void its_init(void)
+{
+ if (!its_data.base)
+ return;
+
+ its_parse_typer();
+}
+
diff --git a/lib/arm/gic.c b/lib/arm/gic.c
index 8416dde..f9a6f57 100644
--- a/lib/arm/gic.c
+++ b/lib/arm/gic.c
@@ -6,6 +6,7 @@
#include <devicetree.h>
#include <asm/gic.h>
#include <asm/io.h>
+#include <asm/gic-v3-its.h>
struct gicv2_data gicv2_data;
struct gicv3_data gicv3_data;
@@ -44,12 +45,14 @@ static const struct gic_common_ops gicv3_common_ops = {
* Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
*/
static bool
-gic_get_dt_bases(const char *compatible, void **base1, void **base2)
+gic_get_dt_bases(const char *compatible, void **base1, void **base2,
+ void **base3)
{
struct dt_pbus_reg reg;
- struct dt_device gic;
+ struct dt_device gic, its;
struct dt_bus bus;
- int node, ret, i;
+ int node, subnode, ret, i, len;
+ const void *fdt = dt_fdt();
dt_bus_init_defaults(&bus);
dt_device_init(&gic, &bus, NULL);
@@ -74,19 +77,36 @@ gic_get_dt_bases(const char *compatible, void **base1, void **base2)
base2[i] = ioremap(reg.addr, reg.size);
}
+ if (base3 && !strcmp(compatible, "arm,gic-v3")) {
+ dt_for_each_subnode(node, subnode) {
+ const struct fdt_property *prop;
+
+ prop = fdt_get_property(fdt, subnode,
+ "compatible", &len);
+ if (!strcmp((char *)prop->data, "arm,gic-v3-its")) {
+ dt_device_bind_node(&its, subnode);
+ ret = dt_pbus_translate(&its, 0, ®);
+ assert(ret == 0);
+ *base3 = ioremap(reg.addr, reg.size);
+ break;
+ }
+ }
+
+ }
+
return true;
}
int gicv2_init(void)
{
return gic_get_dt_bases("arm,cortex-a15-gic",
- &gicv2_data.dist_base, &gicv2_data.cpu_base);
+ &gicv2_data.dist_base, &gicv2_data.cpu_base, NULL);
}
int gicv3_init(void)
{
return gic_get_dt_bases("arm,gic-v3", &gicv3_data.dist_base,
- &gicv3_data.redist_bases[0]);
+ &gicv3_data.redist_bases[0], &its_data.base);
}
int gic_version(void)
@@ -104,6 +124,7 @@ int gic_init(void)
gic_common_ops = &gicv2_common_ops;
else if (gicv3_init())
gic_common_ops = &gicv3_common_ops;
+ its_init();
return gic_version();
}
diff --git a/lib/arm64/asm/gic-v3-its.h b/lib/arm64/asm/gic-v3-its.h
new file mode 100644
index 0000000..083cba4
--- /dev/null
+++ b/lib/arm64/asm/gic-v3-its.h
@@ -0,0 +1 @@
+#include "../../arm/asm/gic-v3-its.h"
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests
2019-12-16 14:02 ` [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests Eric Auger
@ 2019-12-18 3:46 ` Zenghui Yu
2019-12-18 8:34 ` Auger Eric
0 siblings, 1 reply; 28+ messages in thread
From: Zenghui Yu @ 2019-12-18 3:46 UTC (permalink / raw)
To: Eric Auger, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Hi Eric,
I have to admit that this is the first time I've looked into
the kvm-unit-tests code, so only some minor comments inline :)
On 2019/12/16 22:02, Eric Auger wrote:
> Detect the presence of an ITS as part of the GICv3 init
> routine, initialize its base address and read few registers
> the IIDR, the TYPER to store its dimensioning parameters.
>
> This is our first ITS test, belonging to a new "its" group.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
[...]
> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
> new file mode 100644
> index 0000000..2ce483e
> --- /dev/null
> +++ b/lib/arm/asm/gic-v3-its.h
> @@ -0,0 +1,116 @@
> +/*
> + * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h
> + *
> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#ifndef _ASMARM_GIC_V3_ITS_H_
> +#define _ASMARM_GIC_V3_ITS_H_
> +
> +#ifndef __ASSEMBLY__
> +
> +#define GITS_CTLR 0x0000
> +#define GITS_IIDR 0x0004
> +#define GITS_TYPER 0x0008
> +#define GITS_CBASER 0x0080
> +#define GITS_CWRITER 0x0088
> +#define GITS_CREADR 0x0090
> +#define GITS_BASER 0x0100
> +
> +#define GITS_TYPER_PLPIS (1UL << 0)
> +#define GITS_TYPER_IDBITS_SHIFT 8
> +#define GITS_TYPER_DEVBITS_SHIFT 13
> +#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
> +#define GITS_TYPER_PTA (1UL << 19)
> +#define GITS_TYPER_HWCOLLCNT_SHIFT 24
> +
> +#define GITS_CTLR_ENABLE (1U << 0)
> +
> +#define GITS_CBASER_VALID (1UL << 63)
> +#define GITS_CBASER_SHAREABILITY_SHIFT (10)
> +#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
> +#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
> +#define GITS_CBASER_SHAREABILITY_MASK \
> + GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
> +#define GITS_CBASER_INNER_CACHEABILITY_MASK \
> + GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
> +#define GITS_CBASER_OUTER_CACHEABILITY_MASK \
> + GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
> +#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
> +
> +#define GITS_CBASER_InnerShareable \
> + GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
> +
> +#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
> +#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
> +#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
> +#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
s/RaWt/RaWb/
> +#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
> +#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
> +#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
> +#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
> +
> +#define GITS_BASER_NR_REGS 8
> +
> +#define GITS_BASER_VALID (1UL << 63)
> +#define GITS_BASER_INDIRECT (1ULL << 62)
> +
> +#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
> +#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
> +#define GITS_BASER_CACHEABILITY_MASK 0x7
> +
> +#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
> +
> +#define GITS_BASER_TYPE_SHIFT (56)
> +#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
> +#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
> +#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
> +#define GITS_BASER_SHAREABILITY_SHIFT (10)
> +#define GITS_BASER_InnerShareable \
> + GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
> +#define GITS_BASER_PAGE_SIZE_SHIFT (8)
> +#define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT)
> +#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT)
> +#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT)
> +#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT)
> +#define GITS_BASER_PAGES_MAX 256
> +#define GITS_BASER_PAGES_SHIFT (0)
> +#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
> +#define GITS_BASER_PHYS_ADDR_MASK 0xFFFFFFFFF000
> +
> +#define GITS_BASER_TYPE_NONE 0
> +#define GITS_BASER_TYPE_DEVICE 1
> +#define GITS_BASER_TYPE_VCPU 2
> +#define GITS_BASER_TYPE_CPU 3
'3' is one of the reserved values of the GITS_BASER.Type field, and
what do we expect with a "GITS_BASER_TYPE_CPU" table type? ;-)
I think we can copy (and might update in the future) all these
macros against the latest Linux kernel.
> +#define GITS_BASER_TYPE_COLLECTION 4
> +
> +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) > +
> +struct its_typer {
> + unsigned int ite_size;
> + unsigned int eventid_bits;
> + unsigned int deviceid_bits;
> + unsigned int collid_bits;
> + unsigned int hw_collections;
> + bool pta;
> + bool cil;
> + bool cct;
> + bool phys_lpi;
> + bool virt_lpi;
> +};
> +
> +struct its_data {
> + void *base;
> + struct its_typer typer;
> +};
> +
> +extern struct its_data its_data;
> +
> +#define gicv3_its_base() (its_data.base)
> +
> +extern void its_parse_typer(void);
> +extern void its_init(void);
> +
> +#endif /* !__ASSEMBLY__ */
> +#endif /* _ASMARM_GIC_V3_ITS_H_ */
> diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
> index 55dd84b..b44da9c 100644
> --- a/lib/arm/asm/gic.h
> +++ b/lib/arm/asm/gic.h
> @@ -40,6 +40,7 @@
>
> #include <asm/gic-v2.h>
> #include <asm/gic-v3.h>
> +#include <asm/gic-v3-its.h>
>
> #define PPI(irq) ((irq) + 16)
> #define SPI(irq) ((irq) + GIC_FIRST_SPI)
> diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
> new file mode 100644
> index 0000000..34f4d0e
> --- /dev/null
> +++ b/lib/arm/gic-v3-its.c
> @@ -0,0 +1,41 @@
> +/*
> + * Copyright (C) 2016, Red Hat Inc, Eric Auger <eric.auger@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include <asm/gic.h>
> +
> +struct its_data its_data;
> +
> +void its_parse_typer(void)
> +{
> + u64 typer = readq(gicv3_its_base() + GITS_TYPER);
> +
> + its_data.typer.ite_size = ((typer >> 4) & 0xf) + 1;
> + its_data.typer.pta = typer & GITS_TYPER_PTA;
> + its_data.typer.eventid_bits =
> + ((typer >> GITS_TYPER_IDBITS_SHIFT) & 0x1f) + 1;
> + its_data.typer.deviceid_bits = GITS_TYPER_DEVBITS(typer) + 1;
No need to '+1'. As GITS_TYPER_DEVBITS already helps us to calculate
the implemented DeviceID bits.
> +
> + its_data.typer.cil = (typer >> 36) & 0x1;
> + if (its_data.typer.cil)
> + its_data.typer.collid_bits = ((typer >> 32) & 0xf) + 1;
> + else
> + its_data.typer.collid_bits = 16;
> +
> + its_data.typer.hw_collections =
> + (typer >> GITS_TYPER_HWCOLLCNT_SHIFT) & 0xff;
> +
> + its_data.typer.cct = typer & 0x4;
> + its_data.typer.virt_lpi = typer & 0x2;
> + its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS;
Personally, mix using of GITS_TYPER_* macros and some magic constants to
parse the TYPER makes it a bit difficult to review the code. Maybe we
can have more such kinds of macros in the header file and get rid of all
hardcoded numbers?
Thanks,
Zenghui
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^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests
2019-12-18 3:46 ` Zenghui Yu
@ 2019-12-18 8:34 ` Auger Eric
2019-12-20 7:34 ` Zenghui Yu
0 siblings, 1 reply; 28+ messages in thread
From: Auger Eric @ 2019-12-18 8:34 UTC (permalink / raw)
To: Zenghui Yu, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Hi Zenghui,
On 12/18/19 4:46 AM, Zenghui Yu wrote:
> Hi Eric,
>
> I have to admit that this is the first time I've looked into
> the kvm-unit-tests code, so only some minor comments inline :)
no problem. Thank you for looking at this.
By the way, with patch 16 I was able to test yout fix: "KVM: arm/arm64:
vgic: Don't rely on the wrong pending table". Reverting it produced an
error. I forgot to mention that.
>
> On 2019/12/16 22:02, Eric Auger wrote:
>> Detect the presence of an ITS as part of the GICv3 init
>> routine, initialize its base address and read few registers
>> the IIDR, the TYPER to store its dimensioning parameters.
>>
>> This is our first ITS test, belonging to a new "its" group.
>>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>
> [...]
>
>> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
>> new file mode 100644
>> index 0000000..2ce483e
>> --- /dev/null
>> +++ b/lib/arm/asm/gic-v3-its.h
>> @@ -0,0 +1,116 @@
>> +/*
>> + * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h
>> + *
>> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones <drjones@redhat.com>
>> + *
>> + * This work is licensed under the terms of the GNU LGPL, version 2.
>> + */
>> +#ifndef _ASMARM_GIC_V3_ITS_H_
>> +#define _ASMARM_GIC_V3_ITS_H_
>> +
>> +#ifndef __ASSEMBLY__
>> +
>> +#define GITS_CTLR 0x0000
>> +#define GITS_IIDR 0x0004
>> +#define GITS_TYPER 0x0008
>> +#define GITS_CBASER 0x0080
>> +#define GITS_CWRITER 0x0088
>> +#define GITS_CREADR 0x0090
>> +#define GITS_BASER 0x0100
>> +
>> +#define GITS_TYPER_PLPIS (1UL << 0)
>> +#define GITS_TYPER_IDBITS_SHIFT 8
>> +#define GITS_TYPER_DEVBITS_SHIFT 13
>> +#define GITS_TYPER_DEVBITS(r) ((((r) >>
>> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
>> +#define GITS_TYPER_PTA (1UL << 19)
>> +#define GITS_TYPER_HWCOLLCNT_SHIFT 24
>> +
>> +#define GITS_CTLR_ENABLE (1U << 0)
>> +
>> +#define GITS_CBASER_VALID (1UL << 63)
>> +#define GITS_CBASER_SHAREABILITY_SHIFT (10)
>> +#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
>> +#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
>> +#define
>> GITS_CBASER_SHAREABILITY_MASK \
>> + GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
>> +#define
>> GITS_CBASER_INNER_CACHEABILITY_MASK \
>> + GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
>> +#define
>> GITS_CBASER_OUTER_CACHEABILITY_MASK \
>> + GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
>> +#define GITS_CBASER_CACHEABILITY_MASK
>> GITS_CBASER_INNER_CACHEABILITY_MASK
>> +
>> +#define
>> GITS_CBASER_InnerShareable \
>> + GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
>> +
>> +#define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER,
>> INNER, nCnB)
>> +#define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER,
>> INNER, nC)
>> +#define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER,
>> INNER, RaWt)
>> +#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER,
>> INNER, RaWt)
>
> s/RaWt/RaWb/
OK
>
>> +#define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER,
>> INNER, WaWt)
>> +#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER,
>> INNER, WaWb)
>> +#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER,
>> INNER, RaWaWt)
>> +#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER,
>> INNER, RaWaWb)
>> +
>> +#define GITS_BASER_NR_REGS 8
>> +
>> +#define GITS_BASER_VALID (1UL << 63)
>> +#define GITS_BASER_INDIRECT (1ULL << 62)
>> +
>> +#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
>> +#define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
>> +#define GITS_BASER_CACHEABILITY_MASK 0x7
>> +
>> +#define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER,
>> INNER, nCnB)
>> +
>> +#define GITS_BASER_TYPE_SHIFT (56)
>> +#define GITS_BASER_TYPE(r) (((r) >>
>> GITS_BASER_TYPE_SHIFT) & 7)
>> +#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
>> +#define GITS_BASER_ENTRY_SIZE(r) ((((r) >>
>> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
>> +#define GITS_BASER_SHAREABILITY_SHIFT (10)
>> +#define
>> GITS_BASER_InnerShareable \
>> + GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
>> +#define GITS_BASER_PAGE_SIZE_SHIFT (8)
>> +#define GITS_BASER_PAGE_SIZE_4K (0UL <<
>> GITS_BASER_PAGE_SIZE_SHIFT)
>> +#define GITS_BASER_PAGE_SIZE_16K (1UL <<
>> GITS_BASER_PAGE_SIZE_SHIFT)
>> +#define GITS_BASER_PAGE_SIZE_64K (2UL <<
>> GITS_BASER_PAGE_SIZE_SHIFT)
>> +#define GITS_BASER_PAGE_SIZE_MASK (3UL <<
>> GITS_BASER_PAGE_SIZE_SHIFT)
>> +#define GITS_BASER_PAGES_MAX 256
>> +#define GITS_BASER_PAGES_SHIFT (0)
>> +#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
>> +#define GITS_BASER_PHYS_ADDR_MASK 0xFFFFFFFFF000
>> +
>> +#define GITS_BASER_TYPE_NONE 0
>> +#define GITS_BASER_TYPE_DEVICE 1
>> +#define GITS_BASER_TYPE_VCPU 2
>> +#define GITS_BASER_TYPE_CPU 3
>
> '3' is one of the reserved values of the GITS_BASER.Type field, and
> what do we expect with a "GITS_BASER_TYPE_CPU" table type? ;-)
Yes I agree. This is code extracted from the irqchip header in Dec 2016.
I should have checked again. I only use DEVICE and COLLECTION here.
I will remove all the defines I am not using at the moment. I guess most
of the defines related to memory/cache mgt are not mandated either.
>
> I think we can copy (and might update in the future) all these
> macros against the latest Linux kernel.
>
>> +#define GITS_BASER_TYPE_COLLECTION 4
>> +
>> +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) > +
>> +struct its_typer {
>> + unsigned int ite_size;
>> + unsigned int eventid_bits;
>> + unsigned int deviceid_bits;
>> + unsigned int collid_bits;
>> + unsigned int hw_collections;
>> + bool pta;
>> + bool cil;
>> + bool cct;
>> + bool phys_lpi;
>> + bool virt_lpi;
>> +};
>> +
>> +struct its_data {
>> + void *base;
>> + struct its_typer typer;
>> +};
>> +
>> +extern struct its_data its_data;
>> +
>> +#define gicv3_its_base() (its_data.base)
>> +
>> +extern void its_parse_typer(void);
>> +extern void its_init(void);
>> +
>> +#endif /* !__ASSEMBLY__ */
>> +#endif /* _ASMARM_GIC_V3_ITS_H_ */
>> diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
>> index 55dd84b..b44da9c 100644
>> --- a/lib/arm/asm/gic.h
>> +++ b/lib/arm/asm/gic.h
>> @@ -40,6 +40,7 @@
>> #include <asm/gic-v2.h>
>> #include <asm/gic-v3.h>
>> +#include <asm/gic-v3-its.h>
>> #define PPI(irq) ((irq) + 16)
>> #define SPI(irq) ((irq) + GIC_FIRST_SPI)
>> diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
>> new file mode 100644
>> index 0000000..34f4d0e
>> --- /dev/null
>> +++ b/lib/arm/gic-v3-its.c
>> @@ -0,0 +1,41 @@
>> +/*
>> + * Copyright (C) 2016, Red Hat Inc, Eric Auger <eric.auger@redhat.com>
>> + *
>> + * This work is licensed under the terms of the GNU LGPL, version 2.
>> + */
>> +#include <asm/gic.h>
>> +
>> +struct its_data its_data;
>> +
>> +void its_parse_typer(void)
>> +{
>> + u64 typer = readq(gicv3_its_base() + GITS_TYPER);
>> +
>> + its_data.typer.ite_size = ((typer >> 4) & 0xf) + 1;
>> + its_data.typer.pta = typer & GITS_TYPER_PTA;
>> + its_data.typer.eventid_bits =
>> + ((typer >> GITS_TYPER_IDBITS_SHIFT) & 0x1f) + 1;
>> + its_data.typer.deviceid_bits = GITS_TYPER_DEVBITS(typer) + 1;
>
> No need to '+1'. As GITS_TYPER_DEVBITS already helps us to calculate
> the implemented DeviceID bits.
OK
>
>> +
>> + its_data.typer.cil = (typer >> 36) & 0x1;
>> + if (its_data.typer.cil)
>> + its_data.typer.collid_bits = ((typer >> 32) & 0xf) + 1;
>> + else
>> + its_data.typer.collid_bits = 16;
>> +
>> + its_data.typer.hw_collections =
>> + (typer >> GITS_TYPER_HWCOLLCNT_SHIFT) & 0xff;
>> +
>> + its_data.typer.cct = typer & 0x4;
>> + its_data.typer.virt_lpi = typer & 0x2;
>> + its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS;
>
> Personally, mix using of GITS_TYPER_* macros and some magic constants to
> parse the TYPER makes it a bit difficult to review the code. Maybe we
> can have more such kinds of macros in the header file and get rid of all
> hardcoded numbers?
Sure I will clean that up.
Thanks!
Eric
>
>
> Thanks,
> Zenghui
>
>
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^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests
2019-12-18 8:34 ` Auger Eric
@ 2019-12-20 7:34 ` Zenghui Yu
0 siblings, 0 replies; 28+ messages in thread
From: Zenghui Yu @ 2019-12-20 7:34 UTC (permalink / raw)
To: Auger Eric, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
On 2019/12/18 16:34, Auger Eric wrote:
> Hi Zenghui,
>
> On 12/18/19 4:46 AM, Zenghui Yu wrote:
>> Hi Eric,
>>
>> I have to admit that this is the first time I've looked into
>> the kvm-unit-tests code, so only some minor comments inline :)
>
> no problem. Thank you for looking at this.
>
> By the way, with patch 16 I was able to test yout fix: "KVM: arm/arm64:
> vgic: Don't rely on the wrong pending table". Reverting it produced an
> error.
which is great! Thanks for your work!
Zenghui
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [kvm-unit-tests PATCH 06/16] arm/arm64: ITS: Test BASER
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (4 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 05/16] arm/arm64: ITS: Introspection tests Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-20 6:59 ` Zenghui Yu
2019-12-16 14:02 ` [kvm-unit-tests PATCH 07/16] arm/arm64: ITS: Set the LPI config and pending tables Eric Auger
` (9 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Add helper routines to parse and set up BASER registers.
Add a new test dedicated to BASER<n> accesses.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
arm/gic.c | 20 ++++++++++
arm/unittests.cfg | 6 +++
lib/arm/asm/gic-v3-its.h | 17 ++++++++
lib/arm/gic-v3-its.c | 84 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 127 insertions(+)
diff --git a/arm/gic.c b/arm/gic.c
index adeb981..8b56fce 100644
--- a/arm/gic.c
+++ b/arm/gic.c
@@ -536,6 +536,22 @@ static void test_its_introspection(void)
typer->pta ? "Redist basse address" : "PE #");
}
+static void test_its_baser(void)
+{
+ struct its_baser *dev_baser, *coll_baser;
+
+ if (!gicv3_its_base()) {
+ report_skip("No ITS, skip ...");
+ return;
+ }
+
+ dev_baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE);
+ coll_baser = its_lookup_baser(GITS_BASER_TYPE_COLLECTION);
+ report(dev_baser && coll_baser, "detect device and collection BASER");
+ report_info("device baser entry_size = 0x%x", dev_baser->esz);
+ report_info("collection baser entry_size = 0x%x", dev_baser->esz);
+}
+
int main(int argc, char **argv)
{
if (!gic_init()) {
@@ -571,6 +587,10 @@ int main(int argc, char **argv)
report_prefix_push(argv[1]);
test_its_introspection();
report_prefix_pop();
+ } else if (strcmp(argv[1], "its-baser") == 0) {
+ report_prefix_push(argv[1]);
+ test_its_baser();
+ report_prefix_pop();
} else {
report_abort("Unknown subtest '%s'", argv[1]);
}
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index bd20460..2234a0f 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -128,6 +128,12 @@ smp = $MAX_SMP
extra_params = -machine gic-version=3 -append 'its-introspection'
groups = its
+[its-baser]
+file = gic.flat
+smp = $MAX_SMP
+extra_params = -machine gic-version=3 -append 'its-baser'
+groups = its
+
# Test PSCI emulation
[psci]
file = psci.flat
diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
index 2ce483e..0c0178d 100644
--- a/lib/arm/asm/gic-v3-its.h
+++ b/lib/arm/asm/gic-v3-its.h
@@ -100,9 +100,23 @@ struct its_typer {
bool virt_lpi;
};
+struct its_baser {
+ unsigned int index;
+ int type;
+ u64 cache;
+ int shr;
+ size_t psz;
+ int nr_pages;
+ bool indirect;
+ phys_addr_t table_addr;
+ bool valid;
+ int esz;
+};
+
struct its_data {
void *base;
struct its_typer typer;
+ struct its_baser baser[GITS_BASER_NR_REGS];
};
extern struct its_data its_data;
@@ -111,6 +125,9 @@ extern struct its_data its_data;
extern void its_parse_typer(void);
extern void its_init(void);
+extern int its_parse_baser(int i, struct its_baser *baser);
+extern void its_setup_baser(int i, struct its_baser *baser);
+extern struct its_baser *its_lookup_baser(int type);
#endif /* !__ASSEMBLY__ */
#endif /* _ASMARM_GIC_V3_ITS_H_ */
diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
index 34f4d0e..303022f 100644
--- a/lib/arm/gic-v3-its.c
+++ b/lib/arm/gic-v3-its.c
@@ -4,6 +4,7 @@
* This work is licensed under the terms of the GNU LGPL, version 2.
*/
#include <asm/gic.h>
+#include <alloc_page.h>
struct its_data its_data;
@@ -31,11 +32,94 @@ void its_parse_typer(void)
its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS;
}
+int its_parse_baser(int i, struct its_baser *baser)
+{
+ void *reg_addr = gicv3_its_base() + GITS_BASER + i * 8;
+ u64 val = readq(reg_addr);
+
+ if (!val) {
+ memset(baser, 0, sizeof(*baser));
+ return -1;
+ }
+
+ baser->valid = val & GITS_BASER_VALID;
+ baser->indirect = val & GITS_BASER_INDIRECT;
+ baser->type = GITS_BASER_TYPE(val);
+ baser->esz = GITS_BASER_ENTRY_SIZE(val);
+ baser->nr_pages = GITS_BASER_NR_PAGES(val);
+ baser->table_addr = val & GITS_BASER_PHYS_ADDR_MASK;
+ baser->cache = (val >> GITS_BASER_INNER_CACHEABILITY_SHIFT) &
+ GITS_BASER_CACHEABILITY_MASK;
+ switch (val & GITS_BASER_PAGE_SIZE_MASK) {
+ case GITS_BASER_PAGE_SIZE_4K:
+ baser->psz = SZ_4K;
+ break;
+ case GITS_BASER_PAGE_SIZE_16K:
+ baser->psz = SZ_16K;
+ break;
+ case GITS_BASER_PAGE_SIZE_64K:
+ baser->psz = SZ_64K;
+ break;
+ default:
+ baser->psz = SZ_64K;
+ }
+ baser->shr = (val >> 10) & 0x3;
+ return 0;
+}
+
+struct its_baser *its_lookup_baser(int type)
+{
+ int i;
+
+ for (i = 0; i < GITS_BASER_NR_REGS; i++) {
+ struct its_baser *baser = &its_data.baser[i];
+
+ if (baser->type == type)
+ return baser;
+ }
+ return NULL;
+}
+
void its_init(void)
{
+ int i;
if (!its_data.base)
return;
its_parse_typer();
+ for (i = 0; i < GITS_BASER_NR_REGS; i++)
+ its_parse_baser(i, &its_data.baser[i]);
+}
+
+void its_setup_baser(int i, struct its_baser *baser)
+{
+ unsigned long n = (baser->nr_pages * baser->psz) >> PAGE_SHIFT;
+ unsigned long order = is_power_of_2(n) ? fls(n) : fls(n) + 1;
+ u64 val;
+
+ baser->table_addr = (u64)virt_to_phys(alloc_pages(order));
+
+ val = ((u64)baser->table_addr |
+ ((u64)baser->type << GITS_BASER_TYPE_SHIFT) |
+ ((u64)(baser->esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
+ ((baser->nr_pages - 1) << GITS_BASER_PAGES_SHIFT) |
+ baser->cache |
+ baser->shr |
+ (u64)baser->indirect << 62 |
+ (u64)baser->valid << 63);
+
+ switch (baser->psz) {
+ case SZ_4K:
+ val |= GITS_BASER_PAGE_SIZE_4K;
+ break;
+ case SZ_16K:
+ val |= GITS_BASER_PAGE_SIZE_16K;
+ break;
+ case SZ_64K:
+ val |= GITS_BASER_PAGE_SIZE_64K;
+ break;
+ }
+
+ writeq(val, gicv3_its_base() + GITS_BASER + i * 8);
}
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 06/16] arm/arm64: ITS: Test BASER
2019-12-16 14:02 ` [kvm-unit-tests PATCH 06/16] arm/arm64: ITS: Test BASER Eric Auger
@ 2019-12-20 6:59 ` Zenghui Yu
0 siblings, 0 replies; 28+ messages in thread
From: Zenghui Yu @ 2019-12-20 6:59 UTC (permalink / raw)
To: Eric Auger, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Hi Eric,
On 2019/12/16 22:02, Eric Auger wrote:
> Add helper routines to parse and set up BASER registers.
> Add a new test dedicated to BASER<n> accesses.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> ---
> arm/gic.c | 20 ++++++++++
> arm/unittests.cfg | 6 +++
> lib/arm/asm/gic-v3-its.h | 17 ++++++++
> lib/arm/gic-v3-its.c | 84 ++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 127 insertions(+)
>
> diff --git a/arm/gic.c b/arm/gic.c
> index adeb981..8b56fce 100644
> --- a/arm/gic.c
> +++ b/arm/gic.c
> @@ -536,6 +536,22 @@ static void test_its_introspection(void)
> typer->pta ? "Redist basse address" : "PE #");
> }
>
> +static void test_its_baser(void)
> +{
> + struct its_baser *dev_baser, *coll_baser;
> +
> + if (!gicv3_its_base()) {
> + report_skip("No ITS, skip ...");
> + return;
> + }
> +
> + dev_baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE);
> + coll_baser = its_lookup_baser(GITS_BASER_TYPE_COLLECTION);
> + report(dev_baser && coll_baser, "detect device and collection BASER");
> + report_info("device baser entry_size = 0x%x", dev_baser->esz);
> + report_info("collection baser entry_size = 0x%x", dev_baser->esz);
s/dev_baser/coll_baser/
> +}
> +
> int main(int argc, char **argv)
> {
> if (!gic_init()) {
> @@ -571,6 +587,10 @@ int main(int argc, char **argv)
> report_prefix_push(argv[1]);
> test_its_introspection();
> report_prefix_pop();
> + } else if (strcmp(argv[1], "its-baser") == 0) {
> + report_prefix_push(argv[1]);
> + test_its_baser();
> + report_prefix_pop();
> } else {
> report_abort("Unknown subtest '%s'", argv[1]);
> }
> diff --git a/arm/unittests.cfg b/arm/unittests.cfg
> index bd20460..2234a0f 100644
> --- a/arm/unittests.cfg
> +++ b/arm/unittests.cfg
> @@ -128,6 +128,12 @@ smp = $MAX_SMP
> extra_params = -machine gic-version=3 -append 'its-introspection'
> groups = its
>
> +[its-baser]
> +file = gic.flat
> +smp = $MAX_SMP
> +extra_params = -machine gic-version=3 -append 'its-baser'
> +groups = its
> +
> # Test PSCI emulation
> [psci]
> file = psci.flat
> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
> index 2ce483e..0c0178d 100644
> --- a/lib/arm/asm/gic-v3-its.h
> +++ b/lib/arm/asm/gic-v3-its.h
> @@ -100,9 +100,23 @@ struct its_typer {
> bool virt_lpi;
> };
>
> +struct its_baser {
> + unsigned int index;
We've already maintained an array of GITS_BASERs, so 'index' is
not needed.
> + int type;
> + u64 cache;
> + int shr;
> + size_t psz;
> + int nr_pages;
> + bool indirect;
> + phys_addr_t table_addr;
> + bool valid;
> + int esz;
> +};
> +
> struct its_data {
> void *base;
> struct its_typer typer;
> + struct its_baser baser[GITS_BASER_NR_REGS];
> };
>
> extern struct its_data its_data;
> @@ -111,6 +125,9 @@ extern struct its_data its_data;
>
> extern void its_parse_typer(void);
> extern void its_init(void);
> +extern int its_parse_baser(int i, struct its_baser *baser);
> +extern void its_setup_baser(int i, struct its_baser *baser);
> +extern struct its_baser *its_lookup_baser(int type);
>
> #endif /* !__ASSEMBLY__ */
> #endif /* _ASMARM_GIC_V3_ITS_H_ */
> diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
> index 34f4d0e..303022f 100644
> --- a/lib/arm/gic-v3-its.c
> +++ b/lib/arm/gic-v3-its.c
> @@ -4,6 +4,7 @@
> * This work is licensed under the terms of the GNU LGPL, version 2.
> */
> #include <asm/gic.h>
> +#include <alloc_page.h>
>
> struct its_data its_data;
>
> @@ -31,11 +32,94 @@ void its_parse_typer(void)
> its_data.typer.phys_lpi = typer & GITS_TYPER_PLPIS;
> }
>
> +int its_parse_baser(int i, struct its_baser *baser)
> +{
> + void *reg_addr = gicv3_its_base() + GITS_BASER + i * 8;
> + u64 val = readq(reg_addr);
> +
> + if (!val) {
> + memset(baser, 0, sizeof(*baser));
> + return -1;
> + }
> +
> + baser->valid = val & GITS_BASER_VALID;
> + baser->indirect = val & GITS_BASER_INDIRECT;
> + baser->type = GITS_BASER_TYPE(val);
> + baser->esz = GITS_BASER_ENTRY_SIZE(val);
> + baser->nr_pages = GITS_BASER_NR_PAGES(val);
> + baser->table_addr = val & GITS_BASER_PHYS_ADDR_MASK;
> + baser->cache = (val >> GITS_BASER_INNER_CACHEABILITY_SHIFT) &
> + GITS_BASER_CACHEABILITY_MASK;
> + switch (val & GITS_BASER_PAGE_SIZE_MASK) {
> + case GITS_BASER_PAGE_SIZE_4K:
> + baser->psz = SZ_4K;
> + break;
> + case GITS_BASER_PAGE_SIZE_16K:
> + baser->psz = SZ_16K;
> + break;
> + case GITS_BASER_PAGE_SIZE_64K:
> + baser->psz = SZ_64K;
> + break;
> + default:
> + baser->psz = SZ_64K;
> + }
> + baser->shr = (val >> 10) & 0x3;
> + return 0;
> +}
> +
> +struct its_baser *its_lookup_baser(int type)
> +{
> + int i;
> +
> + for (i = 0; i < GITS_BASER_NR_REGS; i++) {
> + struct its_baser *baser = &its_data.baser[i];
> +
> + if (baser->type == type)
> + return baser;
> + }
> + return NULL;
> +}
> +
> void its_init(void)
> {
> + int i;
Please add a blank line here.
> if (!its_data.base)
> return;
>
> its_parse_typer();
> + for (i = 0; i < GITS_BASER_NR_REGS; i++)
> + its_parse_baser(i, &its_data.baser[i]);
> +}
> +
> +void its_setup_baser(int i, struct its_baser *baser)
> +{
> + unsigned long n = (baser->nr_pages * baser->psz) >> PAGE_SHIFT;
> + unsigned long order = is_power_of_2(n) ? fls(n) : fls(n) + 1;
> + u64 val;
> +
> + baser->table_addr = (u64)virt_to_phys(alloc_pages(order));
> +
> + val = ((u64)baser->table_addr |
> + ((u64)baser->type << GITS_BASER_TYPE_SHIFT) |
> + ((u64)(baser->esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
> + ((baser->nr_pages - 1) << GITS_BASER_PAGES_SHIFT) |
> + baser->cache |
> + baser->shr |
baser->cache << GITS_BASER_INNER_CACHEABILITY_SHIFT |
baser->shr << 10 (GITS_BASER_SHAREABILITY_SHIFT) ?
Thanks,
Zenghui
> + (u64)baser->indirect << 62 |
> + (u64)baser->valid << 63);
> +
> + switch (baser->psz) {
> + case SZ_4K:
> + val |= GITS_BASER_PAGE_SIZE_4K;
> + break;
> + case SZ_16K:
> + val |= GITS_BASER_PAGE_SIZE_16K;
> + break;
> + case SZ_64K:
> + val |= GITS_BASER_PAGE_SIZE_64K;
> + break;
> + }
> +
> + writeq(val, gicv3_its_base() + GITS_BASER + i * 8);
> }
>
>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [kvm-unit-tests PATCH 07/16] arm/arm64: ITS: Set the LPI config and pending tables
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (5 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 06/16] arm/arm64: ITS: Test BASER Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 08/16] arm/arm64: ITS: Init the command queue Eric Auger
` (8 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Allocate the LPI configuration and per re-distributor pending table.
Set redistributor's PROPBASER and PENDBASER. The LPIs are enabled
by default in the config table.
Also introduce a helper routine that allows to set the pending table
bit for a given LPI.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
lib/arm/asm/gic-v3-its.h | 3 ++
lib/arm/asm/gic-v3.h | 79 ++++++++++++++++++++++++++++++++++++++++
lib/arm/gic-v3-its.c | 65 +++++++++++++++++++++++++++++++++
3 files changed, 147 insertions(+)
diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
index 0c0178d..0d11aed 100644
--- a/lib/arm/asm/gic-v3-its.h
+++ b/lib/arm/asm/gic-v3-its.h
@@ -128,6 +128,9 @@ extern void its_init(void);
extern int its_parse_baser(int i, struct its_baser *baser);
extern void its_setup_baser(int i, struct its_baser *baser);
extern struct its_baser *its_lookup_baser(int type);
+extern void set_lpi_config(int n, u8 val);
+extern u8 get_lpi_config(int n);
+extern void set_pending_table_bit(int rdist, int n, bool set);
#endif /* !__ASSEMBLY__ */
#endif /* _ASMARM_GIC_V3_ITS_H_ */
diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
index d02f4a4..5bf9a92 100644
--- a/lib/arm/asm/gic-v3.h
+++ b/lib/arm/asm/gic-v3.h
@@ -47,6 +47,83 @@
#define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
(MPIDR_AFFINITY_LEVEL(cluster_id, level) << ICC_SGI1R_AFFINITY_## level ## _SHIFT)
+#define GIC_BASER_CACHE_nCnB 0ULL
+#define GIC_BASER_CACHE_SameAsInner 0ULL
+#define GIC_BASER_CACHE_nC 1ULL
+#define GIC_BASER_CACHE_RaWt 2ULL
+#define GIC_BASER_CACHE_RaWb 3ULL
+#define GIC_BASER_CACHE_WaWt 4ULL
+#define GIC_BASER_CACHE_WaWb 5ULL
+#define GIC_BASER_CACHE_RaWaWt 6ULL
+#define GIC_BASER_CACHE_RaWaWb 7ULL
+#define GIC_BASER_CACHE_MASK 7ULL
+#define GIC_BASER_NonShareable 0ULL
+#define GIC_BASER_InnerShareable 1ULL
+#define GIC_BASER_OuterShareable 2ULL
+#define GIC_BASER_SHAREABILITY_MASK 3ULL
+
+#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
+ (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
+
+#define GIC_BASER_SHAREABILITY(reg, type) \
+ (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
+
+#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
+#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
+#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
+#define GICR_PROPBASER_SHAREABILITY_MASK \
+ GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
+#define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
+#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
+#define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
+
+#define GICR_PROPBASER_InnerShareable \
+ GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
+
+#define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
+#define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
+#define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
+#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
+#define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
+#define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
+#define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
+#define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
+
+#define GICR_PROPBASER_IDBITS_MASK (0x1f)
+
+#define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
+#define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
+#define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
+#define GICR_PENDBASER_SHAREABILITY_MASK \
+ GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
+#define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
+#define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
+#define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
+
+#define GICR_PENDBASER_InnerShareable \
+ GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
+
+#define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
+#define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
+#define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
+#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
+#define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
+#define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
+#define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
+#define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
+
+#define GICR_PENDBASER_PTZ BIT_ULL(62)
+
+#define LPI_PROP_GROUP1 (1 << 1)
+#define LPI_PROP_ENABLED (1 << 0)
+#define LPI_PROP_DEFAULT_PRIO 0xa0
+#define LPI_PROP_DEFAULT (LPI_PROP_DEFAULT_PRIO | \
+ LPI_PROP_GROUP1 | LPI_PROP_ENABLED)
+
#include <asm/arch_gicv3.h>
#ifndef __ASSEMBLY__
@@ -63,6 +140,8 @@ struct gicv3_data {
void *dist_base;
void *redist_bases[GICV3_NR_REDISTS];
void *redist_base[NR_CPUS];
+ void *lpi_prop;
+ void *lpi_pend[NR_CPUS];
unsigned int irq_nr;
};
extern struct gicv3_data gicv3_data;
diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
index 303022f..0b5a700 100644
--- a/lib/arm/gic-v3-its.c
+++ b/lib/arm/gic-v3-its.c
@@ -123,3 +123,68 @@ void its_setup_baser(int i, struct its_baser *baser)
writeq(val, gicv3_its_base() + GITS_BASER + i * 8);
}
+inline void set_lpi_config(int n, u8 value)
+{
+ u8 *entry = (u8 *)(gicv3_data.lpi_prop + (n - 8192));
+ *entry = value;
+}
+
+inline u8 get_lpi_config(int n)
+{
+ u8 *entry = (u8 *)(gicv3_data.lpi_prop + (n - 8192));
+ return *entry;
+}
+
+/* alloc_lpi_tables: Allocate LPI config and pending tables */
+void alloc_lpi_tables(void);
+void alloc_lpi_tables(void)
+{
+ unsigned long n = SZ_64K >> PAGE_SHIFT;
+ unsigned long order = fls(n);
+ u64 prop_val;
+ int cpu;
+
+ gicv3_data.lpi_prop = (void *)virt_to_phys(alloc_pages(order));
+
+ /* ID bits = 13, ie. up to 14b LPI INTID */
+ prop_val = ((u64)gicv3_data.lpi_prop |
+ GICR_PROPBASER_InnerShareable |
+ GICR_PROPBASER_WaWb |
+ (13 & GICR_PROPBASER_IDBITS_MASK));
+
+ /*
+ * Allocate pending tables for each redistributor
+ * and set PROPBASER and PENDBASER
+ */
+ for_each_present_cpu(cpu) {
+ u64 pend_val;
+ void *ptr;
+
+ ptr = gicv3_data.redist_base[cpu];
+
+ writeq(prop_val, ptr + GICR_PROPBASER);
+
+ gicv3_data.lpi_pend[cpu] =
+ (void *)virt_to_phys(alloc_pages(order));
+
+ pend_val = ((u64)gicv3_data.lpi_pend[cpu] |
+ GICR_PENDBASER_InnerShareable |
+ GICR_PENDBASER_WaWb);
+
+ writeq(pend_val, ptr + GICR_PENDBASER);
+ }
+}
+
+void set_pending_table_bit(int rdist, int n, bool set)
+{
+ u8 *ptr = phys_to_virt((phys_addr_t)gicv3_data.lpi_pend[rdist]);
+ u8 mask = 1 << (n % 8), byte;
+
+ ptr += (n / 8);
+ byte = *ptr;
+ if (set)
+ byte |= mask;
+ else
+ byte &= ~mask;
+ *ptr = byte;
+}
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* [kvm-unit-tests PATCH 08/16] arm/arm64: ITS: Init the command queue
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (6 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 07/16] arm/arm64: ITS: Set the LPI config and pending tables Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-20 7:10 ` Zenghui Yu
2019-12-16 14:02 ` [kvm-unit-tests PATCH 09/16] arm/arm64: ITS: Enable/Disable LPIs at re-distributor level Eric Auger
` (7 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Allocate the command queue and initialize related registers:
CBASER, CREADR, CWRITER.
The command queue is 64kB. This aims at not bothing with fullness.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
lib/arm/asm/gic-v3-its.h | 7 +++++++
lib/arm/gic-v3-its.c | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
index 0d11aed..ed42707 100644
--- a/lib/arm/asm/gic-v3-its.h
+++ b/lib/arm/asm/gic-v3-its.h
@@ -113,10 +113,17 @@ struct its_baser {
int esz;
};
+struct its_cmd_block {
+ u64 raw_cmd[4];
+};
+
struct its_data {
void *base;
struct its_typer typer;
struct its_baser baser[GITS_BASER_NR_REGS];
+ struct its_cmd_block *cmd_base;
+ struct its_cmd_block *cmd_write;
+ struct its_cmd_block *cmd_readr;
};
extern struct its_data its_data;
diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
index 0b5a700..8b6a095 100644
--- a/lib/arm/gic-v3-its.c
+++ b/lib/arm/gic-v3-its.c
@@ -188,3 +188,40 @@ void set_pending_table_bit(int rdist, int n, bool set)
byte &= ~mask;
*ptr = byte;
}
+
+/**
+ * init_cmd_queue: Allocate the command queue and initialize
+ * CBASER, CREADR, CWRITER
+ */
+void init_cmd_queue(void);
+void init_cmd_queue(void)
+{
+ unsigned long n = SZ_64K >> PAGE_SHIFT;
+ unsigned long order = fls(n);
+ u64 cbaser, tmp;
+
+ its_data.cmd_base = (void *)virt_to_phys(alloc_pages(order));
+
+ cbaser = ((u64)its_data.cmd_base |
+ GITS_CBASER_WaWb |
+ GITS_CBASER_InnerShareable |
+ (SZ_64K / SZ_4K - 1) |
+ GITS_CBASER_VALID);
+
+ writeq(cbaser, its_data.base + GITS_CBASER);
+ tmp = readq(its_data.base + GITS_CBASER);
+
+ if ((tmp ^ cbaser) & GITS_CBASER_SHAREABILITY_MASK) {
+ if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
+ cbaser &= ~(GITS_CBASER_SHAREABILITY_MASK |
+ GITS_CBASER_CACHEABILITY_MASK);
+ cbaser |= GITS_CBASER_nC;
+ writeq(cbaser, its_data.base + GITS_CBASER);
+ }
+ }
+
+ its_data.cmd_write = its_data.cmd_base;
+ its_data.cmd_readr = its_data.cmd_base;
+ writeq(0, its_data.base + GITS_CWRITER);
+ writeq(0, its_data.base + GITS_CREADR);
+}
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 08/16] arm/arm64: ITS: Init the command queue
2019-12-16 14:02 ` [kvm-unit-tests PATCH 08/16] arm/arm64: ITS: Init the command queue Eric Auger
@ 2019-12-20 7:10 ` Zenghui Yu
2020-01-10 14:19 ` Auger Eric
0 siblings, 1 reply; 28+ messages in thread
From: Zenghui Yu @ 2019-12-20 7:10 UTC (permalink / raw)
To: Eric Auger, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Hi Eric,
On 2019/12/16 22:02, Eric Auger wrote:
> Allocate the command queue and initialize related registers:
> CBASER, CREADR, CWRITER.
>
> The command queue is 64kB. This aims at not bothing with fullness.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> ---
> lib/arm/asm/gic-v3-its.h | 7 +++++++
> lib/arm/gic-v3-its.c | 37 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 44 insertions(+)
>
> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
> index 0d11aed..ed42707 100644
> --- a/lib/arm/asm/gic-v3-its.h
> +++ b/lib/arm/asm/gic-v3-its.h
> @@ -113,10 +113,17 @@ struct its_baser {
> int esz;
> };
>
> +struct its_cmd_block {
> + u64 raw_cmd[4];
> +};
> +
> struct its_data {
> void *base;
> struct its_typer typer;
> struct its_baser baser[GITS_BASER_NR_REGS];
> + struct its_cmd_block *cmd_base;
> + struct its_cmd_block *cmd_write;
> + struct its_cmd_block *cmd_readr;
I think we can just get rid of the 'cmd_readr'. As GITS_CREADR is
generally manipulated by the ITS, and ...
> };
>
> extern struct its_data its_data;
> diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
> index 0b5a700..8b6a095 100644
> --- a/lib/arm/gic-v3-its.c
> +++ b/lib/arm/gic-v3-its.c
> @@ -188,3 +188,40 @@ void set_pending_table_bit(int rdist, int n, bool set)
> byte &= ~mask;
> *ptr = byte;
> }
> +
> +/**
> + * init_cmd_queue: Allocate the command queue and initialize
> + * CBASER, CREADR, CWRITER
> + */
> +void init_cmd_queue(void);
> +void init_cmd_queue(void)
> +{
> + unsigned long n = SZ_64K >> PAGE_SHIFT;
> + unsigned long order = fls(n);
> + u64 cbaser, tmp;
> +
> + its_data.cmd_base = (void *)virt_to_phys(alloc_pages(order));
> +
> + cbaser = ((u64)its_data.cmd_base |
> + GITS_CBASER_WaWb |
> + GITS_CBASER_InnerShareable |
> + (SZ_64K / SZ_4K - 1) |
> + GITS_CBASER_VALID);
> +
> + writeq(cbaser, its_data.base + GITS_CBASER);
..."(CREADR) is cleared to 0 when a value is written to GITS_CBASER."
-- from IHI0069E 9.19.3
> + tmp = readq(its_data.base + GITS_CBASER);
> +
> + if ((tmp ^ cbaser) & GITS_CBASER_SHAREABILITY_MASK) {
> + if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
> + cbaser &= ~(GITS_CBASER_SHAREABILITY_MASK |
> + GITS_CBASER_CACHEABILITY_MASK);
> + cbaser |= GITS_CBASER_nC;
> + writeq(cbaser, its_data.base + GITS_CBASER);
> + }
> + }
> +
> + its_data.cmd_write = its_data.cmd_base;
> + its_data.cmd_readr = its_data.cmd_base;
> + writeq(0, its_data.base + GITS_CWRITER);
> + writeq(0, its_data.base + GITS_CREADR);
So this writeq() is also not needed.
Or I've just missed the point that this is done by intention to test
"whether the GITS_CREADR implemented by KVM is Write Ignored"?
If so, please ignore all of the comments above :)
Thanks,
Zenghui
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^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 08/16] arm/arm64: ITS: Init the command queue
2019-12-20 7:10 ` Zenghui Yu
@ 2020-01-10 14:19 ` Auger Eric
0 siblings, 0 replies; 28+ messages in thread
From: Auger Eric @ 2020-01-10 14:19 UTC (permalink / raw)
To: Zenghui Yu, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Hi Zenghui,
On 12/20/19 8:10 AM, Zenghui Yu wrote:
> Hi Eric,
>
> On 2019/12/16 22:02, Eric Auger wrote:
>> Allocate the command queue and initialize related registers:
>> CBASER, CREADR, CWRITER.
>>
>> The command queue is 64kB. This aims at not bothing with fullness.
>>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>> ---
>> lib/arm/asm/gic-v3-its.h | 7 +++++++
>> lib/arm/gic-v3-its.c | 37 +++++++++++++++++++++++++++++++++++++
>> 2 files changed, 44 insertions(+)
>>
>> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
>> index 0d11aed..ed42707 100644
>> --- a/lib/arm/asm/gic-v3-its.h
>> +++ b/lib/arm/asm/gic-v3-its.h
>> @@ -113,10 +113,17 @@ struct its_baser {
>> int esz;
>> };
>> +struct its_cmd_block {
>> + u64 raw_cmd[4];
>> +};
>> +
>> struct its_data {
>> void *base;
>> struct its_typer typer;
>> struct its_baser baser[GITS_BASER_NR_REGS];
>> + struct its_cmd_block *cmd_base;
>> + struct its_cmd_block *cmd_write;
>> + struct its_cmd_block *cmd_readr;
>
> I think we can just get rid of the 'cmd_readr'. As GITS_CREADR is
> generally manipulated by the ITS, and ...
>
>> };
>> extern struct its_data its_data;
>> diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
>> index 0b5a700..8b6a095 100644
>> --- a/lib/arm/gic-v3-its.c
>> +++ b/lib/arm/gic-v3-its.c
>> @@ -188,3 +188,40 @@ void set_pending_table_bit(int rdist, int n, bool
>> set)
>> byte &= ~mask;
>> *ptr = byte;
>> }
>> +
>> +/**
>> + * init_cmd_queue: Allocate the command queue and initialize
>> + * CBASER, CREADR, CWRITER
>> + */
>> +void init_cmd_queue(void);
>> +void init_cmd_queue(void)
>> +{
>> + unsigned long n = SZ_64K >> PAGE_SHIFT;
>> + unsigned long order = fls(n);
>> + u64 cbaser, tmp;
>> +
>> + its_data.cmd_base = (void *)virt_to_phys(alloc_pages(order));
>> +
>> + cbaser = ((u64)its_data.cmd_base |
>> + GITS_CBASER_WaWb |
>> + GITS_CBASER_InnerShareable |
>> + (SZ_64K / SZ_4K - 1) |
>> + GITS_CBASER_VALID);
>> +
>> + writeq(cbaser, its_data.base + GITS_CBASER);
>
> ..."(CREADR) is cleared to 0 when a value is written to GITS_CBASER."
> -- from IHI0069E 9.19.3
>
>> + tmp = readq(its_data.base + GITS_CBASER);
>> +
>> + if ((tmp ^ cbaser) & GITS_CBASER_SHAREABILITY_MASK) {
>> + if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
>> + cbaser &= ~(GITS_CBASER_SHAREABILITY_MASK |
>> + GITS_CBASER_CACHEABILITY_MASK);
>> + cbaser |= GITS_CBASER_nC;
>> + writeq(cbaser, its_data.base + GITS_CBASER);
>> + }
>> + }
>> +
>> + its_data.cmd_write = its_data.cmd_base;
>> + its_data.cmd_readr = its_data.cmd_base;
>> + writeq(0, its_data.base + GITS_CWRITER);
>> + writeq(0, its_data.base + GITS_CREADR);
>
> So this writeq() is also not needed.
>
> Or I've just missed the point that this is done by intention to test
> "whether the GITS_CREADR implemented by KVM is Write Ignored"?
> If so, please ignore all of the comments above :)
No I must admit this was not done on purpose. I can remove it from the
its_data struct at the moment.
Thanks
Eric
>
>
> Thanks,
> Zenghui
>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [kvm-unit-tests PATCH 09/16] arm/arm64: ITS: Enable/Disable LPIs at re-distributor level
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (7 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 08/16] arm/arm64: ITS: Init the command queue Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 10/16] arm/arm64: ITS: its_enable_defaults Eric Auger
` (6 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
This helper function enables or disables the signaling of LPIs
at redistributor level.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
lib/arm/asm/gic-v3-its.h | 1 +
lib/arm/gic-v3-its.c | 18 ++++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
index ed42707..d56a17f 100644
--- a/lib/arm/asm/gic-v3-its.h
+++ b/lib/arm/asm/gic-v3-its.h
@@ -138,6 +138,7 @@ extern struct its_baser *its_lookup_baser(int type);
extern void set_lpi_config(int n, u8 val);
extern u8 get_lpi_config(int n);
extern void set_pending_table_bit(int rdist, int n, bool set);
+extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set);
#endif /* !__ASSEMBLY__ */
#endif /* _ASMARM_GIC_V3_ITS_H_ */
diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
index 8b6a095..b0f7714 100644
--- a/lib/arm/gic-v3-its.c
+++ b/lib/arm/gic-v3-its.c
@@ -225,3 +225,21 @@ void init_cmd_queue(void)
writeq(0, its_data.base + GITS_CWRITER);
writeq(0, its_data.base + GITS_CREADR);
}
+
+void gicv3_rdist_ctrl_lpi(u32 redist, bool set)
+{
+ void *ptr;
+ u64 val;
+
+ if (redist >= nr_cpus)
+ report_abort("%s redist=%d >= cpu_count=%d\n",
+ __func__, redist, nr_cpus);
+
+ ptr = gicv3_data.redist_base[redist];
+ val = readl(ptr + GICR_CTLR);
+ if (set)
+ val |= GICR_CTLR_ENABLE_LPIS;
+ else
+ val &= ~GICR_CTLR_ENABLE_LPIS;
+ writel(val, ptr + GICR_CTLR);
+}
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* [kvm-unit-tests PATCH 10/16] arm/arm64: ITS: its_enable_defaults
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (8 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 09/16] arm/arm64: ITS: Enable/Disable LPIs at re-distributor level Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 11/16] arm/arm64: ITS: Device and collection Initialization Eric Auger
` (5 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
its_enable_defaults() is the top init function that allocates all
the requested tables (device, collection, lpi config and pending
tables), enable LPIs at distributor level and ITS level.
gicv3_enable_defaults must be called before.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
lib/arm/asm/gic-v3-its.h | 1 +
lib/arm/gic-v3-its.c | 41 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
index d56a17f..ab639c5 100644
--- a/lib/arm/asm/gic-v3-its.h
+++ b/lib/arm/asm/gic-v3-its.h
@@ -139,6 +139,7 @@ extern void set_lpi_config(int n, u8 val);
extern u8 get_lpi_config(int n);
extern void set_pending_table_bit(int rdist, int n, bool set);
extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set);
+extern void its_enable_defaults(void);
#endif /* !__ASSEMBLY__ */
#endif /* _ASMARM_GIC_V3_ITS_H_ */
diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
index b0f7714..9a51ef4 100644
--- a/lib/arm/gic-v3-its.c
+++ b/lib/arm/gic-v3-its.c
@@ -243,3 +243,44 @@ void gicv3_rdist_ctrl_lpi(u32 redist, bool set)
val &= ~GICR_CTLR_ENABLE_LPIS;
writel(val, ptr + GICR_CTLR);
}
+
+void its_enable_defaults(void)
+{
+ unsigned int i;
+
+ its_parse_typer();
+
+ /* Allocate BASER tables (device and collection tables) */
+ for (i = 0; i < GITS_BASER_NR_REGS; i++) {
+ struct its_baser *baser = &its_data.baser[i];
+ int ret;
+
+ ret = its_parse_baser(i, baser);
+ if (ret)
+ continue;
+
+ switch (baser->type) {
+ case GITS_BASER_TYPE_DEVICE:
+ baser->valid = true;
+ baser->cache = GITS_BASER_nCnB;
+ its_setup_baser(i, baser);
+ break;
+ case GITS_BASER_TYPE_COLLECTION:
+ baser->valid = true;
+ its_setup_baser(i, baser);
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Allocate LPI config and pending tables */
+ alloc_lpi_tables();
+
+ init_cmd_queue();
+
+ for (i = 0; i < nr_cpus; i++)
+ gicv3_rdist_ctrl_lpi(i, true);
+
+ writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR);
+}
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* [kvm-unit-tests PATCH 11/16] arm/arm64: ITS: Device and collection Initialization
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (9 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 10/16] arm/arm64: ITS: its_enable_defaults Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-20 7:25 ` Zenghui Yu
2019-12-16 14:02 ` [kvm-unit-tests PATCH 12/16] arm/arm64: ITS: commands Eric Auger
` (4 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Introduce an helper functions to register
- a new device, characterized by its device id and the
max number of event IDs that dimension its ITT (Interrupt
Translation Table). The function allocates the ITT.
- a new collection, characterized by its ID and the
target processing engine (PE).
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
---
lib/arm/asm/gic-v3-its.h | 20 +++++++++++++++++
lib/arm/gic-v3-its.c | 46 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
index ab639c5..245ef61 100644
--- a/lib/arm/asm/gic-v3-its.h
+++ b/lib/arm/asm/gic-v3-its.h
@@ -87,6 +87,9 @@
#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
+#define GITS_MAX_DEVICES 8
+#define GITS_MAX_COLLECTIONS 8
+
struct its_typer {
unsigned int ite_size;
unsigned int eventid_bits;
@@ -117,6 +120,17 @@ struct its_cmd_block {
u64 raw_cmd[4];
};
+struct its_device {
+ u32 device_id; /* device ID */
+ u32 nr_ites; /* Max Interrupt Translation Entries */
+ void *itt; /* Interrupt Translation Table GPA */
+};
+
+struct its_collection {
+ u64 target_address;
+ u16 col_id;
+};
+
struct its_data {
void *base;
struct its_typer typer;
@@ -124,6 +138,10 @@ struct its_data {
struct its_cmd_block *cmd_base;
struct its_cmd_block *cmd_write;
struct its_cmd_block *cmd_readr;
+ struct its_device devices[GITS_MAX_DEVICES];
+ u32 nb_devices; /* Allocated Devices */
+ struct its_collection collections[GITS_MAX_COLLECTIONS];
+ u32 nb_collections; /* Allocated Collections */
};
extern struct its_data its_data;
@@ -140,6 +158,8 @@ extern u8 get_lpi_config(int n);
extern void set_pending_table_bit(int rdist, int n, bool set);
extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set);
extern void its_enable_defaults(void);
+extern struct its_device *its_create_device(u32 dev_id, int nr_ites);
+extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe);
#endif /* !__ASSEMBLY__ */
#endif /* _ASMARM_GIC_V3_ITS_H_ */
diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
index 9a51ef4..9906428 100644
--- a/lib/arm/gic-v3-its.c
+++ b/lib/arm/gic-v3-its.c
@@ -284,3 +284,49 @@ void its_enable_defaults(void)
writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR);
}
+
+struct its_device *its_create_device(u32 device_id, int nr_ites)
+{
+ struct its_baser *baser;
+ struct its_device *new;
+ unsigned long n, order;
+
+ if (its_data.nb_devices >= GITS_MAX_DEVICES)
+ report_abort("%s redimension GITS_MAX_DEVICES", __func__);
+
+ baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE);
+ if (!baser)
+ return NULL;
+
+ new = &its_data.devices[its_data.nb_devices];
+
+ new->device_id = device_id;
+ new->nr_ites = nr_ites;
+
+ n = (baser->esz * nr_ites) >> PAGE_SHIFT;
+ order = is_power_of_2(n) ? fls(n) : fls(n) + 1;
+ new->itt = (void *)virt_to_phys(alloc_pages(order));
+
+ its_data.nb_devices++;
+ return new;
+}
+
+struct its_collection *its_create_collection(u32 col_id, u32 pe)
+{
+ struct its_collection *new;
+
+ if (its_data.nb_collections >= GITS_MAX_COLLECTIONS)
+ report_abort("%s redimension GITS_MAX_COLLECTIONS", __func__);
+
+ new = &its_data.collections[its_data.nb_collections];
+
+ new->col_id = col_id;
+
+ if (its_data.typer.pta)
+ new->target_address = (u64)gicv3_data.redist_base[pe];
+ else
+ new->target_address = pe << 16;
+
+ its_data.nb_collections++;
+ return new;
+}
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 11/16] arm/arm64: ITS: Device and collection Initialization
2019-12-16 14:02 ` [kvm-unit-tests PATCH 11/16] arm/arm64: ITS: Device and collection Initialization Eric Auger
@ 2019-12-20 7:25 ` Zenghui Yu
2020-01-10 14:32 ` Auger Eric
0 siblings, 1 reply; 28+ messages in thread
From: Zenghui Yu @ 2019-12-20 7:25 UTC (permalink / raw)
To: Eric Auger, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Hi Eric,
On 2019/12/16 22:02, Eric Auger wrote:
> Introduce an helper functions to register
> - a new device, characterized by its device id and the
> max number of event IDs that dimension its ITT (Interrupt
> Translation Table). The function allocates the ITT.
>
> - a new collection, characterized by its ID and the
> target processing engine (PE).
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>
> ---
> ---
> lib/arm/asm/gic-v3-its.h | 20 +++++++++++++++++
> lib/arm/gic-v3-its.c | 46 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 66 insertions(+)
>
> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
> index ab639c5..245ef61 100644
> --- a/lib/arm/asm/gic-v3-its.h
> +++ b/lib/arm/asm/gic-v3-its.h
> @@ -87,6 +87,9 @@
>
> #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
>
> +#define GITS_MAX_DEVICES 8
> +#define GITS_MAX_COLLECTIONS 8
> +
> struct its_typer {
> unsigned int ite_size;
> unsigned int eventid_bits;
> @@ -117,6 +120,17 @@ struct its_cmd_block {
> u64 raw_cmd[4];
> };
>
> +struct its_device {
> + u32 device_id; /* device ID */
> + u32 nr_ites; /* Max Interrupt Translation Entries */
> + void *itt; /* Interrupt Translation Table GPA */
> +};
> +
> +struct its_collection {
> + u64 target_address;
> + u16 col_id;
> +};
> +
> struct its_data {
> void *base;
> struct its_typer typer;
> @@ -124,6 +138,10 @@ struct its_data {
> struct its_cmd_block *cmd_base;
> struct its_cmd_block *cmd_write;
> struct its_cmd_block *cmd_readr;
> + struct its_device devices[GITS_MAX_DEVICES];
> + u32 nb_devices; /* Allocated Devices */
> + struct its_collection collections[GITS_MAX_COLLECTIONS];
> + u32 nb_collections; /* Allocated Collections */
('nr_*' may be the more widely used one.)
> };
>
> extern struct its_data its_data;
> @@ -140,6 +158,8 @@ extern u8 get_lpi_config(int n);
> extern void set_pending_table_bit(int rdist, int n, bool set);
> extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set);
> extern void its_enable_defaults(void);
> +extern struct its_device *its_create_device(u32 dev_id, int nr_ites);
> +extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe);
>
> #endif /* !__ASSEMBLY__ */
> #endif /* _ASMARM_GIC_V3_ITS_H_ */
> diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
> index 9a51ef4..9906428 100644
> --- a/lib/arm/gic-v3-its.c
> +++ b/lib/arm/gic-v3-its.c
> @@ -284,3 +284,49 @@ void its_enable_defaults(void)
>
> writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR);
> }
> +
> +struct its_device *its_create_device(u32 device_id, int nr_ites)
> +{
> + struct its_baser *baser;
> + struct its_device *new;
> + unsigned long n, order;
> +
> + if (its_data.nb_devices >= GITS_MAX_DEVICES)
> + report_abort("%s redimension GITS_MAX_DEVICES", __func__);
> +
> + baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE);
> + if (!baser)
> + return NULL;
> +
> + new = &its_data.devices[its_data.nb_devices];
> +
> + new->device_id = device_id;
> + new->nr_ites = nr_ites;
> +
> + n = (baser->esz * nr_ites) >> PAGE_SHIFT;
baser->esz is GITS_BASER.Entry_Size, which indicates the size of
Device Table entry.
We're allocating ITT for this device now, shouldn't we use
its_data.typer.esz?
Thanks,
Zenghui
> + order = is_power_of_2(n) ? fls(n) : fls(n) + 1;
> + new->itt = (void *)virt_to_phys(alloc_pages(order));
> +
> + its_data.nb_devices++;
> + return new;
> +}
> +
> +struct its_collection *its_create_collection(u32 col_id, u32 pe)
> +{
> + struct its_collection *new;
> +
> + if (its_data.nb_collections >= GITS_MAX_COLLECTIONS)
> + report_abort("%s redimension GITS_MAX_COLLECTIONS", __func__);
> +
> + new = &its_data.collections[its_data.nb_collections];
> +
> + new->col_id = col_id;
> +
> + if (its_data.typer.pta)
> + new->target_address = (u64)gicv3_data.redist_base[pe];
> + else
> + new->target_address = pe << 16;
> +
> + its_data.nb_collections++;
> + return new;
> +}
>
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^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 11/16] arm/arm64: ITS: Device and collection Initialization
2019-12-20 7:25 ` Zenghui Yu
@ 2020-01-10 14:32 ` Auger Eric
0 siblings, 0 replies; 28+ messages in thread
From: Auger Eric @ 2020-01-10 14:32 UTC (permalink / raw)
To: Zenghui Yu, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Hi Zenghui,
On 12/20/19 8:25 AM, Zenghui Yu wrote:
> Hi Eric,
>
> On 2019/12/16 22:02, Eric Auger wrote:
>> Introduce an helper functions to register
>> - a new device, characterized by its device id and the
>> max number of event IDs that dimension its ITT (Interrupt
>> Translation Table). The function allocates the ITT.
>>
>> - a new collection, characterized by its ID and the
>> target processing engine (PE).
>>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>>
>> ---
>> ---
>> lib/arm/asm/gic-v3-its.h | 20 +++++++++++++++++
>> lib/arm/gic-v3-its.c | 46 ++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 66 insertions(+)
>>
>> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
>> index ab639c5..245ef61 100644
>> --- a/lib/arm/asm/gic-v3-its.h
>> +++ b/lib/arm/asm/gic-v3-its.h
>> @@ -87,6 +87,9 @@
>> #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
>> +#define GITS_MAX_DEVICES 8
>> +#define GITS_MAX_COLLECTIONS 8
>> +
>> struct its_typer {
>> unsigned int ite_size;
>> unsigned int eventid_bits;
>> @@ -117,6 +120,17 @@ struct its_cmd_block {
>> u64 raw_cmd[4];
>> };
>> +struct its_device {
>> + u32 device_id; /* device ID */
>> + u32 nr_ites; /* Max Interrupt Translation Entries */
>> + void *itt; /* Interrupt Translation Table GPA */
>> +};
>> +
>> +struct its_collection {
>> + u64 target_address;
>> + u16 col_id;
>> +};
>> +
>> struct its_data {
>> void *base;
>> struct its_typer typer;
>> @@ -124,6 +138,10 @@ struct its_data {
>> struct its_cmd_block *cmd_base;
>> struct its_cmd_block *cmd_write;
>> struct its_cmd_block *cmd_readr;
>> + struct its_device devices[GITS_MAX_DEVICES];
>> + u32 nb_devices; /* Allocated Devices */
>> + struct its_collection collections[GITS_MAX_COLLECTIONS];
>> + u32 nb_collections; /* Allocated Collections */
>
> ('nr_*' may be the more widely used one.)
>
>> };
>> extern struct its_data its_data;
>> @@ -140,6 +158,8 @@ extern u8 get_lpi_config(int n);
>> extern void set_pending_table_bit(int rdist, int n, bool set);
>> extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set);
>> extern void its_enable_defaults(void);
>> +extern struct its_device *its_create_device(u32 dev_id, int nr_ites);
>> +extern struct its_collection *its_create_collection(u32 col_id, u32
>> target_pe);
>> #endif /* !__ASSEMBLY__ */
>> #endif /* _ASMARM_GIC_V3_ITS_H_ */
>> diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
>> index 9a51ef4..9906428 100644
>> --- a/lib/arm/gic-v3-its.c
>> +++ b/lib/arm/gic-v3-its.c
>> @@ -284,3 +284,49 @@ void its_enable_defaults(void)
>> writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR);
>> }
>> +
>> +struct its_device *its_create_device(u32 device_id, int nr_ites)
>> +{
>> + struct its_baser *baser;
>> + struct its_device *new;
>> + unsigned long n, order;
>> +
>> + if (its_data.nb_devices >= GITS_MAX_DEVICES)
>> + report_abort("%s redimension GITS_MAX_DEVICES", __func__);
>> +
>> + baser = its_lookup_baser(GITS_BASER_TYPE_DEVICE);
>> + if (!baser)
>> + return NULL;
>> +
>> + new = &its_data.devices[its_data.nb_devices];
>> +
>> + new->device_id = device_id;
>> + new->nr_ites = nr_ites;
>> +
>> + n = (baser->esz * nr_ites) >> PAGE_SHIFT;
>
> baser->esz is GITS_BASER.Entry_Size, which indicates the size of
> Device Table entry.
> We're allocating ITT for this device now, shouldn't we use
> its_data.typer.esz?
Yes you're definitively right. I should use its_data.typer.ite_size.
Thank you!
Eric
>
>
> Thanks,
> Zenghui
>
>> + order = is_power_of_2(n) ? fls(n) : fls(n) + 1;
>> + new->itt = (void *)virt_to_phys(alloc_pages(order));
>> +
>> + its_data.nb_devices++;
>> + return new;
>> +}
>> +
>> +struct its_collection *its_create_collection(u32 col_id, u32 pe)
>> +{
>> + struct its_collection *new;
>> +
>> + if (its_data.nb_collections >= GITS_MAX_COLLECTIONS)
>> + report_abort("%s redimension GITS_MAX_COLLECTIONS", __func__);
>> +
>> + new = &its_data.collections[its_data.nb_collections];
>> +
>> + new->col_id = col_id;
>> +
>> + if (its_data.typer.pta)
>> + new->target_address = (u64)gicv3_data.redist_base[pe];
>> + else
>> + new->target_address = pe << 16;
>> +
>> + its_data.nb_collections++;
>> + return new;
>> +}
>>
>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [kvm-unit-tests PATCH 12/16] arm/arm64: ITS: commands
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (10 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 11/16] arm/arm64: ITS: Device and collection Initialization Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-20 7:29 ` Zenghui Yu
2019-12-16 14:02 ` [kvm-unit-tests PATCH 13/16] arm/arm64: ITS: INT functional tests Eric Auger
` (3 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Implement main ITS commands. The code is largely inherited from
the ITS driver.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
arm/Makefile.common | 2 +-
lib/arm/asm/gic-v3-its.h | 36 +++
lib/arm/gic-v3-its-cmd.c | 462 +++++++++++++++++++++++++++++++++++++++
3 files changed, 499 insertions(+), 1 deletion(-)
create mode 100644 lib/arm/gic-v3-its-cmd.c
diff --git a/arm/Makefile.common b/arm/Makefile.common
index 1aae5a3..7cc0f04 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -52,7 +52,7 @@ cflatobjs += lib/arm/psci.o
cflatobjs += lib/arm/smp.o
cflatobjs += lib/arm/delay.o
cflatobjs += lib/arm/gic.o lib/arm/gic-v2.o lib/arm/gic-v3.o
-cflatobjs += lib/arm/gic-v3-its.o
+cflatobjs += lib/arm/gic-v3-its.o lib/arm/gic-v3-its-cmd.o
OBJDIRS += lib/arm
diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
index 245ef61..d074c17 100644
--- a/lib/arm/asm/gic-v3-its.h
+++ b/lib/arm/asm/gic-v3-its.h
@@ -90,6 +90,24 @@
#define GITS_MAX_DEVICES 8
#define GITS_MAX_COLLECTIONS 8
+/*
+ * ITS commands
+ */
+#define GITS_CMD_MAPD 0x08
+#define GITS_CMD_MAPC 0x09
+#define GITS_CMD_MAPTI 0x0a
+/* older GIC documentation used MAPVI for this command */
+#define GITS_CMD_MAPVI GITS_CMD_MAPTI
+#define GITS_CMD_MAPI 0x0b
+#define GITS_CMD_MOVI 0x01
+#define GITS_CMD_DISCARD 0x0f
+#define GITS_CMD_INV 0x0c
+#define GITS_CMD_MOVALL 0x0e
+#define GITS_CMD_INVALL 0x0d
+#define GITS_CMD_INT 0x03
+#define GITS_CMD_CLEAR 0x04
+#define GITS_CMD_SYNC 0x05
+
struct its_typer {
unsigned int ite_size;
unsigned int eventid_bits;
@@ -161,5 +179,23 @@ extern void its_enable_defaults(void);
extern struct its_device *its_create_device(u32 dev_id, int nr_ites);
extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe);
+extern void its_send_mapd(struct its_device *dev, int valid);
+extern void its_send_mapc(struct its_collection *col, int valid);
+extern void its_send_mapti(struct its_device *dev, u32 irq_id,
+ u32 event_id, struct its_collection *col);
+extern void its_send_int(struct its_device *dev, u32 event_id);
+extern void its_send_inv(struct its_device *dev, u32 event_id);
+extern void its_send_discard(struct its_device *dev, u32 event_id);
+extern void its_send_clear(struct its_device *dev, u32 event_id);
+extern void its_send_invall(struct its_collection *col);
+extern void its_send_movi(struct its_device *dev,
+ struct its_collection *col, u32 id);
+extern void its_send_sync(struct its_collection *col);
+extern void its_print_cmd_state(void);
+
+#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
+#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
+#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASMARM_GIC_V3_ITS_H_ */
diff --git a/lib/arm/gic-v3-its-cmd.c b/lib/arm/gic-v3-its-cmd.c
new file mode 100644
index 0000000..4c326cd
--- /dev/null
+++ b/lib/arm/gic-v3-its-cmd.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright (C) 2016, Red Hat Inc, Eric Auger <eric.auger@redhat.com>
+ *
+ * Most of the code is copy-pasted from:
+ * drivers/irqchip/irq-gic-v3-its.c
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include <asm/io.h>
+#include <asm/gic.h>
+
+#define ITS_ITT_ALIGN SZ_256
+
+static const char * const its_cmd_string[] = {
+ [GITS_CMD_MAPD] = "MAPD",
+ [GITS_CMD_MAPC] = "MAPC",
+ [GITS_CMD_MAPTI] = "MAPTI",
+ [GITS_CMD_MAPI] = "MAPI",
+ [GITS_CMD_MOVI] = "MOVI",
+ [GITS_CMD_DISCARD] = "DISCARD",
+ [GITS_CMD_INV] = "INV",
+ [GITS_CMD_MOVALL] = "MOVALL",
+ [GITS_CMD_INVALL] = "INVALL",
+ [GITS_CMD_INT] = "INT",
+ [GITS_CMD_CLEAR] = "CLEAR",
+ [GITS_CMD_SYNC] = "SYNC",
+};
+
+struct its_cmd_desc {
+ union {
+ struct {
+ struct its_device *dev;
+ u32 event_id;
+ } its_inv_cmd;
+
+ struct {
+ struct its_device *dev;
+ u32 event_id;
+ } its_int_cmd;
+
+ struct {
+ struct its_device *dev;
+ bool valid;
+ } its_mapd_cmd;
+
+ struct {
+ struct its_collection *col;
+ bool valid;
+ } its_mapc_cmd;
+
+ struct {
+ struct its_device *dev;
+ u32 phys_id;
+ u32 event_id;
+ u32 col_id;
+ } its_mapti_cmd;
+
+ struct {
+ struct its_device *dev;
+ struct its_collection *col;
+ u32 event_id;
+ } its_movi_cmd;
+
+ struct {
+ struct its_device *dev;
+ u32 event_id;
+ } its_discard_cmd;
+
+ struct {
+ struct its_device *dev;
+ u32 event_id;
+ } its_clear_cmd;
+
+ struct {
+ struct its_collection *col;
+ } its_invall_cmd;
+
+ struct {
+ struct its_collection *col;
+ } its_sync_cmd;
+ };
+};
+
+typedef void (*its_cmd_builder_t)(struct its_cmd_block *,
+ struct its_cmd_desc *);
+
+/* ITS COMMANDS */
+
+static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
+{
+ cmd->raw_cmd[0] &= ~0xffUL;
+ cmd->raw_cmd[0] |= cmd_nr;
+}
+
+static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
+{
+ cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
+ cmd->raw_cmd[0] |= ((u64)devid) << 32;
+}
+
+static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
+{
+ cmd->raw_cmd[1] &= ~0xffffffffUL;
+ cmd->raw_cmd[1] |= id;
+}
+
+static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
+{
+ cmd->raw_cmd[1] &= 0xffffffffUL;
+ cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
+}
+
+static void its_encode_size(struct its_cmd_block *cmd, u8 size)
+{
+ cmd->raw_cmd[1] &= ~0x1fUL;
+ cmd->raw_cmd[1] |= size & 0x1f;
+}
+
+static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
+{
+ cmd->raw_cmd[2] &= ~0xffffffffffffUL;
+ cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
+}
+
+static void its_encode_valid(struct its_cmd_block *cmd, int valid)
+{
+ cmd->raw_cmd[2] &= ~(1UL << 63);
+ cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
+}
+
+static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
+{
+ cmd->raw_cmd[2] &= ~(0xfffffffffUL << 16);
+ cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
+}
+
+static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
+{
+ cmd->raw_cmd[2] &= ~0xffffUL;
+ cmd->raw_cmd[2] |= col;
+}
+
+static inline void its_fixup_cmd(struct its_cmd_block *cmd)
+{
+ /* Let's fixup BE commands */
+ cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
+ cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
+ cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
+ cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
+}
+
+static u64 its_cmd_ptr_to_offset(struct its_cmd_block *ptr)
+{
+ return (ptr - its_data.cmd_base) * sizeof(*ptr);
+}
+
+static struct its_cmd_block *its_post_commands(void)
+{
+ u64 wr = its_cmd_ptr_to_offset(its_data.cmd_write);
+
+ writeq(wr, its_data.base + GITS_CWRITER);
+ return its_data.cmd_write;
+}
+
+
+/* We just assume the queue is large enough */
+static struct its_cmd_block *its_allocate_entry(void)
+{
+ struct its_cmd_block *cmd;
+
+ cmd = its_data.cmd_write++;
+ return cmd;
+}
+
+static void its_wait_for_range_completion(struct its_cmd_block *from,
+ struct its_cmd_block *to)
+{
+ u64 rd_idx, from_idx, to_idx;
+ u32 count = 1000000; /* 1s! */
+
+ from_idx = its_cmd_ptr_to_offset(from);
+ to_idx = its_cmd_ptr_to_offset(to);
+ while (1) {
+ rd_idx = readq(its_data.base + GITS_CREADR);
+ if (rd_idx >= to_idx || rd_idx < from_idx)
+ break;
+
+ count--;
+ if (!count) {
+ unsigned int cmd_id = from->raw_cmd[0] & 0xFF;
+
+ report(false, "%s timeout!",
+ cmd_id <= 0xF ? its_cmd_string[cmd_id] :
+ "Unexpected");
+ return;
+ }
+ cpu_relax();
+ udelay(1);
+ }
+}
+
+void its_print_cmd_state(void)
+{
+ u64 rd, wr;
+
+ rd = readq(its_data.base + GITS_CREADR);
+ wr = readq(its_data.base + GITS_CWRITER);
+ report_info("GITS_CREADR=0x%lx GITS_CWRITER=0x%lx", rd, wr);
+}
+
+static void its_send_single_command(its_cmd_builder_t builder,
+ struct its_cmd_desc *desc)
+{
+ struct its_cmd_block *cmd, *next_cmd;
+
+ cmd = its_allocate_entry();
+ builder(cmd, desc);
+ next_cmd = its_post_commands();
+
+ its_wait_for_range_completion(cmd, next_cmd);
+}
+
+
+static void its_build_mapd_cmd(struct its_cmd_block *cmd,
+ struct its_cmd_desc *desc)
+{
+ unsigned long itt_addr;
+ u8 size = 12; //TODO ilog2(desc->its_mapd_cmd.dev->nr_ites);
+
+ itt_addr = (unsigned long)desc->its_mapd_cmd.dev->itt;
+ itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
+
+ its_encode_cmd(cmd, GITS_CMD_MAPD);
+ its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
+ its_encode_size(cmd, size - 1);
+ its_encode_itt(cmd, itt_addr);
+ its_encode_valid(cmd, desc->its_mapd_cmd.valid);
+
+ its_fixup_cmd(cmd);
+ report_info("MAPD devid=%d size = 0x%x itt=0x%lx valid=%d",
+ desc->its_mapd_cmd.dev->device_id,
+ size, itt_addr, desc->its_mapd_cmd.valid);
+
+}
+
+static void its_build_mapc_cmd(struct its_cmd_block *cmd,
+ struct its_cmd_desc *desc)
+{
+ its_encode_cmd(cmd, GITS_CMD_MAPC);
+ its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
+ its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
+ its_encode_valid(cmd, desc->its_mapc_cmd.valid);
+
+ its_fixup_cmd(cmd);
+ report_info("MAPC col_id=%d target_addr = 0x%lx valid=%d",
+ desc->its_mapc_cmd.col->col_id,
+ desc->its_mapc_cmd.col->target_address,
+ desc->its_mapc_cmd.valid);
+}
+
+static void its_build_mapti_cmd(struct its_cmd_block *cmd,
+ struct its_cmd_desc *desc)
+{
+ its_encode_cmd(cmd, GITS_CMD_MAPTI);
+ its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
+ its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
+ its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
+ its_encode_collection(cmd, desc->its_mapti_cmd.col_id);
+
+ its_fixup_cmd(cmd);
+ report_info("MAPTI dev_id=%d event_id=%d -> phys_id=%d, col_id=%d",
+ desc->its_mapti_cmd.dev->device_id,
+ desc->its_mapti_cmd.event_id,
+ desc->its_mapti_cmd.phys_id,
+ desc->its_mapti_cmd.col_id);
+}
+
+static void its_build_invall_cmd(struct its_cmd_block *cmd,
+ struct its_cmd_desc *desc)
+{
+ its_encode_cmd(cmd, GITS_CMD_INVALL);
+ its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
+
+ its_fixup_cmd(cmd);
+ report_info("INVALL col_id=%d", desc->its_invall_cmd.col->col_id);
+}
+
+static void its_build_clear_cmd(struct its_cmd_block *cmd,
+ struct its_cmd_desc *desc)
+{
+ its_encode_cmd(cmd, GITS_CMD_CLEAR);
+ its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
+ its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
+
+ its_fixup_cmd(cmd);
+ report_info("CLEAR col_id=%d", desc->its_invall_cmd.col->col_id);
+}
+
+static void its_build_discard_cmd(struct its_cmd_block *cmd,
+ struct its_cmd_desc *desc)
+{
+ its_encode_cmd(cmd, GITS_CMD_DISCARD);
+ its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
+ its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
+
+ its_fixup_cmd(cmd);
+ report_info("DISCARD col_id=%d", desc->its_invall_cmd.col->col_id);
+}
+
+static void its_build_inv_cmd(struct its_cmd_block *cmd,
+ struct its_cmd_desc *desc)
+{
+ its_encode_cmd(cmd, GITS_CMD_INV);
+ its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
+ its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
+
+ its_fixup_cmd(cmd);
+ report_info("INV dev_id=%d event_id=%d",
+ desc->its_inv_cmd.dev->device_id,
+ desc->its_inv_cmd.event_id);
+}
+
+static void its_build_int_cmd(struct its_cmd_block *cmd,
+ struct its_cmd_desc *desc)
+{
+ its_encode_cmd(cmd, GITS_CMD_INT);
+ its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
+ its_encode_event_id(cmd, desc->its_int_cmd.event_id);
+
+ its_fixup_cmd(cmd);
+ report_info("INT dev_id=%d event_id=%d",
+ desc->its_int_cmd.dev->device_id,
+ desc->its_int_cmd.event_id);
+}
+
+static void its_build_sync_cmd(struct its_cmd_block *cmd,
+ struct its_cmd_desc *desc)
+{
+ its_encode_cmd(cmd, GITS_CMD_SYNC);
+ its_encode_target(cmd, desc->its_sync_cmd.col->target_address);
+ its_fixup_cmd(cmd);
+ report_info("SYNC target_addr = 0x%lx",
+ desc->its_sync_cmd.col->target_address);
+}
+
+static void its_build_movi_cmd(struct its_cmd_block *cmd,
+ struct its_cmd_desc *desc)
+{
+ its_encode_cmd(cmd, GITS_CMD_MOVI);
+ its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
+ its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
+ its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
+
+ its_fixup_cmd(cmd);
+ report_info("MOVI dev_id=%d event_id = %d col_id=%d",
+ desc->its_movi_cmd.dev->device_id,
+ desc->its_movi_cmd.event_id,
+ desc->its_movi_cmd.col->col_id);
+}
+
+void its_send_mapd(struct its_device *dev, int valid)
+{
+ struct its_cmd_desc desc;
+
+ desc.its_mapd_cmd.dev = dev;
+ desc.its_mapd_cmd.valid = !!valid;
+
+ its_send_single_command(its_build_mapd_cmd, &desc);
+}
+
+void its_send_mapc(struct its_collection *col, int valid)
+{
+ struct its_cmd_desc desc;
+
+ desc.its_mapc_cmd.col = col;
+ desc.its_mapc_cmd.valid = !!valid;
+
+ its_send_single_command(its_build_mapc_cmd, &desc);
+}
+
+void its_send_mapti(struct its_device *dev, u32 irq_id,
+ u32 event_id, struct its_collection *col)
+{
+ struct its_cmd_desc desc;
+
+ desc.its_mapti_cmd.dev = dev;
+ desc.its_mapti_cmd.phys_id = irq_id;
+ desc.its_mapti_cmd.event_id = event_id;
+ desc.its_mapti_cmd.col_id = col->col_id;
+
+ its_send_single_command(its_build_mapti_cmd, &desc);
+}
+
+void its_send_int(struct its_device *dev, u32 event_id)
+{
+ struct its_cmd_desc desc;
+
+ desc.its_int_cmd.dev = dev;
+ desc.its_int_cmd.event_id = event_id;
+
+ its_send_single_command(its_build_int_cmd, &desc);
+}
+
+void its_send_movi(struct its_device *dev,
+ struct its_collection *col, u32 id)
+{
+ struct its_cmd_desc desc;
+
+ desc.its_movi_cmd.dev = dev;
+ desc.its_movi_cmd.col = col;
+ desc.its_movi_cmd.event_id = id;
+
+ its_send_single_command(its_build_movi_cmd, &desc);
+}
+
+void its_send_invall(struct its_collection *col)
+{
+ struct its_cmd_desc desc;
+
+ desc.its_invall_cmd.col = col;
+
+ its_send_single_command(its_build_invall_cmd, &desc);
+}
+
+void its_send_inv(struct its_device *dev, u32 event_id)
+{
+ struct its_cmd_desc desc;
+
+ desc.its_inv_cmd.dev = dev;
+ desc.its_inv_cmd.event_id = event_id;
+
+ its_send_single_command(its_build_inv_cmd, &desc);
+}
+
+void its_send_discard(struct its_device *dev, u32 event_id)
+{
+ struct its_cmd_desc desc;
+
+ desc.its_discard_cmd.dev = dev;
+ desc.its_discard_cmd.event_id = event_id;
+
+ its_send_single_command(its_build_discard_cmd, &desc);
+}
+
+void its_send_clear(struct its_device *dev, u32 event_id)
+{
+ struct its_cmd_desc desc;
+
+ desc.its_clear_cmd.dev = dev;
+ desc.its_clear_cmd.event_id = event_id;
+
+ its_send_single_command(its_build_clear_cmd, &desc);
+}
+
+void its_send_sync(struct its_collection *col)
+{
+ struct its_cmd_desc desc;
+
+ desc.its_sync_cmd.col = col;
+
+ its_send_single_command(its_build_sync_cmd, &desc);
+}
+
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 12/16] arm/arm64: ITS: commands
2019-12-16 14:02 ` [kvm-unit-tests PATCH 12/16] arm/arm64: ITS: commands Eric Auger
@ 2019-12-20 7:29 ` Zenghui Yu
0 siblings, 0 replies; 28+ messages in thread
From: Zenghui Yu @ 2019-12-20 7:29 UTC (permalink / raw)
To: Eric Auger, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Hi Eric,
On 2019/12/16 22:02, Eric Auger wrote:
> Implement main ITS commands. The code is largely inherited from
> the ITS driver.
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> ---
[...]
> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
> index 245ef61..d074c17 100644
> --- a/lib/arm/asm/gic-v3-its.h
> +++ b/lib/arm/asm/gic-v3-its.h
> @@ -161,5 +179,23 @@ extern void its_enable_defaults(void);
> extern struct its_device *its_create_device(u32 dev_id, int nr_ites);
> extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe);
>
> +extern void its_send_mapd(struct its_device *dev, int valid);
> +extern void its_send_mapc(struct its_collection *col, int valid);
> +extern void its_send_mapti(struct its_device *dev, u32 irq_id,
> + u32 event_id, struct its_collection *col);
> +extern void its_send_int(struct its_device *dev, u32 event_id);
> +extern void its_send_inv(struct its_device *dev, u32 event_id);
> +extern void its_send_discard(struct its_device *dev, u32 event_id);
> +extern void its_send_clear(struct its_device *dev, u32 event_id);
> +extern void its_send_invall(struct its_collection *col);
> +extern void its_send_movi(struct its_device *dev,
> + struct its_collection *col, u32 id);
> +extern void its_send_sync(struct its_collection *col);
> +extern void its_print_cmd_state(void);
This function is not used by later patches, I guess it's mostly used
for debug.
(Assuming the Linux ITS driver has done the right thing ;-), I just skip
looking at this patch.)
Thanks,
Zenghui
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [kvm-unit-tests PATCH 13/16] arm/arm64: ITS: INT functional tests
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (11 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 12/16] arm/arm64: ITS: commands Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 14/16] arm/run: Allow Migration tests Eric Auger
` (2 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Triggers LPIs through the INT command.
the test checks the LPI hits the right CPU and triggers
the right LPI intid, ie. the translation is correct.
Updates to the config table also are tested, along with inv
and invall commands.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
arm/gic.c | 174 +++++++++++++++++++++++++++++++++++++++
arm/unittests.cfg | 6 ++
lib/arm/asm/gic-v3-its.h | 14 ++++
3 files changed, 194 insertions(+)
diff --git a/arm/gic.c b/arm/gic.c
index 8b56fce..6b73258 100644
--- a/arm/gic.c
+++ b/arm/gic.c
@@ -34,6 +34,7 @@ static struct gic *gic;
static int acked[NR_CPUS], spurious[NR_CPUS];
static int bad_sender[NR_CPUS], bad_irq[NR_CPUS];
static cpumask_t ready;
+static struct its_stats lpi_stats;
static void nr_cpu_check(int nr)
{
@@ -158,6 +159,54 @@ static void ipi_handler(struct pt_regs *regs __unused)
}
}
+static void lpi_handler(struct pt_regs *regs __unused)
+{
+ u32 irqstat = gic_read_iar();
+ int irqnr = gic_iar_irqnr(irqstat);
+
+ gic_write_eoir(irqstat);
+ if (irqnr < 8192)
+ report(false, "Unexpected non LPI interrupt received");
+ smp_rmb(); /* pairs with wmb in lpi_stats_expect */
+ lpi_stats.observed.cpu_id = smp_processor_id();
+ lpi_stats.observed.lpi_id = irqnr;
+ smp_wmb(); /* pairs with rmb in check_lpi_stats */
+}
+
+static void lpi_stats_expect(int exp_cpu_id, int exp_lpi_id)
+{
+ lpi_stats.expected.cpu_id = exp_cpu_id;
+ lpi_stats.expected.lpi_id = exp_lpi_id;
+ lpi_stats.observed.cpu_id = -1;
+ lpi_stats.observed.lpi_id = -1;
+ smp_wmb(); /* pairs with rmb in handler */
+}
+
+static void check_lpi_stats(void)
+{
+ mdelay(100);
+ smp_rmb(); /* pairs with wmb in lpi_handler */
+ if ((lpi_stats.observed.cpu_id != lpi_stats.expected.cpu_id) ||
+ (lpi_stats.observed.lpi_id != lpi_stats.expected.lpi_id)) {
+ if (lpi_stats.observed.cpu_id == -1 &&
+ lpi_stats.observed.lpi_id == -1) {
+ report(false,
+ "No LPI received whereas (cpuid=%d, intid=%d) "
+ "was expected", lpi_stats.expected.cpu_id,
+ lpi_stats.expected.lpi_id);
+ } else {
+ report(false, "Unexpected LPI (cpuid=%d, intid=%d)",
+ lpi_stats.observed.cpu_id,
+ lpi_stats.observed.lpi_id);
+ }
+ } else if (lpi_stats.expected.lpi_id != -1) {
+ report(true, "LPI %d on CPU %d", lpi_stats.observed.lpi_id,
+ lpi_stats.observed.cpu_id);
+ } else {
+ report(true, "no LPI received, as expected");
+ }
+}
+
static void gicv2_ipi_send_self(void)
{
writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR);
@@ -241,6 +290,14 @@ static void ipi_test(void *data __unused)
ipi_recv();
}
+static void secondary_lpi_test(void)
+{
+ setup_irq(lpi_handler);
+ cpumask_set_cpu(smp_processor_id(), &ready);
+ while (1)
+ wfi();
+}
+
static struct gic gicv2 = {
.ipi = {
.send_self = gicv2_ipi_send_self,
@@ -552,6 +609,120 @@ static void test_its_baser(void)
report_info("collection baser entry_size = 0x%x", dev_baser->esz);
}
+static int its_prerequisites(int nb_cpus)
+{
+ int cpu;
+
+ if (!gicv3_its_base()) {
+ report_skip("No ITS, skip ...");
+ return -1;
+ }
+
+ if (nr_cpus < 4) {
+ report_skip("Test requires at least %d vcpus", nb_cpus);
+ return -1;
+ }
+
+ stats_reset();
+
+ setup_irq(lpi_handler);
+
+ for_each_present_cpu(cpu) {
+ if (cpu == 0)
+ continue;
+ smp_boot_secondary(cpu, secondary_lpi_test);
+ }
+ wait_on_ready();
+
+ its_enable_defaults();
+
+ lpi_stats_expect(-1, -1);
+ check_lpi_stats();
+
+ return 0;
+}
+
+static void test_its_trigger(void)
+{
+ struct its_collection *col3, *col2;
+ struct its_device *dev2, *dev7;
+
+ if (its_prerequisites(4))
+ return;
+
+ dev2 = its_create_device(2 /* dev id */, 8 /* nb_ites */);
+ dev7 = its_create_device(7 /* dev id */, 8 /* nb_ites */);
+
+ col3 = its_create_collection(3 /* col id */, 3/* target PE */);
+ col2 = its_create_collection(2 /* col id */, 2/* target PE */);
+
+ set_lpi_config(8195, LPI_PROP_DEFAULT);
+ set_lpi_config(8196, LPI_PROP_DEFAULT);
+
+ its_send_invall(col2);
+ its_send_invall(col3);
+
+ report_prefix_push("int");
+
+ its_send_mapd(dev2, true);
+ its_send_mapd(dev7, true);
+
+ its_send_mapc(col3, true);
+ its_send_mapc(col2, true);
+
+ its_send_mapti(dev2, 8195 /* lpi id */,
+ 20 /* event id */, col3);
+ its_send_mapti(dev7, 8196 /* lpi id */,
+ 255 /* event id */, col2);
+
+ lpi_stats_expect(3, 8195);
+ its_send_int(dev2, 20);
+ check_lpi_stats();
+
+ lpi_stats_expect(2, 8196);
+ its_send_int(dev7, 255);
+ check_lpi_stats();
+
+ report_prefix_pop();
+
+ report_prefix_push("inv/invall");
+
+ /* disable 8195 */
+ set_lpi_config(8195, LPI_PROP_DEFAULT & ~0x1);
+ its_send_inv(dev2, 20);
+
+ lpi_stats_expect(-1, -1);
+ its_send_int(dev2, 20);
+ check_lpi_stats();
+
+ set_lpi_config(8195, LPI_PROP_DEFAULT);
+ /* willingly forget the INVALL*/
+ lpi_stats_expect(-1, -1);
+ its_send_int(dev2, 20);
+ check_lpi_stats();
+
+ its_send_invall(col3);
+ lpi_stats_expect(3, 8195);
+ its_send_int(dev2, 20);
+ check_lpi_stats();
+
+ report_prefix_pop();
+
+ report_prefix_push("mapd valid=false");
+ its_send_mapd(dev2, false);
+ lpi_stats_expect(-1, -1);
+ its_send_int(dev2, 20);
+ check_lpi_stats();
+ report_prefix_pop();
+
+ report_prefix_push("mapc valid=false");
+ its_send_mapc(col2, false);
+ lpi_stats_expect(-1, -1);
+ its_send_int(dev7, 255);
+ check_lpi_stats();
+}
+
+
int main(int argc, char **argv)
{
if (!gic_init()) {
@@ -582,6 +753,9 @@ int main(int argc, char **argv)
} else if (strcmp(argv[1], "mmio") == 0) {
report_prefix_push(argv[1]);
gic_test_mmio();
+ } else if (!strcmp(argv[1], "its-trigger")) {
+ report_prefix_push(argv[1]);
+ test_its_trigger();
report_prefix_pop();
} else if (strcmp(argv[1], "its-introspection") == 0) {
report_prefix_push(argv[1]);
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 2234a0f..80a1d27 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -134,6 +134,12 @@ smp = $MAX_SMP
extra_params = -machine gic-version=3 -append 'its-baser'
groups = its
+[its-trigger]
+file = gic.flat
+smp = $MAX_SMP
+extra_params = -machine gic-version=3 -append 'its-trigger'
+groups = its
+
# Test PSCI emulation
[psci]
file = psci.flat
diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
index d074c17..d4fd799 100644
--- a/lib/arm/asm/gic-v3-its.h
+++ b/lib/arm/asm/gic-v3-its.h
@@ -162,6 +162,16 @@ struct its_data {
u32 nb_collections; /* Allocated Collections */
};
+struct its_event {
+ int cpu_id;
+ int lpi_id;
+};
+
+struct its_stats {
+ struct its_event expected;
+ struct its_event observed;
+};
+
extern struct its_data its_data;
#define gicv3_its_base() (its_data.base)
@@ -178,6 +188,10 @@ extern void gicv3_rdist_ctrl_lpi(u32 redist, bool set);
extern void its_enable_defaults(void);
extern struct its_device *its_create_device(u32 dev_id, int nr_ites);
extern struct its_collection *its_create_collection(u32 col_id, u32 target_pe);
+extern struct its_collection *its_create_collection(u32 col_id, u32 target);
+
+extern void set_lpi_config(int n, u8 val);
+extern u8 get_lpi_config(int n);
extern void its_send_mapd(struct its_device *dev, int valid);
extern void its_send_mapc(struct its_collection *col, int valid);
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* [kvm-unit-tests PATCH 14/16] arm/run: Allow Migration tests
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (12 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 13/16] arm/arm64: ITS: INT functional tests Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2020-01-07 7:39 ` Thomas Huth
2019-12-16 14:02 ` [kvm-unit-tests PATCH 15/16] arm/arm64: ITS: migration tests Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 16/16] arm/arm64: ITS: pending table migration test Eric Auger
15 siblings, 1 reply; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Let's link getchar.o to use puts and getchar from the
tests.
Then allow tests belonging to the migration group to
trigger the migration from the test code by putting
"migrate" into the uart. Then the code can wait for the
migration completion by using getchar().
The __getchar implement is minimalist as it just reads the
data register. It is just meant to read the single character
emitted at the end of the migration by the runner script.
It is not meant to read more data (FIFOs are not enabled).
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
arm/Makefile.common | 2 +-
arm/run | 2 +-
lib/arm/io.c | 13 +++++++++++++
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arm/Makefile.common b/arm/Makefile.common
index 7cc0f04..327f112 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -32,7 +32,7 @@ CFLAGS += -I $(SRCDIR)/lib -I $(SRCDIR)/lib/libfdt -I lib
asm-offsets = lib/$(ARCH)/asm-offsets.h
include $(SRCDIR)/scripts/asm-offsets.mak
-cflatobjs += lib/util.o
+cflatobjs += lib/util.o lib/getchar.o
cflatobjs += lib/alloc_phys.o
cflatobjs += lib/alloc_page.o
cflatobjs += lib/vmalloc.o
diff --git a/arm/run b/arm/run
index 277db9b..a390ca5 100755
--- a/arm/run
+++ b/arm/run
@@ -61,6 +61,6 @@ fi
M+=",accel=$ACCEL"
command="$qemu -nodefaults $M -cpu $processor $chr_testdev $pci_testdev"
command+=" -display none -serial stdio -kernel"
-command="$(timeout_cmd) $command"
+command="$(migration_cmd) $(timeout_cmd) $command"
run_qemu $command "$@"
diff --git a/lib/arm/io.c b/lib/arm/io.c
index 99fd315..aa9e1b5 100644
--- a/lib/arm/io.c
+++ b/lib/arm/io.c
@@ -87,6 +87,19 @@ void puts(const char *s)
spin_unlock(&uart_lock);
}
+/*
+ * Minimalist implementation for migration completion detection.
+ * Needs to be improved for more advanced Rx cases
+ */
+int __getchar(void)
+{
+ int ret;
+
+ ret = readb(uart0_base);
+ if (!ret)
+ return -1;
+ return ret;
+}
/*
* Defining halt to take 'code' as an argument guarantees that it will
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [kvm-unit-tests PATCH 14/16] arm/run: Allow Migration tests
2019-12-16 14:02 ` [kvm-unit-tests PATCH 14/16] arm/run: Allow Migration tests Eric Auger
@ 2020-01-07 7:39 ` Thomas Huth
0 siblings, 0 replies; 28+ messages in thread
From: Thomas Huth @ 2020-01-07 7:39 UTC (permalink / raw)
To: Eric Auger, eric.auger.pro, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara
On 16/12/2019 15.02, Eric Auger wrote:
> Let's link getchar.o to use puts and getchar from the
> tests.
>
> Then allow tests belonging to the migration group to
> trigger the migration from the test code by putting
> "migrate" into the uart. Then the code can wait for the
> migration completion by using getchar().
>
> The __getchar implement is minimalist as it just reads the
> data register. It is just meant to read the single character
> emitted at the end of the migration by the runner script.
>
> It is not meant to read more data (FIFOs are not enabled).
>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> ---
> arm/Makefile.common | 2 +-
> arm/run | 2 +-
> lib/arm/io.c | 13 +++++++++++++
> 3 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/arm/Makefile.common b/arm/Makefile.common
> index 7cc0f04..327f112 100644
> --- a/arm/Makefile.common
> +++ b/arm/Makefile.common
> @@ -32,7 +32,7 @@ CFLAGS += -I $(SRCDIR)/lib -I $(SRCDIR)/lib/libfdt -I lib
> asm-offsets = lib/$(ARCH)/asm-offsets.h
> include $(SRCDIR)/scripts/asm-offsets.mak
>
> -cflatobjs += lib/util.o
> +cflatobjs += lib/util.o lib/getchar.o
> cflatobjs += lib/alloc_phys.o
> cflatobjs += lib/alloc_page.o
> cflatobjs += lib/vmalloc.o
> diff --git a/arm/run b/arm/run
> index 277db9b..a390ca5 100755
> --- a/arm/run
> +++ b/arm/run
> @@ -61,6 +61,6 @@ fi
> M+=",accel=$ACCEL"
> command="$qemu -nodefaults $M -cpu $processor $chr_testdev $pci_testdev"
> command+=" -display none -serial stdio -kernel"
> -command="$(timeout_cmd) $command"
> +command="$(migration_cmd) $(timeout_cmd) $command"
>
> run_qemu $command "$@"
> diff --git a/lib/arm/io.c b/lib/arm/io.c
> index 99fd315..aa9e1b5 100644
> --- a/lib/arm/io.c
> +++ b/lib/arm/io.c
> @@ -87,6 +87,19 @@ void puts(const char *s)
> spin_unlock(&uart_lock);
> }
>
> +/*
> + * Minimalist implementation for migration completion detection.
> + * Needs to be improved for more advanced Rx cases
> + */
> +int __getchar(void)
> +{
> + int ret;
> +
> + ret = readb(uart0_base);
Duplicated space before "readb"...
> + if (!ret)
> + return -1;
> + return ret;
> +}
>
> /*
> * Defining halt to take 'code' as an argument guarantees that it will
>
... but apart from that nit:
Reviewed-by: Thomas Huth <thuth@redhat.com>
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [kvm-unit-tests PATCH 15/16] arm/arm64: ITS: migration tests
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (13 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 14/16] arm/run: Allow Migration tests Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
2019-12-16 14:02 ` [kvm-unit-tests PATCH 16/16] arm/arm64: ITS: pending table migration test Eric Auger
15 siblings, 0 replies; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
This test maps LPIs (populates the device table, the collection table,
interrupt translation tables, configuration table), migrates and make
sure the translation is correct on the destination.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
arm/gic.c | 55 +++++++++++++++++++++++++++++++++++++---
arm/unittests.cfg | 7 +++++
lib/arm/asm/gic-v3-its.h | 2 ++
lib/arm/gic-v3-its.c | 22 ++++++++++++++++
4 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/arm/gic.c b/arm/gic.c
index 6b73258..8cca743 100644
--- a/arm/gic.c
+++ b/arm/gic.c
@@ -642,13 +642,19 @@ static int its_prerequisites(int nb_cpus)
return 0;
}
-static void test_its_trigger(void)
+/*
+ * Setup the configuration for those mappings:
+ * dev_id=2 event=20 -> vcpu 3, intid=8195
+ * dev_id=7 event=255 -> vcpu 2, intid=8196
+ * LPIs ready to hit
+ */
+static int its_setup1(void)
{
struct its_collection *col3, *col2;
struct its_device *dev2, *dev7;
if (its_prerequisites(4))
- return;
+ return -1;
dev2 = its_create_device(2 /* dev id */, 8 /* nb_ites */);
dev7 = its_create_device(7 /* dev id */, 8 /* nb_ites */);
@@ -662,8 +668,6 @@ static void test_its_trigger(void)
its_send_invall(col2);
its_send_invall(col3);
- report_prefix_push("int");
-
its_send_mapd(dev2, true);
its_send_mapd(dev7, true);
@@ -674,6 +678,23 @@ static void test_its_trigger(void)
20 /* event id */, col3);
its_send_mapti(dev7, 8196 /* lpi id */,
255 /* event id */, col2);
+ return 0;
+}
+
+static void test_its_trigger(void)
+{
+ struct its_collection *col3, *col2;
+ struct its_device *dev2, *dev7;
+
+ if (its_setup1())
+ return;
+
+ col3 = its_get_collection(3);
+ col2 = its_get_collection(2);
+ dev2 = its_get_device(2);
+ dev7 = its_get_device(7);
+
+ report_prefix_push("int");
lpi_stats_expect(3, 8195);
its_send_int(dev2, 20);
@@ -722,6 +743,28 @@ static void test_its_trigger(void)
check_lpi_stats();
}
+static void test_its_migration(void)
+{
+ struct its_device *dev2, *dev7;
+
+ if (its_setup1())
+ return;
+
+ dev2 = its_get_device(2);
+ dev7 = its_get_device(7);
+
+ puts("Now migrate the VM, then press a key to continue...\n");
+ (void)getchar();
+ report(true, "Migration complete");
+
+ lpi_stats_expect(3, 8195);
+ its_send_int(dev2, 20);
+ check_lpi_stats();
+
+ lpi_stats_expect(2, 8196);
+ its_send_int(dev7, 255);
+ check_lpi_stats();
+}
int main(int argc, char **argv)
{
@@ -757,6 +800,10 @@ int main(int argc, char **argv)
report_prefix_push(argv[1]);
test_its_trigger();
report_prefix_pop();
+ } else if (!strcmp(argv[1], "its-migration")) {
+ report_prefix_push(argv[1]);
+ test_its_migration();
+ report_prefix_pop();
} else if (strcmp(argv[1], "its-introspection") == 0) {
report_prefix_push(argv[1]);
test_its_introspection();
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 80a1d27..29e2efc 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -140,6 +140,13 @@ smp = $MAX_SMP
extra_params = -machine gic-version=3 -append 'its-trigger'
groups = its
+[its-migration]
+file = gic.flat
+smp = $MAX_SMP
+accel = kvm
+extra_params = -machine gic-version=3 -append 'its-migration'
+groups = its migration
+
# Test PSCI emulation
[psci]
file = psci.flat
diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
index d4fd799..c38d524 100644
--- a/lib/arm/asm/gic-v3-its.h
+++ b/lib/arm/asm/gic-v3-its.h
@@ -206,6 +206,8 @@ extern void its_send_movi(struct its_device *dev,
struct its_collection *col, u32 id);
extern void its_send_sync(struct its_collection *col);
extern void its_print_cmd_state(void);
+extern struct its_device *its_get_device(u32 id);
+extern struct its_collection *its_get_collection(u32 id);
#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
diff --git a/lib/arm/gic-v3-its.c b/lib/arm/gic-v3-its.c
index 9906428..e2e289c 100644
--- a/lib/arm/gic-v3-its.c
+++ b/lib/arm/gic-v3-its.c
@@ -330,3 +330,25 @@ struct its_collection *its_create_collection(u32 col_id, u32 pe)
its_data.nb_collections++;
return new;
}
+
+struct its_device *its_get_device(u32 id)
+{
+ int i;
+
+ for (i = 0; i < GITS_MAX_DEVICES; i++) {
+ if (its_data.devices[i].device_id == id)
+ return &its_data.devices[i];
+ }
+ return NULL;
+}
+
+struct its_collection *its_get_collection(u32 id)
+{
+ int i;
+
+ for (i = 0; i < GITS_MAX_COLLECTIONS; i++) {
+ if (its_data.collections[i].col_id == id)
+ return &its_data.collections[i];
+ }
+ return NULL;
+}
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* [kvm-unit-tests PATCH 16/16] arm/arm64: ITS: pending table migration test
2019-12-16 14:02 [kvm-unit-tests PATCH 00/16] arm/arm64: Add ITS tests Eric Auger
` (14 preceding siblings ...)
2019-12-16 14:02 ` [kvm-unit-tests PATCH 15/16] arm/arm64: ITS: migration tests Eric Auger
@ 2019-12-16 14:02 ` Eric Auger
15 siblings, 0 replies; 28+ messages in thread
From: Eric Auger @ 2019-12-16 14:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, maz, kvmarm, kvm, qemu-devel, qemu-arm
Cc: andre.przywara, thuth
Add two new migration tests. One testing the migration of
a topology where collection were unmapped. The second test
checks the migration of the pending table.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
arm/gic.c | 148 ++++++++++++++++++++++++++++++++++++++++++++++
arm/unittests.cfg | 16 ++++-
2 files changed, 163 insertions(+), 1 deletion(-)
diff --git a/arm/gic.c b/arm/gic.c
index 8cca743..fc8cf6e 100644
--- a/arm/gic.c
+++ b/arm/gic.c
@@ -170,6 +170,7 @@ static void lpi_handler(struct pt_regs *regs __unused)
smp_rmb(); /* pairs with wmb in lpi_stats_expect */
lpi_stats.observed.cpu_id = smp_processor_id();
lpi_stats.observed.lpi_id = irqnr;
+ acked[lpi_stats.observed.cpu_id]++;
smp_wmb(); /* pairs with rmb in check_lpi_stats */
}
@@ -207,6 +208,18 @@ static void check_lpi_stats(void)
}
}
+static void check_lpi_hits(int *expected)
+{
+ int i;
+
+ for (i = 0; i < nr_cpus; i++) {
+ if (acked[i] != expected[i])
+ report(false, "expected %d LPIs on PE #%d, %d observed",
+ expected[i], i, acked[i]);
+ }
+ report(true, "check LPI on all vcpus");
+}
+
static void gicv2_ipi_send_self(void)
{
writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR);
@@ -642,6 +655,18 @@ static int its_prerequisites(int nb_cpus)
return 0;
}
+static void set_lpi(struct its_device *dev, u32 eventid, u32 physid,
+ struct its_collection *col)
+{
+ if (!dev || !col)
+ report_abort("wrong device or collection");
+
+ its_send_mapti(dev, physid, eventid, col);
+
+ set_lpi_config(physid, LPI_PROP_DEFAULT);
+ its_send_invall(col);
+}
+
/*
* Setup the configuration for those mappings:
* dev_id=2 event=20 -> vcpu 3, intid=8195
@@ -766,6 +791,121 @@ static void test_its_migration(void)
check_lpi_stats();
}
+static void test_migrate_unmapped_collection(void)
+{
+ struct its_collection *col;
+ struct its_device *dev2, *dev7;
+ u8 config;
+
+ if (its_setup1())
+ return;
+
+ col = its_create_collection(nr_cpus - 1, nr_cpus - 1);
+ dev2 = its_get_device(2);
+ dev7 = its_get_device(7);
+
+ /* MAPTI with the collection unmapped */
+ set_lpi(dev2, 0, 8192, col);
+
+ puts("Now migrate the VM, then press a key to continue...\n");
+ (void)getchar();
+ report(true, "Migration complete");
+
+ /* on the destination, map the collection */
+ its_send_mapc(col, true);
+
+ lpi_stats_expect(2, 8196);
+ its_send_int(dev7, 255);
+ check_lpi_stats();
+
+ config = get_lpi_config(8192);
+ report(config == LPI_PROP_DEFAULT,
+ "Config of LPI 8192 was properly migrated");
+
+ lpi_stats_expect(nr_cpus - 1, 8192);
+ its_send_int(dev2, 0);
+ check_lpi_stats();
+
+ /* unmap the collection */
+ its_send_mapc(col, false);
+
+ lpi_stats_expect(-1, -1);
+ its_send_int(dev2, 0);
+ check_lpi_stats();
+
+ /* remap event 0 onto lpiid 8193 */
+ set_lpi(dev2, 0, 8193, col);
+ lpi_stats_expect(-1, -1);
+ its_send_int(dev2, 0);
+ check_lpi_stats();
+
+ /* remap the collection */
+ its_send_mapc(col, true);
+ lpi_stats_expect(nr_cpus - 1, 8193);
+}
+
+static void test_its_pending_migration(void)
+{
+ struct its_device *dev;
+ struct its_collection *collection[2];
+ int expected[NR_CPUS];
+ u64 pendbaser;
+ void *ptr;
+ int i;
+
+ if (its_prerequisites(4))
+ return;
+
+ dev = its_create_device(2 /* dev id */, 8 /* nb_ites */);
+ its_send_mapd(dev, true);
+
+ collection[0] = its_create_collection(nr_cpus - 1, nr_cpus - 1);
+ collection[1] = its_create_collection(nr_cpus - 2, nr_cpus - 2);
+ its_send_mapc(collection[0], true);
+ its_send_mapc(collection[1], true);
+
+ /* disable lpi at redist level */
+ gicv3_rdist_ctrl_lpi(nr_cpus - 1, false);
+ gicv3_rdist_ctrl_lpi(nr_cpus - 2, false);
+
+ /* even lpis are assigned to even cpu */
+ for (i = 0; i < 256; i++) {
+ struct its_collection *col = i % 2 ? collection[0] :
+ collection[1];
+ int vcpu = col->target_address >> 16;
+
+ its_send_mapti(dev, 8192 + i, i, col);
+ set_lpi_config(8192 + i, LPI_PROP_DEFAULT);
+ set_pending_table_bit(vcpu, 8192 + i, true);
+ }
+ its_send_invall(collection[0]);
+ its_send_invall(collection[1]);
+
+ /* Set the PTZ bit on each pendbaser */
+
+ expected[nr_cpus - 1] = 128;
+ expected[nr_cpus - 2] = 128;
+
+ ptr = gicv3_data.redist_base[nr_cpus - 1] + GICR_PENDBASER;
+ pendbaser = readq(ptr);
+ writeq(pendbaser & ~GICR_PENDBASER_PTZ, ptr);
+
+ ptr = gicv3_data.redist_base[nr_cpus - 2] + GICR_PENDBASER;
+ pendbaser = readq(ptr);
+ writeq(pendbaser & ~GICR_PENDBASER_PTZ, ptr);
+
+ gicv3_rdist_ctrl_lpi(nr_cpus - 1, true);
+ gicv3_rdist_ctrl_lpi(nr_cpus - 2, true);
+
+ puts("Now migrate the VM, then press a key to continue...\n");
+ (void)getchar();
+ report(true, "Migration complete");
+
+ mdelay(1000);
+
+ check_lpi_hits(expected);
+}
+
int main(int argc, char **argv)
{
if (!gic_init()) {
@@ -804,6 +944,14 @@ int main(int argc, char **argv)
report_prefix_push(argv[1]);
test_its_migration();
report_prefix_pop();
+ } else if (!strcmp(argv[1], "its-pending-migration")) {
+ report_prefix_push(argv[1]);
+ test_its_pending_migration();
+ report_prefix_pop();
+ } else if (!strcmp(argv[1], "its-migrate-unmapped-collection")) {
+ report_prefix_push(argv[1]);
+ test_migrate_unmapped_collection();
+ report_prefix_pop();
} else if (strcmp(argv[1], "its-introspection") == 0) {
report_prefix_push(argv[1]);
test_its_introspection();
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index 29e2efc..911f0b7 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -145,7 +145,21 @@ file = gic.flat
smp = $MAX_SMP
accel = kvm
extra_params = -machine gic-version=3 -append 'its-migration'
-groups = its migration
+groups = migration
+
+[its-pending-migration]
+file = gic.flat
+smp = $MAX_SMP
+accel = kvm
+extra_params = -machine gic-version=3 -append 'its-pending-migration'
+groups = migration
+
+[its-migrate-unmapped-collection]
+file = gic.flat
+smp = $MAX_SMP
+accel = kvm
+extra_params = -machine gic-version=3 -append 'its-migrate-unmapped-collection'
+groups = migration
# Test PSCI emulation
[psci]
--
2.20.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread