* [kvm-unit-tests PATCH 1/6] arm64: microbench: get correct ipi recieved num
2020-05-17 10:08 [kvm-unit-tests PATCH 0/6] arm64: add IPI/LPI/vtimer latency Jingyi Wang
@ 2020-05-17 10:08 ` Jingyi Wang
2020-05-21 14:00 ` Zenghui Yu
2020-05-17 10:08 ` [kvm-unit-tests PATCH 2/6] arm64: microbench: Use the funcions for ipi test as the general functions for gic(ipi/lpi/timer) test Jingyi Wang
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Jingyi Wang @ 2020-05-17 10:08 UTC (permalink / raw)
To: drjones, kvm, kvmarm, wangjingyi11; +Cc: maz
If ipi_exec() fails because of timeout, we shouldn't increase
the number of ipi received.
Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
---
arm/micro-bench.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arm/micro-bench.c b/arm/micro-bench.c
index 4612f41..ca022d9 100644
--- a/arm/micro-bench.c
+++ b/arm/micro-bench.c
@@ -103,7 +103,9 @@ static void ipi_exec(void)
while (!ipi_received && tries--)
cpu_relax();
- ++received;
+ if (ipi_recieved)
+ ++received;
+
assert_msg(ipi_received, "failed to receive IPI in time, but received %d successfully\n", received);
}
--
2.19.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH 1/6] arm64: microbench: get correct ipi recieved num
2020-05-17 10:08 ` [kvm-unit-tests PATCH 1/6] arm64: microbench: get correct ipi recieved num Jingyi Wang
@ 2020-05-21 14:00 ` Zenghui Yu
2020-05-22 2:32 ` Jingyi Wang
0 siblings, 1 reply; 12+ messages in thread
From: Zenghui Yu @ 2020-05-21 14:00 UTC (permalink / raw)
To: Jingyi Wang, drjones, kvm, kvmarm; +Cc: maz
On 2020/5/17 18:08, Jingyi Wang wrote:
> If ipi_exec() fails because of timeout, we shouldn't increase
> the number of ipi received.
>
> Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
> ---
> arm/micro-bench.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arm/micro-bench.c b/arm/micro-bench.c
> index 4612f41..ca022d9 100644
> --- a/arm/micro-bench.c
> +++ b/arm/micro-bench.c
> @@ -103,7 +103,9 @@ static void ipi_exec(void)
> while (!ipi_received && tries--)
> cpu_relax();
>
> - ++received;
> + if (ipi_recieved)
I think you may want *ipi_received* ;-) Otherwise it can not even
compile!
> + ++received;
> +
> assert_msg(ipi_received, "failed to receive IPI in time, but received %d successfully\n", received);
> }
With this fixed, this looks good to me,
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Thanks.
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH 1/6] arm64: microbench: get correct ipi recieved num
2020-05-21 14:00 ` Zenghui Yu
@ 2020-05-22 2:32 ` Jingyi Wang
2020-05-22 5:34 ` Andrew Jones
0 siblings, 1 reply; 12+ messages in thread
From: Jingyi Wang @ 2020-05-22 2:32 UTC (permalink / raw)
To: Zenghui Yu, drjones, kvm, kvmarm; +Cc: maz
On 5/21/2020 10:00 PM, Zenghui Yu wrote:
> On 2020/5/17 18:08, Jingyi Wang wrote:
>> If ipi_exec() fails because of timeout, we shouldn't increase
>> the number of ipi received.
>>
>> Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
>> ---
>> arm/micro-bench.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/arm/micro-bench.c b/arm/micro-bench.c
>> index 4612f41..ca022d9 100644
>> --- a/arm/micro-bench.c
>> +++ b/arm/micro-bench.c
>> @@ -103,7 +103,9 @@ static void ipi_exec(void)
>> while (!ipi_received && tries--)
>> cpu_relax();
>> - ++received;
>> + if (ipi_recieved)
>
> I think you may want *ipi_received* ;-) Otherwise it can not even
> compile!
>
>> + ++received;
>> +
>> assert_msg(ipi_received, "failed to receive IPI in time, but
>> received %d successfully\n", received);
>> }
>
> With this fixed, this looks good to me,
>
> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
>
>
> Thanks.
>
> .
This variable name is modified in the next patch, so I ignored that
mistake, thanks.
Thanks,
Jingyi
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH 1/6] arm64: microbench: get correct ipi recieved num
2020-05-22 2:32 ` Jingyi Wang
@ 2020-05-22 5:34 ` Andrew Jones
0 siblings, 0 replies; 12+ messages in thread
From: Andrew Jones @ 2020-05-22 5:34 UTC (permalink / raw)
To: Jingyi Wang; +Cc: kvm, maz, kvmarm
On Fri, May 22, 2020 at 10:32:25AM +0800, Jingyi Wang wrote:
>
> On 5/21/2020 10:00 PM, Zenghui Yu wrote:
> > On 2020/5/17 18:08, Jingyi Wang wrote:
> > > If ipi_exec() fails because of timeout, we shouldn't increase
> > > the number of ipi received.
> > >
> > > Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
> > > ---
> > > arm/micro-bench.c | 4 +++-
> > > 1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arm/micro-bench.c b/arm/micro-bench.c
> > > index 4612f41..ca022d9 100644
> > > --- a/arm/micro-bench.c
> > > +++ b/arm/micro-bench.c
> > > @@ -103,7 +103,9 @@ static void ipi_exec(void)
> > > while (!ipi_received && tries--)
> > > cpu_relax();
> > > - ++received;
> > > + if (ipi_recieved)
> >
> > I think you may want *ipi_received* ;-) Otherwise it can not even
> > compile!
> >
> > > + ++received;
> > > +
> > > assert_msg(ipi_received, "failed to receive IPI in time, but
> > > received %d successfully\n", received);
> > > }
> >
> > With this fixed, this looks good to me,
> >
> > Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
> >
> >
> > Thanks.
> >
> > .
> This variable name is modified in the next patch, so I ignored that
> mistake, thanks.
>
kvm-unit-tests build and run fast enough that you can do something like
git rebase -i -x 'make clean && make && arm/run arm/micro-bench'
to test your series before posting.
Thanks,
drew
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [kvm-unit-tests PATCH 2/6] arm64: microbench: Use the funcions for ipi test as the general functions for gic(ipi/lpi/timer) test.
2020-05-17 10:08 [kvm-unit-tests PATCH 0/6] arm64: add IPI/LPI/vtimer latency Jingyi Wang
2020-05-17 10:08 ` [kvm-unit-tests PATCH 1/6] arm64: microbench: get correct ipi recieved num Jingyi Wang
@ 2020-05-17 10:08 ` Jingyi Wang
2020-05-17 10:08 ` [kvm-unit-tests PATCH 3/6] arm64: microbench: gic: Add gicv4.1 support for ipi latency test Jingyi Wang
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Jingyi Wang @ 2020-05-17 10:08 UTC (permalink / raw)
To: drjones, kvm, kvmarm, wangjingyi11; +Cc: maz
The following patches will use that.
Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
---
arm/micro-bench.c | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/arm/micro-bench.c b/arm/micro-bench.c
index ca022d9..fc4d356 100644
--- a/arm/micro-bench.c
+++ b/arm/micro-bench.c
@@ -25,24 +25,24 @@
static u32 cntfrq;
-static volatile bool ipi_ready, ipi_received;
+static volatile bool irq_ready, irq_received;
static void *vgic_dist_base;
static void (*write_eoir)(u32 irqstat);
-static void ipi_irq_handler(struct pt_regs *regs)
+static void gic_irq_handler(struct pt_regs *regs)
{
- ipi_ready = false;
- ipi_received = true;
+ irq_ready = false;
+ irq_received = true;
gic_write_eoir(gic_read_iar());
- ipi_ready = true;
+ irq_ready = true;
}
-static void ipi_secondary_entry(void *data)
+static void gic_secondary_entry(void *data)
{
- install_irq_handler(EL1H_IRQ, ipi_irq_handler);
+ install_irq_handler(EL1H_IRQ, gic_irq_handler);
gic_enable_defaults();
local_irq_enable();
- ipi_ready = true;
+ irq_ready = true;
while (true)
cpu_relax();
}
@@ -72,9 +72,9 @@ static bool test_init(void)
break;
}
- ipi_ready = false;
+ irq_ready = false;
gic_enable_defaults();
- on_cpu_async(1, ipi_secondary_entry, NULL);
+ on_cpu_async(1, gic_secondary_entry, NULL);
cntfrq = get_cntfrq();
printf("Timer Frequency %d Hz (Output in microseconds)\n", cntfrq);
@@ -82,13 +82,18 @@ static bool test_init(void)
return true;
}
-static void ipi_prep(void)
+static void gic_prep_common(void)
{
unsigned tries = 1 << 28;
- while (!ipi_ready && tries--)
+ while (!irq_ready && tries--)
cpu_relax();
- assert(ipi_ready);
+ assert(irq_ready);
+}
+
+static void ipi_prep(void)
+{
+ gic_prep_common();
}
static void ipi_exec(void)
@@ -96,17 +101,17 @@ static void ipi_exec(void)
unsigned tries = 1 << 28;
static int received = 0;
- ipi_received = false;
+ irq_received = false;
gic_ipi_send_single(1, 1);
- while (!ipi_received && tries--)
+ while (!irq_received && tries--)
cpu_relax();
- if (ipi_recieved)
+ if (irq_received)
++received;
- assert_msg(ipi_received, "failed to receive IPI in time, but received %d successfully\n", received);
+ assert_msg(irq_received, "failed to receive IPI in time, but received %d successfully\n", received);
}
static void hvc_exec(void)
--
2.19.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [kvm-unit-tests PATCH 3/6] arm64: microbench: gic: Add gicv4.1 support for ipi latency test.
2020-05-17 10:08 [kvm-unit-tests PATCH 0/6] arm64: add IPI/LPI/vtimer latency Jingyi Wang
2020-05-17 10:08 ` [kvm-unit-tests PATCH 1/6] arm64: microbench: get correct ipi recieved num Jingyi Wang
2020-05-17 10:08 ` [kvm-unit-tests PATCH 2/6] arm64: microbench: Use the funcions for ipi test as the general functions for gic(ipi/lpi/timer) test Jingyi Wang
@ 2020-05-17 10:08 ` Jingyi Wang
2020-05-17 10:08 ` [kvm-unit-tests PATCH 4/6] arm64: its: Handle its command queue wrapping Jingyi Wang
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Jingyi Wang @ 2020-05-17 10:08 UTC (permalink / raw)
To: drjones, kvm, kvmarm, wangjingyi11; +Cc: maz
If gicv4.1(sgi hardware injection) supported, we test ipi injection
via hw/sw way separately.
Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
---
arm/micro-bench.c | 53 +++++++++++++++++++++++++++++++++++++++-----
lib/arm/asm/gic-v3.h | 5 +++++
lib/arm/asm/gic.h | 1 +
3 files changed, 54 insertions(+), 5 deletions(-)
diff --git a/arm/micro-bench.c b/arm/micro-bench.c
index fc4d356..0c7869b 100644
--- a/arm/micro-bench.c
+++ b/arm/micro-bench.c
@@ -28,6 +28,7 @@ static u32 cntfrq;
static volatile bool irq_ready, irq_received;
static void *vgic_dist_base;
static void (*write_eoir)(u32 irqstat);
+static bool ipi_hw;
static void gic_irq_handler(struct pt_regs *regs)
{
@@ -91,9 +92,42 @@ static void gic_prep_common(void)
assert(irq_ready);
}
-static void ipi_prep(void)
+static bool ipi_prep(void)
{
+ u32 val;
+
+ val = readl(vgic_dist_base + GICD_CTLR);
+ if (readl(vgic_dist_base + GICD_TYPER2) & GICD_TYPER2_nASSGIcap) {
+ val &= ~GICD_CTLR_ENABLE_G1A;
+ val &= ~GICD_CTLR_nASSGIreq;
+ writel(val, vgic_dist_base + GICD_CTLR);
+ val |= GICD_CTLR_ENABLE_G1A;
+ writel(val, vgic_dist_base + GICD_CTLR);
+ }
+
+ ipi_hw = false;
gic_prep_common();
+ return true;
+}
+
+static bool ipi_hw_prep(void)
+{
+ u32 val;
+
+ val = readl(vgic_dist_base + GICD_CTLR);
+ if (readl(vgic_dist_base + GICD_TYPER2) & GICD_TYPER2_nASSGIcap) {
+ val &= ~GICD_CTLR_ENABLE_G1A;
+ val |= GICD_CTLR_nASSGIreq;
+ writel(val, vgic_dist_base + GICD_CTLR);
+ val |= GICD_CTLR_ENABLE_G1A;
+ writel(val, vgic_dist_base + GICD_CTLR);
+ } else {
+ return false;
+ }
+
+ ipi_hw = true;
+ gic_prep_common();
+ return true;
}
static void ipi_exec(void)
@@ -103,7 +137,11 @@ static void ipi_exec(void)
irq_received = false;
- gic_ipi_send_single(1, 1);
+ if (ipi_hw) {
+ writel(1 << 1, gicv3_sgi_base_percpu(1) + GICR_ISPENDR0);
+ } else {
+ gic_ipi_send_single(1, 1);
+ }
while (!irq_received && tries--)
cpu_relax();
@@ -147,7 +185,7 @@ static void eoi_exec(void)
struct exit_test {
const char *name;
- void (*prep)(void);
+ bool (*prep)(void);
void (*exec)(void);
bool run;
};
@@ -158,6 +196,7 @@ static struct exit_test tests[] = {
{"mmio_read_vgic", NULL, mmio_read_vgic_exec, true},
{"eoi", NULL, eoi_exec, true},
{"ipi", ipi_prep, ipi_exec, true},
+ {"ipi_hw", ipi_hw_prep, ipi_exec, true},
};
struct ns_time {
@@ -181,9 +220,13 @@ static void loop_test(struct exit_test *test)
uint64_t start, end, total_ticks, ntimes = NTIMES;
struct ns_time total_ns, avg_ns;
- if (test->prep)
- test->prep();
+ if (test->prep) {
+ if(!test->prep()) {
+ printf("%s test skipped\n", test->name);
+ return;
+ }
+ }
isb();
start = read_sysreg(cntpct_el0);
while (ntimes--)
diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
index cb72922..cbf51ba 100644
--- a/lib/arm/asm/gic-v3.h
+++ b/lib/arm/asm/gic-v3.h
@@ -20,10 +20,13 @@
*/
#define GICD_CTLR 0x0000
#define GICD_CTLR_RWP (1U << 31)
+#define GICD_CTLR_nASSGIreq (1U << 8)
#define GICD_CTLR_ARE_NS (1U << 4)
#define GICD_CTLR_ENABLE_G1A (1U << 1)
#define GICD_CTLR_ENABLE_G1 (1U << 0)
+#define GICD_TYPER2_nASSGIcap (1U << 8)
+
/* Re-Distributor registers, offsets from RD_base */
#define GICR_TYPER 0x0008
@@ -87,6 +90,8 @@ extern struct gicv3_data gicv3_data;
#define gicv3_redist_base() (gicv3_data.redist_base[smp_processor_id()])
#define gicv3_sgi_base() (gicv3_data.redist_base[smp_processor_id()] + SZ_64K)
+#define gicv3_sgi_base_percpu(cpu) (gicv3_data.redist_base[cpu] + SZ_64K)
+
extern int gicv3_init(void);
extern void gicv3_enable_defaults(void);
extern u32 gicv3_read_iar(void);
diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h
index 38e79b2..1898400 100644
--- a/lib/arm/asm/gic.h
+++ b/lib/arm/asm/gic.h
@@ -13,6 +13,7 @@
#define GICD_CTLR 0x0000
#define GICD_TYPER 0x0004
#define GICD_IIDR 0x0008
+#define GICD_TYPER2 0x000C
#define GICD_IGROUPR 0x0080
#define GICD_ISENABLER 0x0100
#define GICD_ICENABLER 0x0180
--
2.19.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [kvm-unit-tests PATCH 4/6] arm64: its: Handle its command queue wrapping
2020-05-17 10:08 [kvm-unit-tests PATCH 0/6] arm64: add IPI/LPI/vtimer latency Jingyi Wang
` (2 preceding siblings ...)
2020-05-17 10:08 ` [kvm-unit-tests PATCH 3/6] arm64: microbench: gic: Add gicv4.1 support for ipi latency test Jingyi Wang
@ 2020-05-17 10:08 ` Jingyi Wang
2020-05-17 10:08 ` [kvm-unit-tests PATCH 5/6] arm64: microbench: its: Add LPI latency test Jingyi Wang
2020-05-17 10:09 ` [kvm-unit-tests PATCH 6/6] arm64: microbench: Add vtimer " Jingyi Wang
5 siblings, 0 replies; 12+ messages in thread
From: Jingyi Wang @ 2020-05-17 10:08 UTC (permalink / raw)
To: drjones, kvm, kvmarm, wangjingyi11; +Cc: maz
Because micro-bench may send a large number of ITS commands, we
should handle ITS command queue wrapping as kernel instead of just
failing the test.
Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
---
lib/arm64/gic-v3-its-cmd.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/arm64/gic-v3-its-cmd.c b/lib/arm64/gic-v3-its-cmd.c
index 2c208d1..34574f7 100644
--- a/lib/arm64/gic-v3-its-cmd.c
+++ b/lib/arm64/gic-v3-its-cmd.c
@@ -164,8 +164,9 @@ static struct its_cmd_block *its_allocate_entry(void)
{
struct its_cmd_block *cmd;
- assert((u64)its_data.cmd_write < (u64)its_data.cmd_base + SZ_64K);
cmd = its_data.cmd_write++;
+ if ((u64)its_data.cmd_write == (u64)its_data.cmd_base + SZ_64K)
+ its_data.cmd_write = its_data.cmd_base;
return cmd;
}
--
2.19.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [kvm-unit-tests PATCH 5/6] arm64: microbench: its: Add LPI latency test.
2020-05-17 10:08 [kvm-unit-tests PATCH 0/6] arm64: add IPI/LPI/vtimer latency Jingyi Wang
` (3 preceding siblings ...)
2020-05-17 10:08 ` [kvm-unit-tests PATCH 4/6] arm64: its: Handle its command queue wrapping Jingyi Wang
@ 2020-05-17 10:08 ` Jingyi Wang
2020-05-17 10:09 ` [kvm-unit-tests PATCH 6/6] arm64: microbench: Add vtimer " Jingyi Wang
5 siblings, 0 replies; 12+ messages in thread
From: Jingyi Wang @ 2020-05-17 10:08 UTC (permalink / raw)
To: drjones, kvm, kvmarm, wangjingyi11; +Cc: maz
Triggers LPIs through the INT command and test the latency.
Mostly inherited form commit 0ef02cd6cbaa(arm/arm64: ITS: INT
functional tests).
Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
---
arm/micro-bench.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arm/micro-bench.c b/arm/micro-bench.c
index 0c7869b..91af1f7 100644
--- a/arm/micro-bench.c
+++ b/arm/micro-bench.c
@@ -20,6 +20,7 @@
*/
#include <libcflat.h>
#include <asm/gic.h>
+#include <asm/gic-v3-its.h>
#define NTIMES (1U << 16)
@@ -152,6 +153,48 @@ static void ipi_exec(void)
assert_msg(irq_received, "failed to receive IPI in time, but received %d successfully\n", received);
}
+static bool lpi_prep(void)
+{
+ struct its_collection *col1;
+ struct its_device *dev2;
+
+ if (!gicv3_its_base())
+ return false;
+
+ its_enable_defaults();
+ dev2 = its_create_device(2 /* dev id */, 8 /* nb_ites */);
+ col1 = its_create_collection(1 /* col id */, 1 /* target PE */);
+ gicv3_lpi_set_config(8199, LPI_PROP_DEFAULT);
+
+ its_send_mapd_nv(dev2, true);
+ its_send_mapc_nv(col1, true);
+ its_send_invall_nv(col1);
+ its_send_mapti_nv(dev2, 8199 /* lpi id */, 20 /* event id */, col1);
+
+ gic_prep_common();
+ return true;
+}
+
+static void lpi_exec(void)
+{
+ struct its_device *dev2;
+ unsigned tries = 1 << 28;
+ static int received = 0;
+
+ irq_received = false;
+
+ dev2 = its_get_device(2);
+ its_send_int_nv(dev2, 20);
+
+ while (!irq_received && tries--)
+ cpu_relax();
+
+ if (irq_received)
+ ++received;
+
+ assert_msg(irq_received, "failed to receive LPI in time, but received %d successfully\n", received);
+}
+
static void hvc_exec(void)
{
asm volatile("mov w0, #0x4b000000; hvc #0" ::: "w0");
@@ -197,6 +240,7 @@ static struct exit_test tests[] = {
{"eoi", NULL, eoi_exec, true},
{"ipi", ipi_prep, ipi_exec, true},
{"ipi_hw", ipi_hw_prep, ipi_exec, true},
+ {"lpi", lpi_prep, lpi_exec, true},
};
struct ns_time {
--
2.19.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [kvm-unit-tests PATCH 6/6] arm64: microbench: Add vtimer latency test
2020-05-17 10:08 [kvm-unit-tests PATCH 0/6] arm64: add IPI/LPI/vtimer latency Jingyi Wang
` (4 preceding siblings ...)
2020-05-17 10:08 ` [kvm-unit-tests PATCH 5/6] arm64: microbench: its: Add LPI latency test Jingyi Wang
@ 2020-05-17 10:09 ` Jingyi Wang
2020-05-18 7:05 ` Andrew Jones
5 siblings, 1 reply; 12+ messages in thread
From: Jingyi Wang @ 2020-05-17 10:09 UTC (permalink / raw)
To: drjones, kvm, kvmarm, wangjingyi11; +Cc: maz
Triggers PPIs by setting up a 10msec timer and test the latency.
For this test can be time consuming, we add time limit for loop_test
to make sure each test should be done in a certain time(5 sec here).
Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
---
arm/micro-bench.c | 81 ++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 70 insertions(+), 11 deletions(-)
diff --git a/arm/micro-bench.c b/arm/micro-bench.c
index 91af1f7..dbe8e54 100644
--- a/arm/micro-bench.c
+++ b/arm/micro-bench.c
@@ -23,6 +23,11 @@
#include <asm/gic-v3-its.h>
#define NTIMES (1U << 16)
+#define MAX_NS (5 * 1000 * 1000 * 1000UL)
+
+#define IRQ_VTIMER 27
+#define ARCH_TIMER_CTL_ENABLE (1 << 0)
+#define ARCH_TIMER_CTL_IMASK (1 << 1)
static u32 cntfrq;
@@ -33,9 +38,16 @@ static bool ipi_hw;
static void gic_irq_handler(struct pt_regs *regs)
{
+ u32 irqstat = gic_read_iar();
irq_ready = false;
irq_received = true;
- gic_write_eoir(gic_read_iar());
+ gic_write_eoir(irqstat);
+
+ if (irqstat == IRQ_VTIMER) {
+ write_sysreg((ARCH_TIMER_CTL_IMASK | ARCH_TIMER_CTL_ENABLE),
+ cntv_ctl_el0);
+ isb();
+ }
irq_ready = true;
}
@@ -195,6 +207,47 @@ static void lpi_exec(void)
assert_msg(irq_received, "failed to receive LPI in time, but received %d successfully\n", received);
}
+static bool timer_prep(void)
+{
+ static void *gic_isenabler;
+
+ gic_enable_defaults();
+ install_irq_handler(EL1H_IRQ, gic_irq_handler);
+ local_irq_enable();
+
+ gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0;
+ writel(1 << IRQ_VTIMER, gic_isenabler);
+ write_sysreg(ARCH_TIMER_CTL_ENABLE, cntv_ctl_el0);
+ isb();
+
+ gic_prep_common();
+ return true;
+}
+
+static void timer_exec(void)
+{
+ u64 before_timer;
+ u64 timer_10ms;
+ unsigned tries = 1 << 28;
+ static int received = 0;
+
+ irq_received = false;
+
+ before_timer = read_sysreg(cntvct_el0);
+ timer_10ms = cntfrq / 100;
+ write_sysreg(before_timer + timer_10ms, cntv_cval_el0);
+ write_sysreg(ARCH_TIMER_CTL_ENABLE, cntv_ctl_el0);
+ isb();
+
+ while (!irq_received && tries--)
+ cpu_relax();
+
+ if (irq_received)
+ ++received;
+
+ assert_msg(irq_received, "failed to receive PPI in time, but received %d successfully\n", received);
+}
+
static void hvc_exec(void)
{
asm volatile("mov w0, #0x4b000000; hvc #0" ::: "w0");
@@ -241,6 +294,7 @@ static struct exit_test tests[] = {
{"ipi", ipi_prep, ipi_exec, true},
{"ipi_hw", ipi_hw_prep, ipi_exec, true},
{"lpi", lpi_prep, lpi_exec, true},
+ {"timer_10ms", timer_prep, timer_exec, true},
};
struct ns_time {
@@ -261,27 +315,32 @@ static void ticks_to_ns_time(uint64_t ticks, struct ns_time *ns_time)
static void loop_test(struct exit_test *test)
{
- uint64_t start, end, total_ticks, ntimes = NTIMES;
+ uint64_t start, end, total_ticks, ntimes = 0;
struct ns_time total_ns, avg_ns;
+ total_ticks = 0;
if (test->prep) {
if(!test->prep()) {
-
printf("%s test skipped\n", test->name);
return;
}
}
- isb();
- start = read_sysreg(cntpct_el0);
- while (ntimes--)
+
+ while (ntimes < NTIMES && total_ns.ns < MAX_NS) {
+ isb();
+ start = read_sysreg(cntpct_el0);
test->exec();
- isb();
- end = read_sysreg(cntpct_el0);
+ isb();
+ end = read_sysreg(cntpct_el0);
+
+ ntimes++;
+ total_ticks += (end - start);
+ ticks_to_ns_time(total_ticks, &total_ns);
+ }
- total_ticks = end - start;
ticks_to_ns_time(total_ticks, &total_ns);
- avg_ns.ns = total_ns.ns / NTIMES;
- avg_ns.ns_frac = total_ns.ns_frac / NTIMES;
+ avg_ns.ns = total_ns.ns / ntimes;
+ avg_ns.ns_frac = total_ns.ns_frac / ntimes;
printf("%-30s%15" PRId64 ".%-15" PRId64 "%15" PRId64 ".%-15" PRId64 "\n",
test->name, total_ns.ns, total_ns.ns_frac, avg_ns.ns, avg_ns.ns_frac);
--
2.19.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH 6/6] arm64: microbench: Add vtimer latency test
2020-05-17 10:09 ` [kvm-unit-tests PATCH 6/6] arm64: microbench: Add vtimer " Jingyi Wang
@ 2020-05-18 7:05 ` Andrew Jones
2020-05-20 4:16 ` Jingyi Wang
0 siblings, 1 reply; 12+ messages in thread
From: Andrew Jones @ 2020-05-18 7:05 UTC (permalink / raw)
To: Jingyi Wang; +Cc: kvm, maz, kvmarm
On Sun, May 17, 2020 at 06:09:00PM +0800, Jingyi Wang wrote:
> Triggers PPIs by setting up a 10msec timer and test the latency.
> For this test can be time consuming, we add time limit for loop_test
> to make sure each test should be done in a certain time(5 sec here).
Having a time limit for the micro-bench tests might be a good idea, as
the overall unit test timeout configured by unittests.cfg can't measure
each individual micro-bench test separately, but it seems what we're
really doing here is saying that we can't do 65536 10ms long vtimer-ppi
tests, so let's do 500 instead -- however by using time to dictate the
count.
I think I'd rather see NTIMES be changed to a micro-bench test parameter
that defaults to 65536, but for the vtimer-ppi test it can be set to
something much smaller.
Also, please create a separate patch for the loop_test()/ntimes changes.
If you'd still like to do a per micro-bench test timeout as well, then
please create a separate patch for that too.
Thanks,
drew
>
> Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com>
> ---
> arm/micro-bench.c | 81 ++++++++++++++++++++++++++++++++++++++++-------
> 1 file changed, 70 insertions(+), 11 deletions(-)
>
> diff --git a/arm/micro-bench.c b/arm/micro-bench.c
> index 91af1f7..dbe8e54 100644
> --- a/arm/micro-bench.c
> +++ b/arm/micro-bench.c
> @@ -23,6 +23,11 @@
> #include <asm/gic-v3-its.h>
>
> #define NTIMES (1U << 16)
> +#define MAX_NS (5 * 1000 * 1000 * 1000UL)
> +
> +#define IRQ_VTIMER 27
> +#define ARCH_TIMER_CTL_ENABLE (1 << 0)
> +#define ARCH_TIMER_CTL_IMASK (1 << 1)
>
> static u32 cntfrq;
>
> @@ -33,9 +38,16 @@ static bool ipi_hw;
>
> static void gic_irq_handler(struct pt_regs *regs)
> {
> + u32 irqstat = gic_read_iar();
> irq_ready = false;
> irq_received = true;
> - gic_write_eoir(gic_read_iar());
> + gic_write_eoir(irqstat);
> +
> + if (irqstat == IRQ_VTIMER) {
> + write_sysreg((ARCH_TIMER_CTL_IMASK | ARCH_TIMER_CTL_ENABLE),
> + cntv_ctl_el0);
> + isb();
> + }
> irq_ready = true;
> }
>
> @@ -195,6 +207,47 @@ static void lpi_exec(void)
> assert_msg(irq_received, "failed to receive LPI in time, but received %d successfully\n", received);
> }
>
> +static bool timer_prep(void)
> +{
> + static void *gic_isenabler;
> +
> + gic_enable_defaults();
> + install_irq_handler(EL1H_IRQ, gic_irq_handler);
> + local_irq_enable();
> +
> + gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0;
> + writel(1 << IRQ_VTIMER, gic_isenabler);
> + write_sysreg(ARCH_TIMER_CTL_ENABLE, cntv_ctl_el0);
> + isb();
> +
> + gic_prep_common();
> + return true;
> +}
> +
> +static void timer_exec(void)
> +{
> + u64 before_timer;
> + u64 timer_10ms;
> + unsigned tries = 1 << 28;
> + static int received = 0;
> +
> + irq_received = false;
> +
> + before_timer = read_sysreg(cntvct_el0);
> + timer_10ms = cntfrq / 100;
> + write_sysreg(before_timer + timer_10ms, cntv_cval_el0);
> + write_sysreg(ARCH_TIMER_CTL_ENABLE, cntv_ctl_el0);
> + isb();
> +
> + while (!irq_received && tries--)
> + cpu_relax();
> +
> + if (irq_received)
> + ++received;
> +
> + assert_msg(irq_received, "failed to receive PPI in time, but received %d successfully\n", received);
> +}
> +
> static void hvc_exec(void)
> {
> asm volatile("mov w0, #0x4b000000; hvc #0" ::: "w0");
> @@ -241,6 +294,7 @@ static struct exit_test tests[] = {
> {"ipi", ipi_prep, ipi_exec, true},
> {"ipi_hw", ipi_hw_prep, ipi_exec, true},
> {"lpi", lpi_prep, lpi_exec, true},
> + {"timer_10ms", timer_prep, timer_exec, true},
> };
>
> struct ns_time {
> @@ -261,27 +315,32 @@ static void ticks_to_ns_time(uint64_t ticks, struct ns_time *ns_time)
>
> static void loop_test(struct exit_test *test)
> {
> - uint64_t start, end, total_ticks, ntimes = NTIMES;
> + uint64_t start, end, total_ticks, ntimes = 0;
> struct ns_time total_ns, avg_ns;
>
> + total_ticks = 0;
> if (test->prep) {
> if(!test->prep()) {
> -
> printf("%s test skipped\n", test->name);
> return;
> }
> }
> - isb();
> - start = read_sysreg(cntpct_el0);
> - while (ntimes--)
> +
> + while (ntimes < NTIMES && total_ns.ns < MAX_NS) {
> + isb();
> + start = read_sysreg(cntpct_el0);
> test->exec();
> - isb();
> - end = read_sysreg(cntpct_el0);
> + isb();
> + end = read_sysreg(cntpct_el0);
> +
> + ntimes++;
> + total_ticks += (end - start);
> + ticks_to_ns_time(total_ticks, &total_ns);
> + }
>
> - total_ticks = end - start;
> ticks_to_ns_time(total_ticks, &total_ns);
> - avg_ns.ns = total_ns.ns / NTIMES;
> - avg_ns.ns_frac = total_ns.ns_frac / NTIMES;
> + avg_ns.ns = total_ns.ns / ntimes;
> + avg_ns.ns_frac = total_ns.ns_frac / ntimes;
>
> printf("%-30s%15" PRId64 ".%-15" PRId64 "%15" PRId64 ".%-15" PRId64 "\n",
> test->name, total_ns.ns, total_ns.ns_frac, avg_ns.ns, avg_ns.ns_frac);
> --
> 2.19.1
>
>
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [kvm-unit-tests PATCH 6/6] arm64: microbench: Add vtimer latency test
2020-05-18 7:05 ` Andrew Jones
@ 2020-05-20 4:16 ` Jingyi Wang
0 siblings, 0 replies; 12+ messages in thread
From: Jingyi Wang @ 2020-05-20 4:16 UTC (permalink / raw)
To: Andrew Jones; +Cc: kvm, maz, kvmarm
Hi Drew,
On 5/18/2020 3:05 PM, Andrew Jones wrote:
> On Sun, May 17, 2020 at 06:09:00PM +0800, Jingyi Wang wrote:
>> Triggers PPIs by setting up a 10msec timer and test the latency.
>> For this test can be time consuming, we add time limit for loop_test
>> to make sure each test should be done in a certain time(5 sec here).
>
> Having a time limit for the micro-bench tests might be a good idea, as
> the overall unit test timeout configured by unittests.cfg can't measure
> each individual micro-bench test separately, but it seems what we're
> really doing here is saying that we can't do 65536 10ms long vtimer-ppi
> tests, so let's do 500 instead -- however by using time to dictate the
> count.
>
> I think I'd rather see NTIMES be changed to a micro-bench test parameter
> that defaults to 65536, but for the vtimer-ppi test it can be set to
> something much smaller.
>
> Also, please create a separate patch for the loop_test()/ntimes changes.
> If you'd still like to do a per micro-bench test timeout as well, then
> please create a separate patch for that too.
>
> Thanks,
> drew
>
Thanks for your review, I will update that in the next version.
Thanks,
Jingyi
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^ permalink raw reply [flat|nested] 12+ messages in thread