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From: Andrew Lunn <andrew@lunn.ch>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Calvin Johnson <calvin.johnson@oss.nxp.com>,
	Grant Likely <grant.likely@arm.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Jeremy Linton <jeremy.linton@arm.com>,
	Russell King - ARM Linux admin <linux@armlinux.org.uk>,
	Jon <jon@solid-run.com>,
	Cristi Sovaiala <cristian.sovaiala@nxp.com>,
	Ioana Ciornei <ioana.ciornei@nxp.com>,
	Andy Shevchenko <andy.shevchenko@gmail.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Madalin Bucur <madalin.bucur@oss.nxp.com>,
	Networking <netdev@vger.kernel.org>,
	linux.cj@gmail.com,
	ACPI Devel Maling List <linux-acpi@vger.kernel.org>,
	nd <nd@arm.com>
Subject: Re: [net-next PATCH v7 1/6] Documentation: ACPI: DSD: Document MDIO PHY
Date: Tue, 29 Sep 2020 16:59:10 +0200
Message-ID: <20200929145910.GJ3950513@lunn.ch> (raw)
In-Reply-To: <CAK8P3a0etJf_SG8qLY0VjR+JamKQ8MtyPwoXnb0mpnGZawLfRA@mail.gmail.com>

> IIRC both UEFI and ACPI define only little-endian data structures.
> The code does not attempt to convert these into CPU endianness
> at the moment.  In theory it could be changed to support either, but
> this seems non-practical for the UEFI runtime services that require
> calling into firmware code in little-endian mode.

Hi Arnd

Thanks for the info. So we can assume the CPU is little endian.  That
helps narrow down the problem.

> > If this is the bus controller endianness, are all the SoCs you plan to
> > support via ACPI the same endianness? If they are all the same, you
> > can hard code it.
> 
> NXP has a bunch of SoCs that reuse the same on-chip devices but
> change the endianness between them based on what the chip
> designers guessed the OS would want, which is why the drivers
> usually support both register layouts and switch at runtime.
> Worse, depending on which SoC was the first to get a DT binding
> for a particular NXP on-chip device, the default endianness is
> different, and there is either a "big-endian" or "little-endian"
> override in the binding.
> 
> I would guess that for modern NXP chips that you might boot with
> ACPI the endianness is always wired the same way, but I
> understand the caution when they have been burned by this
> problem before.

So it might depend on if NXP is worried it might flip the endianness
of the synthesis of the MDIO controller at some point for devices it
wants to support using ACPI?

Does ACPI have a standard way of declaring the endianness of a device?
We don't really want to put the DT parameter in ACPI, we want to use
the ACPI way of doing it.

    Thanks
	Andrew

  reply index

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-15  9:03 [net-next PATCH v7 0/6] ACPI support for dpaa2 MAC driver Calvin Johnson
2020-07-15  9:03 ` [net-next PATCH v7 1/6] Documentation: ACPI: DSD: Document MDIO PHY Calvin Johnson
2020-07-16  3:04   ` Florian Fainelli
2020-07-16  3:11     ` Andrew Lunn
2020-07-23 23:26   ` Jeremy Linton
2020-07-24 13:39     ` Andrew Lunn
2020-07-24 17:26       ` Jeremy Linton
2020-07-24 17:39         ` Florian Fainelli
2020-07-24 19:20           ` Andrew Lunn
2020-07-24 20:12             ` Andy Shevchenko
2020-07-24 20:13               ` Florian Fainelli
2020-07-24 20:20                 ` Andy Shevchenko
2020-07-25  7:36                   ` Calvin Johnson
2020-07-25 10:48                     ` Andy Shevchenko
2020-07-24 21:06               ` Russell King - ARM Linux admin
2020-07-27 17:03             ` Sudeep Holla
2020-07-24 19:14         ` Andrew Lunn
2020-07-27 17:21           ` Sudeep Holla
2020-07-28 20:34             ` Andrew Lunn
2020-07-28 20:59               ` Russell King - ARM Linux admin
2020-07-28 21:26                 ` Andy Shevchenko
2020-07-29 16:00               ` Rafael J. Wysocki
2020-07-31 15:08                 ` Andrew Lunn
2020-07-27 17:32           ` Jon Nettleton
     [not found]           ` <1595922651-sup-5323@galangal.danc.bne.opengear.com>
2020-07-28 20:45             ` Andrew Lunn
2020-07-28 20:56               ` Florian Fainelli
2020-07-28 21:28                 ` Andy Shevchenko
2020-07-28 21:40                   ` Florian Fainelli
2020-07-31 15:14                   ` Andrew Lunn
2020-09-25 13:22                     ` Grant Likely
2020-07-28 22:30             ` Jeremy Linton
2020-07-29  0:39               ` Florian Fainelli
2020-07-29  2:53                 ` Jeremy Linton
2020-07-29  3:16                   ` Florian Fainelli
2020-07-29  8:43                   ` Jon Nettleton
2020-07-29  9:39                     ` Calvin Johnson
2020-09-25 13:34   ` Grant Likely
2020-09-26  4:30     ` Calvin Johnson
2020-09-29  5:17     ` Calvin Johnson
2020-09-29 13:43       ` Andrew Lunn
2020-09-29 13:55         ` Andy Shevchenko
2020-09-29 14:32           ` Andrew Lunn
2020-09-29 14:46             ` Andy Shevchenko
2020-09-29 15:06               ` Andrew Lunn
2020-09-29 15:29               ` Arnd Bergmann
2020-09-29 14:44         ` Arnd Bergmann
2020-09-29 14:59           ` Andrew Lunn [this message]
2020-09-29 15:59             ` Grant Likely
2020-09-29 15:53         ` Grant Likely
2020-09-29 16:04           ` Calvin Johnson
2020-07-15  9:03 ` [net-next PATCH v7 2/6] net: phy: introduce device_mdiobus_register() Calvin Johnson
2020-07-16  3:05   ` Florian Fainelli
2020-07-15  9:03 ` [net-next PATCH v7 3/6] net/fsl: use device_mdiobus_register() Calvin Johnson
2020-07-16  3:05   ` Florian Fainelli
2020-07-15  9:03 ` [net-next PATCH v7 4/6] net: phy: introduce phy_find_by_mdio_handle() Calvin Johnson
2020-07-16  3:06   ` Florian Fainelli
2020-07-15  9:03 ` [net-next PATCH v7 5/6] phylink: introduce phylink_fwnode_phy_connect() Calvin Johnson
2020-07-15  9:04 ` [net-next PATCH v7 6/6] net: dpaa2-mac: Add ACPI support for DPAA2 MAC driver Calvin Johnson
2020-09-25 13:39 ` [net-next PATCH v7 0/6] ACPI support for dpaa2 " Grant Likely
2020-09-26  4:34   ` Calvin Johnson
2020-07-25 14:23 Calvin Johnson
2020-07-25 14:23 ` [net-next PATCH v7 1/6] Documentation: ACPI: DSD: Document MDIO PHY Calvin Johnson

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