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From: Hector Martin <marcan@marcan.st>
To: Kalle Valo <kvalo@codeaurora.org>,
	"David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>, Arend van Spriel <aspriel@gmail.com>,
	Franky Lin <franky.lin@broadcom.com>,
	Hante Meuleman <hante.meuleman@broadcom.com>,
	Chi-hsien Lin <chi-hsien.lin@infineon.com>,
	Wright Feng <wright.feng@infineon.com>,
	Chung-hsien Hsu <chung-hsien.hsu@infineon.com>
Cc: "Hector Martin" <marcan@marcan.st>,
	"Sven Peter" <sven@svenpeter.dev>,
	"Alyssa Rosenzweig" <alyssa@rosenzweig.io>,
	"Mark Kettenis" <kettenis@openbsd.org>,
	"Rafał Miłecki" <zajec5@gmail.com>,
	"Pieter-Paul Giesberts" <pieter-paul.giesberts@broadcom.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Hans de Goede" <hdegoede@redhat.com>,
	"John W. Linville" <linville@tuxdriver.com>,
	"Daniel (Deognyoun) Kim" <dekim@broadcom.com>,
	"brian m. carlson" <sandals@crustytoothpaste.net>,
	linux-wireless@vger.kernel.org, netdev@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-acpi@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com,
	SHA-cyfmac-dev-list@infineon.com
Subject: [PATCH 13/34] brcmfmac: pcie: Support PCIe core revisions >= 64
Date: Mon, 27 Dec 2021 00:36:03 +0900	[thread overview]
Message-ID: <20211226153624.162281-14-marcan@marcan.st> (raw)
In-Reply-To: <20211226153624.162281-1-marcan@marcan.st>

These newer PCIe core revisions include new sets of registers that must
be used instead of the legacy ones. Introduce a brcmf_pcie_reginfo to
hold the specific register offsets and values to use for a given
platform, and change all the register accesses to indirect through it.

Signed-off-by: Hector Martin <marcan@marcan.st>
---
 .../broadcom/brcm80211/brcmfmac/pcie.c        | 125 +++++++++++++++---
 1 file changed, 105 insertions(+), 20 deletions(-)

diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
index ffb01872c6a3..520de2531e30 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
@@ -118,6 +118,12 @@ static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0	0x140
 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1	0x144
 
+#define BRCMF_PCIE_64_PCIE2REG_INTMASK		0xC14
+#define BRCMF_PCIE_64_PCIE2REG_MAILBOXINT	0xC30
+#define BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK	0xC34
+#define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0	0xA20
+#define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1	0xA24
+
 #define BRCMF_PCIE2_INTA			0x01
 #define BRCMF_PCIE2_INTB			0x02
 
@@ -137,6 +143,8 @@ static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
 #define	BRCMF_PCIE_MB_INT_D2H3_DB0		0x400000
 #define	BRCMF_PCIE_MB_INT_D2H3_DB1		0x800000
 
+#define BRCMF_PCIE_MB_INT_FN0			(BRCMF_PCIE_MB_INT_FN0_0 | \
+						 BRCMF_PCIE_MB_INT_FN0_1)
 #define BRCMF_PCIE_MB_INT_D2H_DB		(BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 						 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 						 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
@@ -146,6 +154,40 @@ static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
 						 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 						 BRCMF_PCIE_MB_INT_D2H3_DB1)
 
+#define	BRCMF_PCIE_64_MB_INT_D2H0_DB0		0x1
+#define	BRCMF_PCIE_64_MB_INT_D2H0_DB1		0x2
+#define	BRCMF_PCIE_64_MB_INT_D2H1_DB0		0x4
+#define	BRCMF_PCIE_64_MB_INT_D2H1_DB1		0x8
+#define	BRCMF_PCIE_64_MB_INT_D2H2_DB0		0x10
+#define	BRCMF_PCIE_64_MB_INT_D2H2_DB1		0x20
+#define	BRCMF_PCIE_64_MB_INT_D2H3_DB0		0x40
+#define	BRCMF_PCIE_64_MB_INT_D2H3_DB1		0x80
+#define	BRCMF_PCIE_64_MB_INT_D2H4_DB0		0x100
+#define	BRCMF_PCIE_64_MB_INT_D2H4_DB1		0x200
+#define	BRCMF_PCIE_64_MB_INT_D2H5_DB0		0x400
+#define	BRCMF_PCIE_64_MB_INT_D2H5_DB1		0x800
+#define	BRCMF_PCIE_64_MB_INT_D2H6_DB0		0x1000
+#define	BRCMF_PCIE_64_MB_INT_D2H6_DB1		0x2000
+#define	BRCMF_PCIE_64_MB_INT_D2H7_DB0		0x4000
+#define	BRCMF_PCIE_64_MB_INT_D2H7_DB1		0x8000
+
+#define BRCMF_PCIE_64_MB_INT_D2H_DB		(BRCMF_PCIE_64_MB_INT_D2H0_DB0 | \
+						 BRCMF_PCIE_64_MB_INT_D2H0_DB1 | \
+						 BRCMF_PCIE_64_MB_INT_D2H1_DB0 | \
+						 BRCMF_PCIE_64_MB_INT_D2H1_DB1 | \
+						 BRCMF_PCIE_64_MB_INT_D2H2_DB0 | \
+						 BRCMF_PCIE_64_MB_INT_D2H2_DB1 | \
+						 BRCMF_PCIE_64_MB_INT_D2H3_DB0 | \
+						 BRCMF_PCIE_64_MB_INT_D2H3_DB1 | \
+						 BRCMF_PCIE_64_MB_INT_D2H4_DB0 | \
+						 BRCMF_PCIE_64_MB_INT_D2H4_DB1 | \
+						 BRCMF_PCIE_64_MB_INT_D2H5_DB0 | \
+						 BRCMF_PCIE_64_MB_INT_D2H5_DB1 | \
+						 BRCMF_PCIE_64_MB_INT_D2H6_DB0 | \
+						 BRCMF_PCIE_64_MB_INT_D2H6_DB1 | \
+						 BRCMF_PCIE_64_MB_INT_D2H7_DB0 | \
+						 BRCMF_PCIE_64_MB_INT_D2H7_DB1)
+
 #define BRCMF_PCIE_SHARED_VERSION_7		7
 #define BRCMF_PCIE_MIN_SHARED_VERSION		5
 #define BRCMF_PCIE_MAX_SHARED_VERSION		BRCMF_PCIE_SHARED_VERSION_7
@@ -272,6 +314,7 @@ struct brcmf_pciedev_info {
 	char nvram_name[BRCMF_FW_NAME_LEN];
 	char clm_name[BRCMF_FW_NAME_LEN];
 	const struct firmware *clm_fw;
+	const struct brcmf_pcie_reginfo *reginfo;
 	void __iomem *regs;
 	void __iomem *tcm;
 	u32 ram_base;
@@ -358,6 +401,36 @@ static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 	BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 };
 
+struct brcmf_pcie_reginfo {
+	u32 intmask;
+	u32 mailboxint;
+	u32 mailboxmask;
+	u32 h2d_mailbox_0;
+	u32 h2d_mailbox_1;
+	u32 int_d2h_db;
+	u32 int_fn0;
+};
+
+static const struct brcmf_pcie_reginfo brcmf_reginfo_default = {
+	.intmask = BRCMF_PCIE_PCIE2REG_INTMASK,
+	.mailboxint = BRCMF_PCIE_PCIE2REG_MAILBOXINT,
+	.mailboxmask = BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
+	.h2d_mailbox_0 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0,
+	.h2d_mailbox_1 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1,
+	.int_d2h_db = BRCMF_PCIE_MB_INT_D2H_DB,
+	.int_fn0 = BRCMF_PCIE_MB_INT_FN0,
+};
+
+static const struct brcmf_pcie_reginfo brcmf_reginfo_64 = {
+	.intmask = BRCMF_PCIE_64_PCIE2REG_INTMASK,
+	.mailboxint = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT,
+	.mailboxmask = BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK,
+	.h2d_mailbox_0 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0,
+	.h2d_mailbox_1 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1,
+	.int_d2h_db = BRCMF_PCIE_64_MB_INT_D2H_DB,
+	.int_fn0 = 0,
+};
+
 static void brcmf_pcie_setup(struct device *dev, int ret,
 			     struct brcmf_fw_request *fwreq);
 static struct brcmf_fw_request *
@@ -840,30 +913,29 @@ static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo,
 
 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 {
-	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0);
+	brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 0);
 }
 
 
 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 {
-	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
-			       BRCMF_PCIE_MB_INT_D2H_DB |
-			       BRCMF_PCIE_MB_INT_FN0_0 |
-			       BRCMF_PCIE_MB_INT_FN0_1);
+	brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask,
+			       devinfo->reginfo->int_d2h_db |
+			       devinfo->reginfo->int_fn0);
 }
 
 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo)
 {
 	if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1)
 		brcmf_pcie_write_reg32(devinfo,
-				       BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1, 1);
+				       devinfo->reginfo->h2d_mailbox_1, 1);
 }
 
 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
 {
 	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 
-	if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
+	if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint)) {
 		brcmf_pcie_intr_disable(devinfo);
 		brcmf_dbg(PCIE, "Enter\n");
 		return IRQ_WAKE_THREAD;
@@ -878,15 +950,14 @@ static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
 	u32 status;
 
 	devinfo->in_irq = true;
-	status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
+	status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
 	brcmf_dbg(PCIE, "Enter %x\n", status);
 	if (status) {
-		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
+		brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint,
 				       status);
-		if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
-			      BRCMF_PCIE_MB_INT_FN0_1))
+		if (status & devinfo->reginfo->int_fn0)
 			brcmf_pcie_handle_mb_data(devinfo);
-		if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
+		if (status & devinfo->reginfo->int_d2h_db) {
 			if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 				brcmf_proto_msgbuf_rx_trigger(
 							&devinfo->pdev->dev);
@@ -945,8 +1016,8 @@ static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 	if (devinfo->in_irq)
 		brcmf_err(bus, "Still in IRQ (processing) !!!\n");
 
-	status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
-	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status);
+	status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
+	brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, status);
 
 	devinfo->irq_allocated = false;
 }
@@ -998,7 +1069,7 @@ static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 
 	brcmf_dbg(PCIE, "RING !\n");
 	/* Any arbitrary value will do, lets use 1 */
-	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0, 1);
+	brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->h2d_mailbox_0, 1);
 
 	return 0;
 }
@@ -1760,15 +1831,22 @@ static int brcmf_pcie_buscoreprep(void *ctx)
 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
 {
 	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
-	u32 val;
+	struct brcmf_core *core;
+	u32 val, reg;
 
 	devinfo->ci = chip;
 	brcmf_pcie_reset_device(devinfo);
 
-	val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
+	/* reginfo is not ready yet */
+	core = brcmf_chip_get_core(chip, BCMA_CORE_PCIE2);
+	if (core->rev >= 64)
+		reg = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT;
+	else
+		reg = BRCMF_PCIE_PCIE2REG_MAILBOXINT;
+
+	val = brcmf_pcie_read_reg32(devinfo, reg);
 	if (val != 0xffffffff)
-		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
-				       val);
+		brcmf_pcie_write_reg32(devinfo, reg, val);
 
 	return 0;
 }
@@ -2179,6 +2257,7 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	struct brcmf_pciedev_info *devinfo;
 	struct brcmf_pciedev *pcie_bus_dev;
 	struct brcmf_bus *bus;
+	struct brcmf_core *core;
 
 	brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
 
@@ -2197,6 +2276,12 @@ brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 		goto fail;
 	}
 
+	core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
+	if (core->rev >= 64)
+		devinfo->reginfo = &brcmf_reginfo_64;
+	else
+		devinfo->reginfo = &brcmf_reginfo_default;
+
 	pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
 	if (pcie_bus_dev == NULL) {
 		ret = -ENOMEM;
@@ -2365,7 +2450,7 @@ static int brcmf_pcie_pm_leave_D3(struct device *dev)
 	brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
 
 	/* Check if device is still up and running, if so we are ready */
-	if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
+	if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->intmask) != 0) {
 		brcmf_dbg(PCIE, "Try to wakeup device....\n");
 		if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
 			goto cleanup;
-- 
2.33.0


  parent reply	other threads:[~2021-12-26 15:38 UTC|newest]

Thread overview: 105+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-26 15:35 [RFC PATCH 00/34] brcmfmac: Support Apple T2 and M1 platforms Hector Martin
2021-12-26 15:35 ` [PATCH 01/34] dt-bindings: net: bcm4329-fmac: Add Apple properties & chips Hector Martin
2021-12-26 21:02   ` Linus Walleij
2021-12-26 23:34   ` Rob Herring
2021-12-27 16:36   ` Rob Herring
2021-12-27 17:23     ` Hector Martin
2021-12-29 16:38       ` Mark Kettenis
2022-01-02 14:12         ` Hector Martin
2021-12-29 16:42   ` Mark Kettenis
2022-01-04  5:47     ` Hector Martin
2021-12-26 15:35 ` [PATCH 02/34] brcmfmac: pcie: Declare missing firmware files in pcie.c Hector Martin
2021-12-26 21:04   ` Linus Walleij
2021-12-26 15:35 ` [PATCH 03/34] brcmfmac: firmware: Support having multiple alt paths Hector Martin
2022-01-02  5:31   ` Linus Walleij
2022-01-02  7:10     ` Dmitry Osipenko
2022-01-02  6:38   ` Dmitry Osipenko
2022-01-02  6:45   ` Dmitry Osipenko
2022-01-02 14:18     ` Hector Martin
2022-01-02 20:11       ` Dmitry Osipenko
2022-01-03  0:41         ` Hector Martin
2022-01-03  1:26           ` Dmitry Osipenko
2022-01-03  6:17             ` Hector Martin
2022-01-02  6:55   ` Dmitry Osipenko
2022-01-03  6:18     ` Hector Martin
2022-01-02  7:08   ` Dmitry Osipenko
2022-01-02  7:20     ` Dmitry Osipenko
2022-01-02 14:25     ` Hector Martin
2022-01-02 20:12       ` Dmitry Osipenko
2021-12-26 15:35 ` [PATCH 04/34] brcmfmac: firmware: Handle per-board clm_blob files Hector Martin
2022-01-02  6:21   ` Linus Walleij
2021-12-26 15:35 ` [PATCH 05/34] brcmfmac: pcie/sdio/usb: Get CLM blob via standard firmware mechanism Hector Martin
2022-01-02  6:22   ` Linus Walleij
2021-12-26 15:35 ` [PATCH 06/34] brcmfmac: firmware: Support passing in multiple board_types Hector Martin
2022-01-02  5:34   ` Linus Walleij
2021-12-26 15:35 ` [PATCH 07/34] brcmfmac: pcie: Read Apple OTP information Hector Martin
2022-01-02  5:38   ` Linus Walleij
2022-01-03  5:51     ` Hector Martin
2022-01-03 11:13       ` Linus Walleij
2021-12-26 15:35 ` [PATCH 08/34] brcmfmac: of: Fetch Apple properties Hector Martin
2022-01-02  5:40   ` Linus Walleij
2021-12-26 15:35 ` [PATCH 09/34] brcmfmac: pcie: Perform firmware selection for Apple platforms Hector Martin
2022-01-02  5:44   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 10/34] brcmfmac: firmware: Allow platform to override macaddr Hector Martin
2022-01-02  5:50   ` Linus Walleij
2022-01-03  5:42     ` Hector Martin
2021-12-26 15:36 ` [PATCH 11/34] brcmfmac: msgbuf: Increase RX ring sizes to 1024 Hector Martin
2022-01-02  5:50   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 12/34] brcmfmac: pcie: Fix crashes due to early IRQs Hector Martin
2022-01-02  5:51   ` Linus Walleij
2021-12-26 15:36 ` Hector Martin [this message]
2022-01-02  5:53   ` [PATCH 13/34] brcmfmac: pcie: Support PCIe core revisions >= 64 Linus Walleij
2021-12-26 15:36 ` [PATCH 14/34] brcmfmac: pcie: Add IDs/properties for BCM4378 Hector Martin
2022-01-02  5:53   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 15/34] ACPI / property: Support strings in Apple _DSM props Hector Martin
2021-12-26 18:20   ` Lukas Wunner
2022-01-02  6:20   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 16/34] brcmfmac: acpi: Add support for fetching Apple ACPI properties Hector Martin
2022-01-02  5:58   ` Linus Walleij
2022-01-03  6:03     ` Hector Martin
2022-01-03 11:14       ` Linus Walleij
     [not found]   ` <CAHp75VcZcJ+zCDL-J+w8gEeKXGYdJajjLoa1JTj_kkJixrV12Q@mail.gmail.com>
2022-01-03 17:22     ` Hector Martin
     [not found]       ` <CAHp75Vedgs_zTH2O120jtUuQiuseA0VN62TJiJ7kAi1f5nDQ6Q@mail.gmail.com>
2022-01-04  5:22         ` Hector Martin
2022-01-10  9:59     ` Kalle Valo
2021-12-26 15:36 ` [PATCH 17/34] brcmfmac: pcie: Provide a buffer of random bytes to the device Hector Martin
2022-01-02  5:59   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 18/34] brcmfmac: pcie: Add IDs/properties for BCM4355 Hector Martin
2022-01-02  6:00   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 19/34] brcmfmac: pcie: Add IDs/properties for BCM4377 Hector Martin
2022-01-02  6:01   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 20/34] brcmfmac: pcie: Perform correct BCM4364 firmware selection Hector Martin
2022-01-02  6:02   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 21/34] brcmfmac: chip: Only disable D11 cores; handle an arbitrary number Hector Martin
2022-01-02  6:03   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 22/34] brcmfmac: chip: Handle 1024-unit sizes for TCM blocks Hector Martin
2022-01-02  6:09   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 23/34] brcmfmac: cfg80211: Add support for scan params v2 Hector Martin
2022-01-02  6:23   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 24/34] brcmfmac: feature: Add support for setting feats based on WLC version Hector Martin
2022-01-02  6:11   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 25/34] brcmfmac: cfg80211: Add support for PMKID_V3 operations Hector Martin
2022-01-02  6:12   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 26/34] brcmfmac: cfg80211: Pass the PMK in binary instead of hex Hector Martin
2022-01-02  6:13   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 27/34] brcmfmac: pcie: Add IDs/properties for BCM4387 Hector Martin
2022-01-02  6:13   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 28/34] brcmfmac: pcie: Replace brcmf_pcie_copy_mem_todev with memcpy_toio Hector Martin
2022-01-02  6:15   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 29/34] brcmfmac: pcie: Read the console on init and shutdown Hector Martin
2022-01-02  6:16   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 30/34] brcmfmac: pcie: Release firmwares in the brcmf_pcie_setup error path Hector Martin
2022-01-02  6:16   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 31/34] brcmfmac: fwil: Constify iovar name arguments Hector Martin
2022-01-02  6:17   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 32/34] brcmfmac: common: Add support for downloading TxCap blobs Hector Martin
2022-01-02  6:18   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 33/34] brcmfmac: pcie: Load and provide " Hector Martin
2022-01-02  6:19   ` Linus Walleij
2021-12-26 15:36 ` [PATCH 34/34] brcmfmac: common: Add support for external calibration blobs Hector Martin
2022-01-02  6:19   ` Linus Walleij
2021-12-26 19:17 ` [RFC PATCH 00/34] brcmfmac: Support Apple T2 and M1 platforms Lukas Wunner
2021-12-26 21:42   ` Hans de Goede
2021-12-27 11:53     ` Hector Martin
2022-01-02  6:25 ` Linus Walleij
2022-01-03  6:27   ` Hector Martin
2022-01-03 10:20     ` Arend van Spriel

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