Re: [PATCH RFC 1/2] arch: Introduce ARCH_HAS_HW_XCHG_SMALL

[Arnd Bergmann <arnd@arndb.de>]

On Mon, Jul 26, 2021 at 10:36 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Sat, Jul 24, 2021 at 2:36 PM Huacai Chen <chenhuacai@loongson.cn> wrote:
> > @@ -228,6 +228,10 @@ config ARCH_HAS_FORTIFY_SOURCE
> >           An architecture should select this when it can successfully
> >           build and run with CONFIG_FORTIFY_SOURCE.
> >
> > +# Select if arch has hardware sub-word xchg/cmpxchg support
> > +config ARCH_HAS_HW_XCHG_SMALL
>
> What do you mean by "hardware"?
> Does a software fallback count?

Indeed, this needs to be clarified

> > --- a/arch/m68k/Kconfig
> > +++ b/arch/m68k/Kconfig
> > @@ -5,6 +5,7 @@ config M68K
> >         select ARCH_32BIT_OFF_T
> >         select ARCH_HAS_BINFMT_FLAT
> >         select ARCH_HAS_DMA_PREP_COHERENT if HAS_DMA && MMU && !COLDFIRE
> > +       select ARCH_HAS_HW_XCHG_SMALL
>
> M68k CPUs which support the CAS (Compare And Set) instruction do
> support this on 8-bit, 16-bit, and 32-bit quantities.
> M68k CPUs which lack CAS use a software implementation, which
> supports the same quantities.
>
> As CAS is used only if CONFIG_RMW_INSNS=y, perhaps this needs
> a dependency?

I would probably define that case as 'yes' then, defined as 'the 8-bit
and 16-bit cmpxchg/xchg helpers are no less atomic than the 32-bit
version'.

This would be in contrast to the MIPS versions that have native
32-bit and 64-bit cmpxchg() but only emulated 8-bit and 16-bit
versions.

Not sure about the parisc case, which only emulates the cmpxchg()
and xchg() based on spinlocks for any of the sizes, so they are not
atomic in regard to a concurrent READ_ONCE()/WRITE_ONCE().

       Arnd