* [PATCH v2] Coresight: etm4x: add support for Self-hosted trace
@ 2020-08-31 8:02 Jonathan Zhou
2020-09-07 21:00 ` Will Deacon
2020-09-08 9:56 ` Suzuki K Poulose
0 siblings, 2 replies; 7+ messages in thread
From: Jonathan Zhou @ 2020-08-31 8:02 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Shaokun Zhang, Catalin Marinas, Will Deacon, Jonathan Zhou,
Suzuki K Poulose
ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4
Self-hosted Trace Extensions. It provides control of exception
levels and security states. Let's add this feature detection and
enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is
supported.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
---
arch/arm64/include/asm/sysreg.h | 8 ++++++++
drivers/hwtracing/coresight/coresight-etm4x.c | 23 +++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 554a7e8ecb07..53da5f326667 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -184,6 +184,13 @@
#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
+/* Trace Filter control */
+#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
+/* Trace is allowed at EL0 */
+#define SYS_TRFCR_EL1_E0TRE BIT(0)
+/* Trace is allowed at EL1 */
+#define SYS_TRFCR_EL1_E1TRE BIT(1)
+
#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
@@ -772,6 +779,7 @@
#define ID_AA64MMFR2_CNP_SHIFT 0
/* id_aa64dfr0 */
+#define ID_AA64DFR0_SELF_HOSTED_SHIFT 40
#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
#define ID_AA64DFR0_PMSVER_SHIFT 32
#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 96425e818fc2..f72b457c2bad 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -28,6 +28,7 @@
#include <linux/perf_event.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
+#include <asm/sysreg.h>
#include <asm/sections.h>
#include <asm/local.h>
#include <asm/virt.h>
@@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info)
CS_LOCK(drvdata->base);
}
+static void etm4_init_sysctrl(void *info)
+{
+ u64 sys_trfcr_el1, dfr0;
+ int trace_filt;
+
+ dfr0 = read_sysreg(id_aa64dfr0_el1);
+
+ trace_filt = cpuid_feature_extract_unsigned_field(dfr0,
+ ID_AA64DFR0_SELF_HOSTED_SHIFT);
+ /* if selfhosted trace implemented, enable trace EL0 as default. */
+ if (trace_filt == 0x1) {
+ sys_trfcr_el1 = read_sysreg_s(SYS_TRFCR_EL1);
+ write_sysreg_s(sys_trfcr_el1 | SYS_TRFCR_EL1_E0TRE,
+ SYS_TRFCR_EL1);
+ isb();
+ }
+}
+
static void etm4_set_default_config(struct etmv4_config *config)
{
/* disable all events tracing */
@@ -1504,6 +1523,10 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
etm4_init_arch_data, drvdata, 1))
dev_err(dev, "ETM arch init failed\n");
+ if (smp_call_function_single(drvdata->cpu,
+ etm4_init_sysctrl, drvdata, 1))
+ dev_err(dev, "ETM sysctrl init failed\n");
+
ret = etm4_pm_setup_cpuslocked();
cpus_read_unlock();
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2] Coresight: etm4x: add support for Self-hosted trace
2020-08-31 8:02 [PATCH v2] Coresight: etm4x: add support for Self-hosted trace Jonathan Zhou
@ 2020-09-07 21:00 ` Will Deacon
2020-09-09 6:38 ` Jonathan Zhou
2020-09-08 9:56 ` Suzuki K Poulose
1 sibling, 1 reply; 7+ messages in thread
From: Will Deacon @ 2020-09-07 21:00 UTC (permalink / raw)
To: Jonathan Zhou, mathieu.poirier
Cc: Shaokun Zhang, Catalin Marinas, linux-arm-kernel, Suzuki K Poulose
[+ Mathieu, since he maintains the driver you're changing]
On Mon, Aug 31, 2020 at 04:02:46PM +0800, Jonathan Zhou wrote:
> ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4
> Self-hosted Trace Extensions. It provides control of exception
> levels and security states. Let's add this feature detection and
> enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is
> supported.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
> ---
> arch/arm64/include/asm/sysreg.h | 8 ++++++++
> drivers/hwtracing/coresight/coresight-etm4x.c | 23 +++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 554a7e8ecb07..53da5f326667 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -184,6 +184,13 @@
>
> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
>
> +/* Trace Filter control */
> +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
> +/* Trace is allowed at EL0 */
> +#define SYS_TRFCR_EL1_E0TRE BIT(0)
> +/* Trace is allowed at EL1 */
> +#define SYS_TRFCR_EL1_E1TRE BIT(1)
Do we also need to make sure we initialise TRFCR_EL2 correctly for the host?
Will
(keeping rest of the patch intact for Mathieu)
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 96425e818fc2..f72b457c2bad 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -28,6 +28,7 @@
> #include <linux/perf_event.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> +#include <asm/sysreg.h>
> #include <asm/sections.h>
> #include <asm/local.h>
> #include <asm/virt.h>
> @@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info)
> CS_LOCK(drvdata->base);
> }
>
> +static void etm4_init_sysctrl(void *info)
> +{
> + u64 sys_trfcr_el1, dfr0;
> + int trace_filt;
> +
> + dfr0 = read_sysreg(id_aa64dfr0_el1);
> +
> + trace_filt = cpuid_feature_extract_unsigned_field(dfr0,
> + ID_AA64DFR0_SELF_HOSTED_SHIFT);
> + /* if selfhosted trace implemented, enable trace EL0 as default. */
> + if (trace_filt == 0x1) {
> + sys_trfcr_el1 = read_sysreg_s(SYS_TRFCR_EL1);
> + write_sysreg_s(sys_trfcr_el1 | SYS_TRFCR_EL1_E0TRE,
> + SYS_TRFCR_EL1);
> + isb();
> + }
> +}
> +
> static void etm4_set_default_config(struct etmv4_config *config)
> {
> /* disable all events tracing */
> @@ -1504,6 +1523,10 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
> etm4_init_arch_data, drvdata, 1))
> dev_err(dev, "ETM arch init failed\n");
>
> + if (smp_call_function_single(drvdata->cpu,
> + etm4_init_sysctrl, drvdata, 1))
> + dev_err(dev, "ETM sysctrl init failed\n");
> +
> ret = etm4_pm_setup_cpuslocked();
> cpus_read_unlock();
>
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] Coresight: etm4x: add support for Self-hosted trace
2020-08-31 8:02 [PATCH v2] Coresight: etm4x: add support for Self-hosted trace Jonathan Zhou
2020-09-07 21:00 ` Will Deacon
@ 2020-09-08 9:56 ` Suzuki K Poulose
2020-09-09 7:56 ` Jonathan Zhou
1 sibling, 1 reply; 7+ messages in thread
From: Suzuki K Poulose @ 2020-09-08 9:56 UTC (permalink / raw)
To: jonathan.zhouwen, linux-arm-kernel
Cc: zhangshaokun, catalin.marinas, will, mathieu.poirier
On 08/31/2020 09:02 AM, Jonathan Zhou wrote:
> ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4
> Self-hosted Trace Extensions. It provides control of exception
> levels and security states. Let's add this feature detection and
> enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is
> supported.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
> ---
> arch/arm64/include/asm/sysreg.h | 8 ++++++++
> drivers/hwtracing/coresight/coresight-etm4x.c | 23 +++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 554a7e8ecb07..53da5f326667 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -184,6 +184,13 @@
>
> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
>
> +/* Trace Filter control */
> +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
> +/* Trace is allowed at EL0 */
> +#define SYS_TRFCR_EL1_E0TRE BIT(0)
> +/* Trace is allowed at EL1 */
> +#define SYS_TRFCR_EL1_E1TRE BIT(1)
> +
Please drop SYS suffix for the fields.
> #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
> #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
> #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
> @@ -772,6 +779,7 @@
> #define ID_AA64MMFR2_CNP_SHIFT 0
>
> /* id_aa64dfr0 */
> +#define ID_AA64DFR0_SELF_HOSTED_SHIFT 40
> #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
> #define ID_AA64DFR0_PMSVER_SHIFT 32
> #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 96425e818fc2..f72b457c2bad 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -28,6 +28,7 @@
> #include <linux/perf_event.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> +#include <asm/sysreg.h>
> #include <asm/sections.h>
> #include <asm/local.h>
> #include <asm/virt.h>
> @@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info)
> CS_LOCK(drvdata->base);
> }
>
> +static void etm4_init_sysctrl(void *info)
> +{
> + u64 sys_trfcr_el1, dfr0;
> + int trace_filt;
> +
> + dfr0 = read_sysreg(id_aa64dfr0_el1);
> +
> + trace_filt = cpuid_feature_extract_unsigned_field(dfr0,
> + ID_AA64DFR0_SELF_HOSTED_SHIFT);
> + /* if selfhosted trace implemented, enable trace EL0 as default. */
What about EL1 ? We do support kernel tracing. I believe we need to do
this every time when we enable etm4, based on the selected config.
Suzuki
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] Coresight: etm4x: add support for Self-hosted trace
2020-09-07 21:00 ` Will Deacon
@ 2020-09-09 6:38 ` Jonathan Zhou
0 siblings, 0 replies; 7+ messages in thread
From: Jonathan Zhou @ 2020-09-09 6:38 UTC (permalink / raw)
To: Will Deacon, mathieu.poirier
Cc: Shaokun Zhang, Catalin Marinas, linux-arm-kernel, Suzuki K Poulose
Hi Will
Thanks for your review and thanks for adding Mathieu.
On 08/09/2020 05:00, Will Deacon wrote:
> [+ Mathieu, since he maintains the driver you're changing]
>
> On Mon, Aug 31, 2020 at 04:02:46PM +0800, Jonathan Zhou wrote:
>> ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4
>> Self-hosted Trace Extensions. It provides control of exception
>> levels and security states. Let's add this feature detection and
>> enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is
>> supported.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
>> ---
>> arch/arm64/include/asm/sysreg.h | 8 ++++++++
>> drivers/hwtracing/coresight/coresight-etm4x.c | 23 +++++++++++++++++++++++
>> 2 files changed, 31 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 554a7e8ecb07..53da5f326667 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -184,6 +184,13 @@
>>
>> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
>>
>> +/* Trace Filter control */
>> +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
>> +/* Trace is allowed at EL0 */
>> +#define SYS_TRFCR_EL1_E0TRE BIT(0)
>> +/* Trace is allowed at EL1 */
>> +#define SYS_TRFCR_EL1_E1TRE BIT(1)
>
> Do we also need to make sure we initialise TRFCR_EL2 correctly for the host?
>
As Suziki said in the previous patch[1], accessing TRFCR_EL1 under EL2
will be routed to TRFCR_EL2. I just did a default config in this patch.
Actually, it should be better if we can do this based on the trace
sessions or the kernel config.
[1] https://www.spinics.net/lists/arm-kernel/msg818953.html
Regards
Jonathan
> Will
>
> (keeping rest of the patch intact for Mathieu)
>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
>> index 96425e818fc2..f72b457c2bad 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
>> @@ -28,6 +28,7 @@
>> #include <linux/perf_event.h>
>> #include <linux/pm_runtime.h>
>> #include <linux/property.h>
>> +#include <asm/sysreg.h>
>> #include <asm/sections.h>
>> #include <asm/local.h>
>> #include <asm/virt.h>
>> @@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info)
>> CS_LOCK(drvdata->base);
>> }
>>
>> +static void etm4_init_sysctrl(void *info)
>> +{
>> + u64 sys_trfcr_el1, dfr0;
>> + int trace_filt;
>> +
>> + dfr0 = read_sysreg(id_aa64dfr0_el1);
>> +
>> + trace_filt = cpuid_feature_extract_unsigned_field(dfr0,
>> + ID_AA64DFR0_SELF_HOSTED_SHIFT);
>> + /* if selfhosted trace implemented, enable trace EL0 as default. */
>> + if (trace_filt == 0x1) {
>> + sys_trfcr_el1 = read_sysreg_s(SYS_TRFCR_EL1);
>> + write_sysreg_s(sys_trfcr_el1 | SYS_TRFCR_EL1_E0TRE,
>> + SYS_TRFCR_EL1);
>> + isb();
>> + }
>> +}
>> +
>> static void etm4_set_default_config(struct etmv4_config *config)
>> {
>> /* disable all events tracing */
>> @@ -1504,6 +1523,10 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
>> etm4_init_arch_data, drvdata, 1))
>> dev_err(dev, "ETM arch init failed\n");
>>
>> + if (smp_call_function_single(drvdata->cpu,
>> + etm4_init_sysctrl, drvdata, 1))
>> + dev_err(dev, "ETM sysctrl init failed\n");
>> +
>> ret = etm4_pm_setup_cpuslocked();
>> cpus_read_unlock();
>>
>> --
>> 1.9.1
>>
> .
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] Coresight: etm4x: add support for Self-hosted trace
2020-09-08 9:56 ` Suzuki K Poulose
@ 2020-09-09 7:56 ` Jonathan Zhou
2020-09-09 9:05 ` Suzuki K Poulose
0 siblings, 1 reply; 7+ messages in thread
From: Jonathan Zhou @ 2020-09-09 7:56 UTC (permalink / raw)
To: Suzuki K Poulose, linux-arm-kernel, Mathieu Poirier
Cc: zhangshaokun, catalin.marinas, will
Hi Suzuki
Thanks for your review.
On 08/09/2020 17:56, Suzuki K Poulose wrote:
> On 08/31/2020 09:02 AM, Jonathan Zhou wrote:
>> ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4
>> Self-hosted Trace Extensions. It provides control of exception
>> levels and security states. Let's add this feature detection and
>> enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is
>> supported.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
>> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
>> ---
>> arch/arm64/include/asm/sysreg.h | 8 ++++++++
>> drivers/hwtracing/coresight/coresight-etm4x.c | 23
>> +++++++++++++++++++++++
>> 2 files changed, 31 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/sysreg.h
>> b/arch/arm64/include/asm/sysreg.h
>> index 554a7e8ecb07..53da5f326667 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -184,6 +184,13 @@
>> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
>> +/* Trace Filter control */
>> +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
>
>> +/* Trace is allowed at EL0 */
>> +#define SYS_TRFCR_EL1_E0TRE BIT(0)
>> +/* Trace is allowed at EL1 */
>> +#define SYS_TRFCR_EL1_E1TRE BIT(1)
>> +
>
> Please drop SYS suffix for the fields.
>
Thanks, I will fix this.
>> #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
>> #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
>> #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
>> @@ -772,6 +779,7 @@
>> #define ID_AA64MMFR2_CNP_SHIFT 0
>> /* id_aa64dfr0 */
>> +#define ID_AA64DFR0_SELF_HOSTED_SHIFT 40
>> #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
>> #define ID_AA64DFR0_PMSVER_SHIFT 32
>> #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
>> b/drivers/hwtracing/coresight/coresight-etm4x.c
>> index 96425e818fc2..f72b457c2bad 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
>> @@ -28,6 +28,7 @@
>> #include <linux/perf_event.h>
>> #include <linux/pm_runtime.h>
>> #include <linux/property.h>
>> +#include <asm/sysreg.h>
>> #include <asm/sections.h>
>> #include <asm/local.h>
>> #include <asm/virt.h>
>> @@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info)
>> CS_LOCK(drvdata->base);
>> }
>> +static void etm4_init_sysctrl(void *info)
>> +{
>> + u64 sys_trfcr_el1, dfr0;
>> + int trace_filt;
>> +
>> + dfr0 = read_sysreg(id_aa64dfr0_el1);
>> +
>> + trace_filt = cpuid_feature_extract_unsigned_field(dfr0,
>> + ID_AA64DFR0_SELF_HOSTED_SHIFT);
>> + /* if selfhosted trace implemented, enable trace EL0 as default. */
>
> What about EL1 ? We do support kernel tracing. I believe we need to do
> this every time when we enable etm4, based on the selected config.
>
I don't know if it's possible to run trace sessions in a guest OS, so I
left the EL1 and EL2 trace disabled. And it's right. We need to provide
an interface to select these configs include the CX and TS feilds of
TRFCR_EL2. How about a sysfs interface?
Regards.
Jonathan.
>
> Suzuki
> .
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] Coresight: etm4x: add support for Self-hosted trace
2020-09-09 7:56 ` Jonathan Zhou
@ 2020-09-09 9:05 ` Suzuki K Poulose
2020-09-15 14:43 ` Jonathan Zhou
0 siblings, 1 reply; 7+ messages in thread
From: Suzuki K Poulose @ 2020-09-09 9:05 UTC (permalink / raw)
To: jonathan.zhouwen, linux-arm-kernel, mathieu.poirier
Cc: zhangshaokun, catalin.marinas, will
On 09/09/2020 08:56 AM, Jonathan Zhou wrote:
> Hi Suzuki
>
> Thanks for your review.
>
> On 08/09/2020 17:56, Suzuki K Poulose wrote:
>> On 08/31/2020 09:02 AM, Jonathan Zhou wrote:
>>> ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4
>>> Self-hosted Trace Extensions. It provides control of exception
>>> levels and security states. Let's add this feature detection and
>>> enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is
>>> supported.
>>>
>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>> Cc: Will Deacon <will@kernel.org>
>>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
>>> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
>>> ---
>>> arch/arm64/include/asm/sysreg.h | 8 ++++++++
>>> drivers/hwtracing/coresight/coresight-etm4x.c | 23
>>> +++++++++++++++++++++++
>>> 2 files changed, 31 insertions(+)
>>>
>>> diff --git a/arch/arm64/include/asm/sysreg.h
>>> b/arch/arm64/include/asm/sysreg.h
>>> index 554a7e8ecb07..53da5f326667 100644
>>> --- a/arch/arm64/include/asm/sysreg.h
>>> +++ b/arch/arm64/include/asm/sysreg.h
>>> @@ -184,6 +184,13 @@
>>> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
>>> +/* Trace Filter control */
>>> +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
>>
>>> +/* Trace is allowed at EL0 */
>>> +#define SYS_TRFCR_EL1_E0TRE BIT(0)
>>> +/* Trace is allowed at EL1 */
>>> +#define SYS_TRFCR_EL1_E1TRE BIT(1)
>>> +
>>
>> Please drop SYS suffix for the fields.
>>
> Thanks, I will fix this.
>
>>> #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
>>> #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
>>> #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
>>> @@ -772,6 +779,7 @@
>>> #define ID_AA64MMFR2_CNP_SHIFT 0
>>> /* id_aa64dfr0 */
>>> +#define ID_AA64DFR0_SELF_HOSTED_SHIFT 40
>>> #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
>>> #define ID_AA64DFR0_PMSVER_SHIFT 32
>>> #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
>>> b/drivers/hwtracing/coresight/coresight-etm4x.c
>>> index 96425e818fc2..f72b457c2bad 100644
>>> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
>>> @@ -28,6 +28,7 @@
>>> #include <linux/perf_event.h>
>>> #include <linux/pm_runtime.h>
>>> #include <linux/property.h>
>>> +#include <asm/sysreg.h>
>>> #include <asm/sections.h>
>>> #include <asm/local.h>
>>> #include <asm/virt.h>
>>> @@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info)
>>> CS_LOCK(drvdata->base);
>>> }
>>> +static void etm4_init_sysctrl(void *info)
>>> +{
>>> + u64 sys_trfcr_el1, dfr0;
>>> + int trace_filt;
>>> +
>>> + dfr0 = read_sysreg(id_aa64dfr0_el1);
>>> +
>>> + trace_filt = cpuid_feature_extract_unsigned_field(dfr0,
>>> + ID_AA64DFR0_SELF_HOSTED_SHIFT);
>>> + /* if selfhosted trace implemented, enable trace EL0 as default. */
>>
>> What about EL1 ? We do support kernel tracing. I believe we need to do
>> this every time when we enable etm4, based on the selected config.
>>
> I don't know if it's possible to run trace sessions in a guest OS, so I
> left the EL1 and EL2 trace disabled. And it's right. We need to provide
> an interface to select these configs include the CX and TS feilds of
> TRFCR_EL2. How about a sysfs interface?
No, you don't need any additional interfaces. The etm4_config should
tell us, if the ETM4 is supposed to filter events for kernel/userspace.
We don't have virtualization support yet, so we could ignore the
TRFCR_EL2, for now.
Either we :
1) Unconditionally enable EL1 & EL0 tracing on each ETMv4 instance
at probe time and leave the trace exclusion by EL to deal with the
kernel/userspace filtering.
OR
2) For each session of ETMv4 tracing, program the EL1 and EL0 trace
in TRFCR_EL1 based on the exclusion requested by ELs in the configs.
I prefer (1). Also, we must enable CX for TRFCR_EL2, if we are in VHE
to allow contextid tracing.
TS could be set to 0b01 in either case, to use the virtual timestamp.
Suzuki
>
> Regards.
> Jonathan.
>>
>> Suzuki
>> .
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] Coresight: etm4x: add support for Self-hosted trace
2020-09-09 9:05 ` Suzuki K Poulose
@ 2020-09-15 14:43 ` Jonathan Zhou
0 siblings, 0 replies; 7+ messages in thread
From: Jonathan Zhou @ 2020-09-15 14:43 UTC (permalink / raw)
To: Suzuki K Poulose, linux-arm-kernel, mathieu.poirier
Cc: zhangshaokun, catalin.marinas, will
On 09/09/2020 17:05, Suzuki K Poulose wrote:
> On 09/09/2020 08:56 AM, Jonathan Zhou wrote:
>> Hi Suzuki
>>
>> Thanks for your review.
>>
>> On 08/09/2020 17:56, Suzuki K Poulose wrote:
>>> On 08/31/2020 09:02 AM, Jonathan Zhou wrote:
>>>> ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4
>>>> Self-hosted Trace Extensions. It provides control of exception
>>>> levels and security states. Let's add this feature detection and
>>>> enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is
>>>> supported.
>>>>
>>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>>> Cc: Will Deacon <will@kernel.org>
>>>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
>>>> Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
>>>> ---
>>>> arch/arm64/include/asm/sysreg.h | 8 ++++++++
>>>> drivers/hwtracing/coresight/coresight-etm4x.c | 23
>>>> +++++++++++++++++++++++
>>>> 2 files changed, 31 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/include/asm/sysreg.h
>>>> b/arch/arm64/include/asm/sysreg.h
>>>> index 554a7e8ecb07..53da5f326667 100644
>>>> --- a/arch/arm64/include/asm/sysreg.h
>>>> +++ b/arch/arm64/include/asm/sysreg.h
>>>> @@ -184,6 +184,13 @@
>>>> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
>>>> +/* Trace Filter control */
>>>> +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
>>>
>>>> +/* Trace is allowed at EL0 */
>>>> +#define SYS_TRFCR_EL1_E0TRE BIT(0)
>>>> +/* Trace is allowed at EL1 */
>>>> +#define SYS_TRFCR_EL1_E1TRE BIT(1)
>>>> +
>>>
>>> Please drop SYS suffix for the fields.
>>>
>> Thanks, I will fix this.
>>
>>>> #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
>>>> #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
>>>> #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
>>>> @@ -772,6 +779,7 @@
>>>> #define ID_AA64MMFR2_CNP_SHIFT 0
>>>> /* id_aa64dfr0 */
>>>> +#define ID_AA64DFR0_SELF_HOSTED_SHIFT 40
>>>> #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
>>>> #define ID_AA64DFR0_PMSVER_SHIFT 32
>>>> #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
>>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
>>>> b/drivers/hwtracing/coresight/coresight-etm4x.c
>>>> index 96425e818fc2..f72b457c2bad 100644
>>>> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
>>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
>>>> @@ -28,6 +28,7 @@
>>>> #include <linux/perf_event.h>
>>>> #include <linux/pm_runtime.h>
>>>> #include <linux/property.h>
>>>> +#include <asm/sysreg.h>
>>>> #include <asm/sections.h>
>>>> #include <asm/local.h>
>>>> #include <asm/virt.h>
>>>> @@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info)
>>>> CS_LOCK(drvdata->base);
>>>> }
>>>> +static void etm4_init_sysctrl(void *info)
>>>> +{
>>>> + u64 sys_trfcr_el1, dfr0;
>>>> + int trace_filt;
>>>> +
>>>> + dfr0 = read_sysreg(id_aa64dfr0_el1);
>>>> +
>>>> + trace_filt = cpuid_feature_extract_unsigned_field(dfr0,
>>>> + ID_AA64DFR0_SELF_HOSTED_SHIFT);
>>>> + /* if selfhosted trace implemented, enable trace EL0 as
>>>> default. */
>>>
>>> What about EL1 ? We do support kernel tracing. I believe we need to do
>>> this every time when we enable etm4, based on the selected config.
>>>
>> I don't know if it's possible to run trace sessions in a guest OS, so I
>> left the EL1 and EL2 trace disabled. And it's right. We need to provide
>> an interface to select these configs include the CX and TS feilds of
>> TRFCR_EL2. How about a sysfs interface?
>
> No, you don't need any additional interfaces. The etm4_config should
> tell us, if the ETM4 is supposed to filter events for kernel/userspace.
> We don't have virtualization support yet, so we could ignore the
> TRFCR_EL2, for now.
>
Thanks, virtualization is really something out of my mind.
> Either we :
>
> 1) Unconditionally enable EL1 & EL0 tracing on each ETMv4 instance
> at probe time and leave the trace exclusion by EL to deal with the
> kernel/userspace filtering.
>
> OR
>
> 2) For each session of ETMv4 tracing, program the EL1 and EL0 trace
> in TRFCR_EL1 based on the exclusion requested by ELs in the configs.
>
> I prefer (1). Also, we must enable CX for TRFCR_EL2, if we are in VHE
> to allow contextid tracing.
>
Yes, (1) seems to be better. Programming TRFCR_ELx based on the ETM
viewinst ELs' configs looks a little strange, for they are filters on
different level. I will apply this in PATCH V3.
Regards.
Jonathan
> TS could be set to 0b01 in either case, to use the virtual timestamp.
>
> Suzuki
>
>
>
>
>
>>
>> Regards.
>> Jonathan.
>>>
>>> Suzuki
>>> .
>>
>
> .
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-09-15 14:45 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-31 8:02 [PATCH v2] Coresight: etm4x: add support for Self-hosted trace Jonathan Zhou
2020-09-07 21:00 ` Will Deacon
2020-09-09 6:38 ` Jonathan Zhou
2020-09-08 9:56 ` Suzuki K Poulose
2020-09-09 7:56 ` Jonathan Zhou
2020-09-09 9:05 ` Suzuki K Poulose
2020-09-15 14:43 ` Jonathan Zhou
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