[PATCH v2 0/4] Fine tune USB 3.0 PHY on exynos5420

[PATCH v2 0/4] Fine tune USB 3.0 PHY on exynos5420

[Vivek Gautam]

This series is based on Heikki's patches for simpliefied phy lookup table:
[PATCHv2 0/6] phy: simplified phy lookup [1], applied against 'next' branch
of Kishon's linux-phy tree.

Changes since v1:
1) Using 'gen_phy' member of 'hcd' instead of declaring more variables
   to hold phys.
2) Added a check for compatible match for 'Synopsys-dwc3' controller,
   since the 'gen_phy' member of 'hcd' already gets the 'usb' PHY
   in core/hcd.c; but XHCI on Synopsys-dwc3 doesn't need that,
   instead two separate PHYs for UTMI+ and PIPE3 for the two HCDs
   (main hcd and shared hcd).
3) Restructured the code in 'xhci_plat_setup()' and 'xhci_plat_resume()'
   to use hcd->gen_phy directly. Also added the check for Synopsys's DWC3
   controller while trying to calibrate the PHY.

Explanation for the need of this patch-series:
"The DWC3-exynos eXtensible host controller present on Exynos5420/5800
SoCs is quirky. The PHY serving this controller operates at High-Speed
by default, so it detects even Super-speed devices as high-speed ones.
Certain PHY parameters like Tx LOS levels and Boost levels need to be
calibrated further post initialization of xHCI controller, to get
SuperSpeed operations working."

[1] https://lkml.org/lkml/2014/6/5/358

Vivek Gautam (4):
  phy: Add provision for calibrating phy.
  usb: host: xhci-plat: Get PHYs for xhci's hcds
  usb: host: xhci-plat: Caibrate PHY post host reset
  phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800

 drivers/phy/phy-core.c           |   36 ++++++++
 drivers/phy/phy-exynos5-usbdrd.c |  169 ++++++++++++++++++++++++++++++++++++++
 drivers/usb/host/xhci-plat.c     |   75 ++++++++++++++++-
 include/linux/phy/phy.h          |    8 ++
 4 files changed, 286 insertions(+), 2 deletions(-)

-- 
1.7.10.4

[PATCH v2 1/4] phy: Add provision for calibrating phy.

[Vivek Gautam]

Some PHY controllers may need to calibrate certain
PHY settings after initialization of the controller and
sometimes even after initializing the PHY-consumer too.
Add support for the same in order to let consumers do so in need.

Signed-off-by: vivek Gautam <gautam.vivek@samsung.com>
---
 drivers/phy/phy-core.c  |   36 ++++++++++++++++++++++++++++++++++++
 include/linux/phy/phy.h |    8 ++++++++
 2 files changed, 44 insertions(+)

diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 74d4346..92d31a3 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -376,6 +376,42 @@ int phy_power_off(struct phy *phy)
 EXPORT_SYMBOL_GPL(phy_power_off);
 
 /**
+ * phy_calibrate - calibrate a phy post initialization
+ * @phy: Pointer to 'phy' from consumer
+ *
+ * For certain PHYs, it may be needed to calibrate few phy parameters
+ * post initialization. The need to calibrate may arise after the
+ * initialization of consumer itself, in order to prevent further any
+ * loss of phy settings post consumer-initialization.
+ *	example: USB 3.0 DRD PHY on Exynos5420/5800 systems is one such
+ *	phy which needs calibration after the host controller reset
+ *	has happened.
+ */
+int phy_calibrate(struct phy *phy)
+{
+	int ret = -ENOTSUPP;
+
+	if (!phy)
+		return 0;
+
+	mutex_lock(&phy->mutex);
+	if (phy->ops->calibrate) {
+		ret =  phy->ops->calibrate(phy);
+		if (ret < 0) {
+			dev_err(&phy->dev,
+				"phy calibration failed --> %d\n", ret);
+			goto out;
+		}
+	}
+
+out:
+	mutex_unlock(&phy->mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(phy_calibrate);
+
+/**
  * _of_phy_get() - lookup and obtain a reference to a phy by phandle
  * @np: device_node for which to get the phy
  * @index: the index of the phy
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 5a537a5..b7f33ee 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -27,6 +27,7 @@ struct phy;
  * @exit: operation to be performed while exiting
  * @power_on: powering on the phy
  * @power_off: powering off the phy
+ * @calibrate: calibrate the phy post init
  * @owner: the module owner containing the ops
  */
 struct phy_ops {
@@ -34,6 +35,7 @@ struct phy_ops {
 	int	(*exit)(struct phy *phy);
 	int	(*power_on)(struct phy *phy);
 	int	(*power_off)(struct phy *phy);
+	int	(*calibrate)(struct phy *phy);
 	struct module *owner;
 };
 
@@ -124,6 +126,7 @@ int phy_init(struct phy *phy);
 int phy_exit(struct phy *phy);
 int phy_power_on(struct phy *phy);
 int phy_power_off(struct phy *phy);
+int phy_calibrate(struct phy *phy);
 static inline int phy_get_bus_width(struct phy *phy)
 {
 	return phy->attrs.bus_width;
@@ -227,6 +230,11 @@ static inline int phy_power_off(struct phy *phy)
 	return -ENOSYS;
 }
 
+static inline int phy_calibrate(struct phy *phy)
+{
+	return -ENOSYS;
+}
+
 static inline int phy_get_bus_width(struct phy *phy)
 {
 	return -ENOSYS;
-- 
1.7.10.4

[PATCH v2 2/4] usb: host: xhci-plat: Get PHYs for xhci's hcds

[Vivek Gautam]

The host controller by itself may sometimes need to handle PHY
and/or calibrate some of the PHY settings to get full support out
of the PHY controller. The PHY core provides a calibration
funtionality now to do so.
Therefore, facilitate getting the two possible PHYs, viz.
USB 2.0 type (UTMI+) and USB 3.0 type (PIPE3), provided
by the parent - Synopsys's DWC3 controller

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 drivers/usb/host/xhci-plat.c |   36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 29d8adb..e50bd7d 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/phy/phy.h>
 #include <linux/slab.h>
 
 #include "xhci.h"
@@ -101,6 +102,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
 	struct clk              *clk;
 	int			ret;
 	int			irq;
+	struct device		*parent;
 
 	if (usb_disabled())
 		return -ENODEV;
@@ -165,6 +167,23 @@ static int xhci_plat_probe(struct platform_device *pdev)
 			goto unmap_registers;
 	}
 
+	parent = pdev->dev.parent;
+	/*
+	 * Get possile USB 2.0 type PHY (UTMI+) registered by xhci's parent:
+	 * Synopsys-dwc3
+	 */
+	if (of_device_is_compatible(parent->of_node, "synopsys,dwc3") ||
+	    of_device_is_compatible(parent->of_node, "snps,dwc3")) {
+		hcd->gen_phy = devm_phy_get(&pdev->dev, "usb2-phy");
+		if (IS_ERR(hcd->gen_phy)) {
+			ret = PTR_ERR(hcd->gen_phy);
+			if (ret != -ENOSYS && ret != -ENODEV) {
+				dev_err(&pdev->dev, "no usb2 phy configured\n");
+				return ret;
+			}
+		}
+	}
+
 	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
 	if (ret)
 		goto disable_clk;
@@ -191,6 +210,23 @@ static int xhci_plat_probe(struct platform_device *pdev)
 	if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
 		xhci->shared_hcd->can_do_streams = 1;
 
+	/*
+	 * Get possile USB 3.0 type PHY (PIPE3) registered by xhci's parent:
+	 * Synopsys-dwc3
+	 */
+	if (of_device_is_compatible(parent->of_node, "synopsys,dwc3") ||
+	    of_device_is_compatible(parent->of_node, "snps,dwc3")) {
+		xhci->shared_hcd->gen_phy = devm_phy_get(&pdev->dev,
+							 "usb3-phy");
+		if (IS_ERR(xhci->shared_hcd->gen_phy)) {
+			ret = PTR_ERR(xhci->shared_hcd->gen_phy);
+			if (ret != -ENOSYS && ret != -ENODEV) {
+				dev_err(&pdev->dev, "no usb3 phy configured\n");
+				return ret;
+			}
+		}
+	}
+
 	ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
 	if (ret)
 		goto put_usb3_hcd;
-- 
1.7.10.4

[PATCH v2 2/4] usb: host: xhci-plat: Get PHYs for xhci's hcds

[Julius Werner]

On Wed, Jul 9, 2014 at 3:01 AM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> The host controller by itself may sometimes need to handle PHY
> and/or calibrate some of the PHY settings to get full support out
> of the PHY controller. The PHY core provides a calibration
> funtionality now to do so.
> Therefore, facilitate getting the two possible PHYs, viz.
> USB 2.0 type (UTMI+) and USB 3.0 type (PIPE3), provided
> by the parent - Synopsys's DWC3 controller
>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> ---
>  drivers/usb/host/xhci-plat.c |   36 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>
> diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
> index 29d8adb..e50bd7d 100644
> --- a/drivers/usb/host/xhci-plat.c
> +++ b/drivers/usb/host/xhci-plat.c
> @@ -16,6 +16,7 @@
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
>  #include <linux/slab.h>
>
>  #include "xhci.h"
> @@ -101,6 +102,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
>         struct clk              *clk;
>         int                     ret;
>         int                     irq;
> +       struct device           *parent;
>
>         if (usb_disabled())
>                 return -ENODEV;
> @@ -165,6 +167,23 @@ static int xhci_plat_probe(struct platform_device *pdev)
>                         goto unmap_registers;
>         }
>
> +       parent = pdev->dev.parent;
> +       /*
> +        * Get possile USB 2.0 type PHY (UTMI+) registered by xhci's parent:
> +        * Synopsys-dwc3
> +        */
> +       if (of_device_is_compatible(parent->of_node, "synopsys,dwc3") ||
> +           of_device_is_compatible(parent->of_node, "snps,dwc3")) {
> +               hcd->gen_phy = devm_phy_get(&pdev->dev, "usb2-phy");
> +               if (IS_ERR(hcd->gen_phy)) {
> +                       ret = PTR_ERR(hcd->gen_phy);
> +                       if (ret != -ENOSYS && ret != -ENODEV) {
> +                               dev_err(&pdev->dev, "no usb2 phy configured\n");
> +                               return ret;
> +                       }
> +               }
> +       }

Why does this need to check for DWC3? I think this code should be as
generic as possible. Can't you just devm_phy_get("usb2-phy"), and keep
going with a dev_dbg() message if it fails? If the platform has a phy
it will find it, if not that's fine too.

Looks like Heikki's patch assigns the phy names in DWC3-specific code,
so I'm not sure if they are supposed to be specific to that
controller... but DWC3 is the only merged XHCI controller this applys
to right now, so why not make that a general convention? The concept
of having one "usb2-phy" and one "usb3-phy" is probably common across
most xHC implementations (unless they share a single phy in which case
they could just leave one of them unset), so it will be much easier to
handle if they all chose the same two names for those (and we can
avoid a big list of special cases here).

> +
>         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
>         if (ret)
>                 goto disable_clk;
> @@ -191,6 +210,23 @@ static int xhci_plat_probe(struct platform_device *pdev)
>         if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
>                 xhci->shared_hcd->can_do_streams = 1;
>
> +       /*
> +        * Get possile USB 3.0 type PHY (PIPE3) registered by xhci's parent:
> +        * Synopsys-dwc3
> +        */
> +       if (of_device_is_compatible(parent->of_node, "synopsys,dwc3") ||
> +           of_device_is_compatible(parent->of_node, "snps,dwc3")) {
> +               xhci->shared_hcd->gen_phy = devm_phy_get(&pdev->dev,
> +                                                        "usb3-phy");
> +               if (IS_ERR(xhci->shared_hcd->gen_phy)) {
> +                       ret = PTR_ERR(xhci->shared_hcd->gen_phy);
> +                       if (ret != -ENOSYS && ret != -ENODEV) {
> +                               dev_err(&pdev->dev, "no usb3 phy configured\n");
> +                               return ret;
> +                       }
> +               }
> +       }
> +
>         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
>         if (ret)
>                 goto put_usb3_hcd;
> --
> 1.7.10.4
>

[PATCH v2 2/4] usb: host: xhci-plat: Get PHYs for xhci's hcds

[Vivek Gautam]

Hi Julius,


On Wed, Jul 9, 2014 at 11:26 PM, Julius Werner <jwerner@chromium.org> wrote:
> On Wed, Jul 9, 2014 at 3:01 AM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>> The host controller by itself may sometimes need to handle PHY
>> and/or calibrate some of the PHY settings to get full support out
>> of the PHY controller. The PHY core provides a calibration
>> funtionality now to do so.
>> Therefore, facilitate getting the two possible PHYs, viz.
>> USB 2.0 type (UTMI+) and USB 3.0 type (PIPE3), provided
>> by the parent - Synopsys's DWC3 controller
>>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> ---
>>  drivers/usb/host/xhci-plat.c |   36 ++++++++++++++++++++++++++++++++++++
>>  1 file changed, 36 insertions(+)
>>
>> diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
>> index 29d8adb..e50bd7d 100644
>> --- a/drivers/usb/host/xhci-plat.c
>> +++ b/drivers/usb/host/xhci-plat.c
>> @@ -16,6 +16,7 @@
>>  #include <linux/module.h>
>>  #include <linux/of.h>
>>  #include <linux/platform_device.h>
>> +#include <linux/phy/phy.h>
>>  #include <linux/slab.h>
>>
>>  #include "xhci.h"
>> @@ -101,6 +102,7 @@ static int xhci_plat_probe(struct platform_device *pdev)
>>         struct clk              *clk;
>>         int                     ret;
>>         int                     irq;
>> +       struct device           *parent;
>>
>>         if (usb_disabled())
>>                 return -ENODEV;
>> @@ -165,6 +167,23 @@ static int xhci_plat_probe(struct platform_device *pdev)
>>                         goto unmap_registers;
>>         }
>>
>> +       parent = pdev->dev.parent;
>> +       /*
>> +        * Get possile USB 2.0 type PHY (UTMI+) registered by xhci's parent:
>> +        * Synopsys-dwc3
>> +        */
>> +       if (of_device_is_compatible(parent->of_node, "synopsys,dwc3") ||
>> +           of_device_is_compatible(parent->of_node, "snps,dwc3")) {
>> +               hcd->gen_phy = devm_phy_get(&pdev->dev, "usb2-phy");
>> +               if (IS_ERR(hcd->gen_phy)) {
>> +                       ret = PTR_ERR(hcd->gen_phy);
>> +                       if (ret != -ENOSYS && ret != -ENODEV) {
>> +                               dev_err(&pdev->dev, "no usb2 phy configured\n");
>> +                               return ret;
>> +                       }
>> +               }
>> +       }
>
> Why does this need to check for DWC3? I think this code should be as
> generic as possible. Can't you just devm_phy_get("usb2-phy"), and keep
> going with a dev_dbg() message if it fails? If the platform has a phy
> it will find it, if not that's fine too.

Right, i was misled with the phy requisition in usb_add_hcd(), which i
thought would be
called first, and we would have been trying to overwrite the 'gen_phy'
member here. My bad!!

You are right, in this case we will not need the check for DWC3, and
we will still have the
liberty to get two different PHYs (usb2-phy and usb3-phy).

>
> Looks like Heikki's patch assigns the phy names in DWC3-specific code,
> so I'm not sure if they are supposed to be specific to that
> controller... but DWC3 is the only merged XHCI controller this applys
> to right now, so why not make that a general convention? The concept
> of having one "usb2-phy" and one "usb3-phy" is probably common across
> most xHC implementations (unless they share a single phy in which case
> they could just leave one of them unset), so it will be much easier to
> handle if they all chose the same two names for those (and we can
> avoid a big list of special cases here).

Right, i will remove these checks then, and let this be generic so that each
xHCI could get 'usb2-phy' and 'usb3-phy', if it's available.

>
>> +
>>         ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
>>         if (ret)
>>                 goto disable_clk;
>> @@ -191,6 +210,23 @@ static int xhci_plat_probe(struct platform_device *pdev)
>>         if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
>>                 xhci->shared_hcd->can_do_streams = 1;
>>
>> +       /*
>> +        * Get possile USB 3.0 type PHY (PIPE3) registered by xhci's parent:
>> +        * Synopsys-dwc3
>> +        */
>> +       if (of_device_is_compatible(parent->of_node, "synopsys,dwc3") ||
>> +           of_device_is_compatible(parent->of_node, "snps,dwc3")) {
>> +               xhci->shared_hcd->gen_phy = devm_phy_get(&pdev->dev,
>> +                                                        "usb3-phy");
>> +               if (IS_ERR(xhci->shared_hcd->gen_phy)) {
>> +                       ret = PTR_ERR(xhci->shared_hcd->gen_phy);
>> +                       if (ret != -ENOSYS && ret != -ENODEV) {
>> +                               dev_err(&pdev->dev, "no usb3 phy configured\n");
>> +                               return ret;
>> +                       }
>> +               }
>> +       }
>> +
>>         ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
>>         if (ret)
>>                 goto put_usb3_hcd;
>> --
>> 1.7.10.4
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
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> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

[PATCH v2 3/4] usb: host: xhci-plat: Caibrate PHY post host reset

[Vivek Gautam]

Some quirky PHYs may require to be calibrated post the host
controller initialization.
The USB 3.0 DRD PHY on Exynos5420/5800 systems, coming along with
Synopsys's DWC3 controller, is one such PHY which needs to be
calibrated post xhci's reset at initialization time and at
resume time, to get the controller work at SuperSpeed.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 drivers/usb/host/xhci-plat.c |   39 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 37 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index e50bd7d..decf349 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -35,7 +35,27 @@ static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
 /* called during probe() after chip reset completes */
 static int xhci_plat_setup(struct usb_hcd *hcd)
 {
-	return xhci_gen_setup(hcd, xhci_plat_quirks);
+	struct device *parent;
+	int ret;
+
+	ret = xhci_gen_setup(hcd, xhci_plat_quirks);
+	if (ret) {
+		dev_err(hcd->self.controller, "xhci setup failed\n");
+		return ret;
+	}
+
+	parent = hcd->self.controller->parent;
+	if (of_device_is_compatible(parent->of_node, "synopsys,dwc3") ||
+	    of_device_is_compatible(parent->of_node, "snps,dwc3")) {
+		if (!IS_ERR(hcd->gen_phy)) {
+			ret = phy_calibrate(hcd->gen_phy);
+			if (ret < 0 && ret != -ENOTSUPP)
+				dev_err(hcd->self.controller,
+					"failed to calibrate USB PHY\n");
+		}
+	}
+
+	return ret;
 }
 
 static int xhci_plat_start(struct usb_hcd *hcd)
@@ -288,8 +308,23 @@ static int xhci_plat_resume(struct device *dev)
 {
 	struct usb_hcd	*hcd = dev_get_drvdata(dev);
 	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
+	int ret;
+
+	ret = xhci_resume(xhci, 0);
+	if (ret)
+		return ret;
 
-	return xhci_resume(xhci, 0);
+	if (of_device_is_compatible(dev->parent->of_node, "synopsys,dwc3") ||
+	    of_device_is_compatible(dev->parent->of_node, "snps,dwc3")) {
+		if (!IS_ERR(hcd->gen_phy)) {
+			ret = phy_calibrate(hcd->gen_phy);
+			if (ret < 0 && ret != -ENOTSUPP)
+				dev_err(hcd->self.controller,
+					"failed to calibrate USB PHY\n");
+		}
+	}
+
+	return ret;
 }
 
 static const struct dev_pm_ops xhci_plat_pm_ops = {
-- 
1.7.10.4

[PATCH v2 3/4] usb: host: xhci-plat: Caibrate PHY post host reset

[Julius Werner]

On Wed, Jul 9, 2014 at 3:01 AM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
> Some quirky PHYs may require to be calibrated post the host
> controller initialization.
> The USB 3.0 DRD PHY on Exynos5420/5800 systems, coming along with
> Synopsys's DWC3 controller, is one such PHY which needs to be
> calibrated post xhci's reset at initialization time and at
> resume time, to get the controller work at SuperSpeed.
>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> ---
>  drivers/usb/host/xhci-plat.c |   39 +++++++++++++++++++++++++++++++++++++--
>  1 file changed, 37 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
> index e50bd7d..decf349 100644
> --- a/drivers/usb/host/xhci-plat.c
> +++ b/drivers/usb/host/xhci-plat.c
> @@ -35,7 +35,27 @@ static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
>  /* called during probe() after chip reset completes */
>  static int xhci_plat_setup(struct usb_hcd *hcd)
>  {
> -       return xhci_gen_setup(hcd, xhci_plat_quirks);
> +       struct device *parent;
> +       int ret;
> +
> +       ret = xhci_gen_setup(hcd, xhci_plat_quirks);
> +       if (ret) {
> +               dev_err(hcd->self.controller, "xhci setup failed\n");
> +               return ret;
> +       }
> +
> +       parent = hcd->self.controller->parent;
> +       if (of_device_is_compatible(parent->of_node, "synopsys,dwc3") ||
> +           of_device_is_compatible(parent->of_node, "snps,dwc3")) {
> +               if (!IS_ERR(hcd->gen_phy)) {
> +                       ret = phy_calibrate(hcd->gen_phy);
> +                       if (ret < 0 && ret != -ENOTSUPP)
> +                               dev_err(hcd->self.controller,
> +                                       "failed to calibrate USB PHY\n");
> +               }
> +       }

Here as well, is it really necessary to special-case it so much? I'd
say if there is a PHY and it has a calibrate function bound we call
it, and if not we just go ahead.

I also think that this would fit better in core/hcd.c since it's not
really XHCI specific... it's conceivable that an EHCI controller might
also need to tune some PHY settings after reset (in fact Tegra does
something similar, although it already has another hack for that now),
so if we introduce this general facility why not offer it to
everyone?.

> +
> +       return ret;
>  }
>
>  static int xhci_plat_start(struct usb_hcd *hcd)
> @@ -288,8 +308,23 @@ static int xhci_plat_resume(struct device *dev)
>  {
>         struct usb_hcd  *hcd = dev_get_drvdata(dev);
>         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
> +       int ret;
> +
> +       ret = xhci_resume(xhci, 0);
> +       if (ret)
> +               return ret;
>
> -       return xhci_resume(xhci, 0);
> +       if (of_device_is_compatible(dev->parent->of_node, "synopsys,dwc3") ||
> +           of_device_is_compatible(dev->parent->of_node, "snps,dwc3")) {
> +               if (!IS_ERR(hcd->gen_phy)) {
> +                       ret = phy_calibrate(hcd->gen_phy);
> +                       if (ret < 0 && ret != -ENOTSUPP)
> +                               dev_err(hcd->self.controller,
> +                                       "failed to calibrate USB PHY\n");
> +               }
> +       }
> +
> +       return ret;
>  }
>
>  static const struct dev_pm_ops xhci_plat_pm_ops = {
> --
> 1.7.10.4
>

[PATCH v2 3/4] usb: host: xhci-plat: Caibrate PHY post host reset

[Vivek Gautam]

On Wed, Jul 9, 2014 at 11:28 PM, Julius Werner <jwerner@chromium.org> wrote:
> On Wed, Jul 9, 2014 at 3:01 AM, Vivek Gautam <gautam.vivek@samsung.com> wrote:
>> Some quirky PHYs may require to be calibrated post the host
>> controller initialization.
>> The USB 3.0 DRD PHY on Exynos5420/5800 systems, coming along with
>> Synopsys's DWC3 controller, is one such PHY which needs to be
>> calibrated post xhci's reset at initialization time and at
>> resume time, to get the controller work at SuperSpeed.
>>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> ---
>>  drivers/usb/host/xhci-plat.c |   39 +++++++++++++++++++++++++++++++++++++--
>>  1 file changed, 37 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
>> index e50bd7d..decf349 100644
>> --- a/drivers/usb/host/xhci-plat.c
>> +++ b/drivers/usb/host/xhci-plat.c
>> @@ -35,7 +35,27 @@ static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
>>  /* called during probe() after chip reset completes */
>>  static int xhci_plat_setup(struct usb_hcd *hcd)
>>  {
>> -       return xhci_gen_setup(hcd, xhci_plat_quirks);
>> +       struct device *parent;
>> +       int ret;
>> +
>> +       ret = xhci_gen_setup(hcd, xhci_plat_quirks);
>> +       if (ret) {
>> +               dev_err(hcd->self.controller, "xhci setup failed\n");
>> +               return ret;
>> +       }
>> +
>> +       parent = hcd->self.controller->parent;
>> +       if (of_device_is_compatible(parent->of_node, "synopsys,dwc3") ||
>> +           of_device_is_compatible(parent->of_node, "snps,dwc3")) {
>> +               if (!IS_ERR(hcd->gen_phy)) {
>> +                       ret = phy_calibrate(hcd->gen_phy);
>> +                       if (ret < 0 && ret != -ENOTSUPP)
>> +                               dev_err(hcd->self.controller,
>> +                                       "failed to calibrate USB PHY\n");
>> +               }
>> +       }
>
> Here as well, is it really necessary to special-case it so much? I'd
> say if there is a PHY and it has a calibrate function bound we call
> it, and if not we just go ahead.
>
> I also think that this would fit better in core/hcd.c since it's not
> really XHCI specific... it's conceivable that an EHCI controller might
> also need to tune some PHY settings after reset (in fact Tegra does
> something similar, although it already has another hack for that now),
> so if we introduce this general facility why not offer it to
> everyone?.

True, lets move it to core/hcd.c to make the entire calibration thing
more generic.

>
>> +
>> +       return ret;
>>  }
>>
>>  static int xhci_plat_start(struct usb_hcd *hcd)
>> @@ -288,8 +308,23 @@ static int xhci_plat_resume(struct device *dev)
>>  {
>>         struct usb_hcd  *hcd = dev_get_drvdata(dev);
>>         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
>> +       int ret;
>> +
>> +       ret = xhci_resume(xhci, 0);
>> +       if (ret)
>> +               return ret;
>>
>> -       return xhci_resume(xhci, 0);
>> +       if (of_device_is_compatible(dev->parent->of_node, "synopsys,dwc3") ||
>> +           of_device_is_compatible(dev->parent->of_node, "snps,dwc3")) {
>> +               if (!IS_ERR(hcd->gen_phy)) {
>> +                       ret = phy_calibrate(hcd->gen_phy);
>> +                       if (ret < 0 && ret != -ENOTSUPP)
>> +                               dev_err(hcd->self.controller,
>> +                                       "failed to calibrate USB PHY\n");
>> +               }
>> +       }
>> +
>> +       return ret;
>>  }
>>
>>  static const struct dev_pm_ops xhci_plat_pm_ops = {
>> --
>> 1.7.10.4
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India

[PATCH v2 4/4] phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800

[Vivek Gautam]

Adding phy calibrate callback, which facilitates setting certain
PHY settings post initialization of the PHY controller.
Exynos5420 and Exynos5800 have 28nm USB 3.0 DRD PHY for which
the Loss-of-Signal (LOS) Detector Threshold Level as well as
Tx-Vboost-Level should be controlled for Super-Speed operations.

Additionally set proper time to wait for RxDetect measurement,
for desired PHY reference clock, so as to solve issue with enumeration
of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive
on the controller.
We are using CR_port for this purpose to send required data
to override the LOS values.

On testing with USB 3.0 devices on USB 3.0 port present on
SMDK5420, and peach-pit boards should see following message:
usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd

and without this patch, should see below shown message:
usb 1-1: new high-speed USB device number 2 using xhci-hcd

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 drivers/phy/phy-exynos5-usbdrd.c |  169 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 169 insertions(+)

diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index 56285af..b214483 100644
--- a/drivers/phy/phy-exynos5-usbdrd.c
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -89,8 +89,20 @@
 #define PHYCLKRST_COMMONONN			BIT(0)
 
 #define EXYNOS5_DRD_PHYREG0			0x14
+
+#define EXYNOS5_DRD_PHYREG0_SSC_REF_CLK_SEL	BIT(21)
+#define EXYNOS5_DRD_PHYREG0_SSC_RANGE		BIT(20)
+#define EXYNOS5_DRD_PHYREG0_CR_WRITE		BIT(19)
+#define EXYNOS5_DRD_PHYREG0_CR_READ		BIT(18)
+#define EXYNOS5_DRD_PHYREG0_CR_DATA_IN(_x)	((_x) << 2)
+#define EXYNOS5_DRD_PHYREG0_CR_CAP_DATA		BIT(1)
+#define EXYNOS5_DRD_PHYREG0_CR_CAP_ADDR		BIT(0)
+
 #define EXYNOS5_DRD_PHYREG1			0x18
 
+#define EXYNOS5_DRD_PHYREG1_CR_DATA_OUT(_x)	((_x) << 1)
+#define EXYNOS5_DRD_PHYREG1_CR_ACK		BIT(0)
+
 #define EXYNOS5_DRD_PHYPARAM0			0x1c
 
 #define PHYPARAM0_REF_USE_PAD			BIT(31)
@@ -118,6 +130,26 @@
 #define EXYNOS5_DRD_PHYRESUME			0x34
 #define EXYNOS5_DRD_LINKPORT			0x44
 
+/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
+#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN		(0x15)
+
+#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420			(0x5 << 13)
+#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT		(0x0 << 13)
+#define LOSLEVEL_OVRD_IN_EN				(0x1 << 10)
+#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT		(0x9 << 0)
+
+#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN	(0x12)
+#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420		(0x5 << 13)
+#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT		(0x4 << 13)
+
+#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG		(0x1010)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M		(0x4 << 4)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M		(0x8 << 4)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M		(0x8 << 4)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M	(0x20 << 4)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5		(0x20 << 4)
+#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M		(0x40 << 4)
+
 #define KHZ	1000
 #define MHZ	(KHZ * KHZ)
 
@@ -135,12 +167,14 @@ struct exynos5_usbdrd_phy_config {
 	void (*phy_isol)(struct phy_usb_instance *inst, u32 on);
 	void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
 	unsigned int (*set_refclk)(struct phy_usb_instance *inst);
+	int (*phy_calibrate)(struct phy_usb_instance *inst);
 };
 
 struct exynos5_usbdrd_phy_drvdata {
 	const struct exynos5_usbdrd_phy_config *phy_cfg;
 	u32 pmu_offset_usbdrd0_phy;
 	u32 pmu_offset_usbdrd1_phy;
+	void (*calibrate)(struct exynos5_usbdrd_phy *phy_drd);
 };
 
 /**
@@ -487,6 +521,138 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
 	return 0;
 }
 
+static void crport_handshake(struct exynos5_usbdrd_phy *phy_drd,
+						u32 val, u32 cmd)
+{
+	u32 usec = 100;
+	u32 result;
+
+	writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
+
+	do {
+		result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
+		if (result & EXYNOS5_DRD_PHYREG1_CR_ACK)
+			break;
+
+		udelay(1);
+	} while (usec-- > 0);
+
+	if (!usec)
+		dev_err(phy_drd->dev,
+			"CRPORT handshake timeout1 (0x%08x)\n", val);
+
+	usec = 100;
+
+	writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
+
+	do {
+		result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);
+		if (!(result & EXYNOS5_DRD_PHYREG1_CR_ACK))
+			break;
+
+		udelay(1);
+	} while (usec-- > 0);
+
+	if (!usec)
+		dev_err(phy_drd->dev,
+			"CRPORT handshake timeout2 (0x%08x)\n", val);
+}
+
+static void crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd,
+						u32 addr, u32 data)
+{
+	/* Write Address */
+	crport_handshake(phy_drd, EXYNOS5_DRD_PHYREG0_CR_DATA_IN(addr),
+			 EXYNOS5_DRD_PHYREG0_CR_CAP_ADDR);
+
+	/* Write Data */
+	crport_handshake(phy_drd, EXYNOS5_DRD_PHYREG0_CR_DATA_IN(data),
+			 EXYNOS5_DRD_PHYREG0_CR_CAP_DATA);
+	crport_handshake(phy_drd, EXYNOS5_DRD_PHYREG0_CR_DATA_IN(data),
+			 EXYNOS5_DRD_PHYREG0_CR_WRITE);
+}
+
+/*
+ * Override PHY paramaeters using CR_PORT register to calibrate settings
+ * to meet meet SuperSpeed requirements, on Exynos5420 and Exynos5800 systems,
+ * which have 28nm USB 3.0 DRD PHY.
+ */
+static void exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd)
+{
+	u32 temp;
+
+	/*
+	 * Change los_bias to (0x5) for 28nm PHY from a
+	 * default value (0x0); los_level is set as default
+	 * (0x9) as also reflected in los_level[30:26] bits
+	 * of PHYPARAM0 register.
+	 */
+	temp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 |
+		LOSLEVEL_OVRD_IN_EN |
+		LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT;
+	crport_ctrl_write(phy_drd,
+			  EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN,
+			  temp);
+
+	/*
+	 * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning,
+	 * to raise Tx signal level from its default value of (0x4)
+	 */
+	temp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420;
+	crport_ctrl_write(phy_drd,
+			  EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN,
+			  temp);
+
+	/*
+	 * Set proper time to wait for RxDetect measurement, for
+	 * desired reference clock of PHY, by tuning the CRPORT
+	 * register LANE0.TX_DEBUG which is internal to PHY.
+	 * This fixes issue with few USB 3.0 devices, which are
+	 * not detected (not even generate interrupts on the bus
+	 * on insertion) without this change.
+	 * e.g. Samsung SUM-TSB16S 3.0 USB drive.
+	 */
+	switch (phy_drd->extrefclk) {
+	case EXYNOS5_FSEL_50MHZ:
+		temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M;
+		break;
+	case EXYNOS5_FSEL_20MHZ:
+	case EXYNOS5_FSEL_19MHZ2:
+		temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M;
+		break;
+	case EXYNOS5_FSEL_24MHZ:
+	default:
+		temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M;
+		break;
+	}
+
+	crport_ctrl_write(phy_drd,
+			  EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG,
+			  temp);
+}
+
+/* Calibrate PIPE3 PHY settings, if any */
+static int exynos5_usbdrd_pipe3_calibrate(struct phy_usb_instance *inst)
+{
+	struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+
+	/* Call respective phy_calibrate given by certain platform */
+	if (phy_drd->drv_data->phy_calibrate)
+		phy_drd->drv_data->phy_calibrate(phy_drd);
+
+	return 0;
+}
+
+static int exynos5_usbdrd_phy_calibrate(struct phy *phy)
+{
+	struct phy_usb_instance *inst = phy_get_drvdata(phy);
+
+	if (inst->phy_cfg->phy_calibrate)
+		inst->phy_cfg->phy_calibrate(inst);
+
+	return 0;
+}
+
 static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
 					struct of_phandle_args *args)
 {
@@ -503,6 +669,7 @@ static struct phy_ops exynos5_usbdrd_phy_ops = {
 	.exit		= exynos5_usbdrd_phy_exit,
 	.power_on	= exynos5_usbdrd_phy_power_on,
 	.power_off	= exynos5_usbdrd_phy_power_off,
+	.calibrate	= exynos5_usbdrd_phy_calibrate,
 	.owner		= THIS_MODULE,
 };
 
@@ -518,6 +685,7 @@ const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = {
 		.phy_isol	= exynos5_usbdrd_phy_isol,
 		.phy_init	= exynos5_usbdrd_pipe3_init,
 		.set_refclk	= exynos5_usbdrd_pipe3_set_refclk,
+		.phy_calibrate	= exynos5_usbdrd_pipe3_calibrate,
 	},
 };
 
@@ -525,6 +693,7 @@ const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
 	.phy_cfg		= phy_cfg_exynos5,
 	.pmu_offset_usbdrd0_phy	= EXYNOS5_USBDRD_PHY_CONTROL,
 	.pmu_offset_usbdrd1_phy	= EXYNOS5420_USBDRD1_PHY_CONTROL,
+	.calibrate		= exynos5420_usbdrd_phy_calibrate,
 };
 
 const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
-- 
1.7.10.4