From: Yong Wu <yong.wu@mediatek.com> To: Joerg Roedel <joro@8bytes.org>, Matthias Brugger <matthias.bgg@gmail.com>, Robin Murphy <robin.murphy@arm.com>, Will Deacon <will@kernel.org> Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat <drinkcat@chromium.org>, cui.zhang@mediatek.com, srv_heupstream@mediatek.com, chao.hao@mediatek.com, linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>, iommu@lists.linux-foundation.org, Rob Herring <robh+dt@kernel.org>, linux-mediatek@lists.infradead.org, yong.wu@mediatek.com, ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Matthias Kaehlcke <mka@chromium.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 16/21] iommu/mediatek: Add mmu1 support Date: Sat, 10 Aug 2019 15:58:16 +0800 Message-ID: <1565423901-17008-17-git-send-email-yong.wu@mediatek.com> (raw) In-Reply-To: <1565423901-17008-1-git-send-email-yong.wu@mediatek.com> Normally the M4U HW connect EMI with smi. the diagram is like below: EMI | M4U | smi-common | ----------------- | | | | ... larb0 larb1 larb2 larb3 Actually there are 2 mmu cells in the M4U HW, like this diagram: EMI --------- | | mmu0 mmu1 <- M4U | | --------- | smi-common | ----------------- | | | | ... larb0 larb1 larb2 larb3 This patch add support for mmu1. In order to get better performance, we could adjust some larbs go to mmu1 while the others still go to mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220). mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default value of that register is 0 which means all the larbs go to mmu0 defaultly. This is a preparing patch for adjusting SMI_BUS_SEL for mt8183. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> --- drivers/iommu/mtk_iommu.c | 46 +++++++++++++++++++++++++++++----------------- 1 file changed, 29 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 550b093..cbebe11 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -64,26 +64,32 @@ #define F_INT_CLR_BIT BIT(12) #define REG_MMU_INT_MAIN_CONTROL 0x124 -#define F_INT_TRANSLATION_FAULT BIT(0) -#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) -#define F_INT_INVALID_PA_FAULT BIT(2) -#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) -#define F_INT_TLB_MISS_FAULT BIT(4) -#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5) -#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6) + /* mmu0 | mmu1 */ +#define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) +#define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) +#define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) +#define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) +#define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) +#define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) +#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) #define REG_MMU_CPE_DONE 0x12C #define REG_MMU_FAULT_ST1 0x134 +#define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) +#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) -#define REG_MMU_FAULT_VA 0x13c +#define REG_MMU0_FAULT_VA 0x13c #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) -#define REG_MMU_INVLD_PA 0x140 -#define REG_MMU_INT_ID 0x150 -#define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) -#define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) +#define REG_MMU0_INVLD_PA 0x140 +#define REG_MMU1_FAULT_VA 0x144 +#define REG_MMU1_INVLD_PA 0x148 +#define REG_MMU0_INT_ID 0x150 +#define REG_MMU1_INT_ID 0x154 +#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) +#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) #define MTK_PROTECT_PA_ALIGN 128 @@ -202,13 +208,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) /* Read error info from registers */ int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); - fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); + if (int_state & F_REG_MMU0_FAULT_MASK) { + regval = readl_relaxed(data->base + REG_MMU0_INT_ID); + fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); + fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); + } else { + regval = readl_relaxed(data->base + REG_MMU1_INT_ID); + fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); + fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); + } layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; - fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); - regval = readl_relaxed(data->base + REG_MMU_INT_ID); - fault_larb = F_MMU0_INT_ID_LARB_ID(regval); - fault_port = F_MMU0_INT_ID_PORT_ID(regval); + fault_larb = F_MMU_INT_ID_LARB_ID(regval); + fault_port = F_MMU_INT_ID_PORT_ID(regval); fault_larb = data->plat_data->larbid_remap[fault_larb]; -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply index Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-10 7:58 [PATCH v9 00/21] MT8183 IOMMU SUPPORT Yong Wu 2019-08-10 7:58 ` [PATCH v9 01/21] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI Yong Wu 2019-08-10 7:58 ` [PATCH v9 02/21] iommu/mediatek: Use a struct as the platform data Yong Wu 2019-08-10 7:58 ` [PATCH v9 03/21] memory: mtk-smi: Use a general config_port interface Yong Wu 2019-08-10 7:58 ` [PATCH v9 04/21] memory: mtk-smi: Use a struct for the platform data for smi-common Yong Wu 2019-08-10 7:58 ` [PATCH v9 05/21] iommu/io-pgtable-arm-v7s: Add paddr_to_iopte and iopte_to_paddr helpers Yong Wu 2019-08-10 7:58 ` [PATCH v9 06/21] iommu/io-pgtable-arm-v7s: Use ias/oas to check the valid iova/pa Yong Wu 2019-08-10 7:58 ` [PATCH v9 07/21] iommu/io-pgtable-arm-v7s: Rename the quirk from MTK_4GB to MTK_EXT Yong Wu 2019-08-10 7:58 ` [PATCH v9 08/21] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB Mode Yong Wu 2019-08-14 14:41 ` Will Deacon 2019-08-15 8:47 ` Yong Wu 2019-08-15 9:51 ` Will Deacon 2019-08-15 10:03 ` Yong Wu 2019-08-15 10:04 ` Will Deacon 2019-08-15 10:18 ` Yong Wu 2019-08-15 11:50 ` Will Deacon 2019-08-16 7:22 ` Yong Wu 2019-08-19 11:24 ` Will Deacon 2019-08-10 7:58 ` [PATCH v9 09/21] iommu/mediatek: Add bclk can be supported optionally Yong Wu 2019-08-10 7:58 ` [PATCH v9 10/21] iommu/mediatek: Add larb-id remapped support Yong Wu 2019-08-10 7:58 ` [PATCH v9 11/21] iommu/mediatek: Refine protect memory definition Yong Wu 2019-08-10 7:58 ` [PATCH v9 12/21] iommu/mediatek: Move reset_axi into plat_data Yong Wu 2019-08-10 7:58 ` [PATCH v9 13/21] iommu/mediatek: Move vld_pa_rng " Yong Wu 2019-08-10 7:58 ` [PATCH v9 14/21] memory: mtk-smi: Add gals support Yong Wu 2019-08-10 7:58 ` [PATCH v9 15/21] iommu/mediatek: Add mt8183 IOMMU support Yong Wu 2019-08-10 7:58 ` Yong Wu [this message] 2019-08-10 7:58 ` [PATCH v9 17/21] memory: mtk-smi: Invoke pm runtime_callback to enable clocks Yong Wu 2019-08-10 7:58 ` [PATCH v9 18/21] memory: mtk-smi: Add bus_sel for mt8183 Yong Wu 2019-08-10 7:58 ` [PATCH v9 19/21] iommu/mediatek: Fix VLD_PA_RNG register backup when suspend Yong Wu 2019-08-10 7:58 ` [PATCH v9 20/21] memory: mtk-smi: Get rid of need_larbid Yong Wu 2019-08-10 7:58 ` [PATCH v9 21/21] iommu/mediatek: Clean up struct mtk_smi_iommu Yong Wu 2019-08-14 8:18 ` [PATCH v9 00/21] MT8183 IOMMU SUPPORT Joerg Roedel 2019-08-14 8:24 ` Will Deacon
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1565423901-17008-17-git-send-email-yong.wu@mediatek.com \ --to=yong.wu@mediatek.com \ --cc=anan.sun@mediatek.com \ --cc=chao.hao@mediatek.com \ --cc=cui.zhang@mediatek.com \ --cc=devicetree@vger.kernel.org \ --cc=drinkcat@chromium.org \ --cc=evgreen@chromium.org \ --cc=iommu@lists.linux-foundation.org \ --cc=joro@8bytes.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-mediatek@lists.infradead.org \ --cc=matthias.bgg@gmail.com \ --cc=ming-fan.chen@mediatek.com \ --cc=mka@chromium.org \ --cc=robh+dt@kernel.org \ --cc=robin.murphy@arm.com \ --cc=srv_heupstream@mediatek.com \ --cc=tfiga@google.com \ --cc=will@kernel.org \ --cc=youlin.pei@mediatek.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
Linux-ARM-Kernel Archive on lore.kernel.org Archives are clonable: git clone --mirror https://lore.kernel.org/linux-arm-kernel/0 linux-arm-kernel/git/0.git git clone --mirror https://lore.kernel.org/linux-arm-kernel/1 linux-arm-kernel/git/1.git # If you have public-inbox 1.1+ installed, you may # initialize and index your mirror using the following commands: public-inbox-init -V2 linux-arm-kernel linux-arm-kernel/ https://lore.kernel.org/linux-arm-kernel \ linux-arm-kernel@lists.infradead.org public-inbox-index linux-arm-kernel Example config snippet for mirrors Newsgroup available over NNTP: nntp://nntp.lore.kernel.org/org.infradead.lists.linux-arm-kernel AGPL code for this site: git clone https://public-inbox.org/public-inbox.git