Linux-ARM-Kernel Archive on lore.kernel.org
 help / color / Atom feed
From: Will Deacon <will@kernel.org>
To: Yong Wu <yong.wu@mediatek.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
	Nicolas Boichat <drinkcat@chromium.org>,
	cui.zhang@mediatek.com, srv_heupstream@mediatek.com,
	chao.hao@mediatek.com, Joerg Roedel <joro@8bytes.org>,
	linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>,
	Tomasz Figa <tfiga@google.com>,
	iommu@lists.linux-foundation.org,
	Rob Herring <robh+dt@kernel.org>,
	linux-mediatek@lists.infradead.org,
	Matthias Brugger <matthias.bgg@gmail.com>,
	ming-fan.chen@mediatek.com, anan.sun@mediatek.com,
	Robin Murphy <robin.murphy@arm.com>,
	Matthias Kaehlcke <mka@chromium.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v9 08/21] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB Mode
Date: Mon, 19 Aug 2019 12:24:38 +0100
Message-ID: <20190819112438.fr233h5dgjkqb36r@willie-the-truck> (raw)
In-Reply-To: <1565940140.20346.21.camel@mhfsdcap03>

On Fri, Aug 16, 2019 at 03:22:20PM +0800, Yong Wu wrote:
> On Thu, 2019-08-15 at 12:50 +0100, Will Deacon wrote:
> > Ok, I think speaking to Robin helped me a bit with this...
> > 
> > On Thu, Aug 15, 2019 at 06:18:38PM +0800, Yong Wu wrote:
> > > On Thu, 2019-08-15 at 10:51 +0100, Will Deacon wrote:
> > > > On Thu, Aug 15, 2019 at 04:47:49PM +0800, Yong Wu wrote:
> > > > > On Wed, 2019-08-14 at 15:41 +0100, Will Deacon wrote:
> > > > > > On Sat, Aug 10, 2019 at 03:58:08PM +0800, Yong Wu wrote:
> > > > > > > MediaTek extend the arm v7s descriptor to support the dram over 4GB.
> > > > > > > 
> > > > > > > In the mt2712 and mt8173, it's called "4GB mode", the physical address
> > > > > > > is from 0x4000_0000 to 0x1_3fff_ffff, but from EMI point of view, it
> > > > > > > is remapped to high address from 0x1_0000_0000 to 0x1_ffff_ffff, the
> > > > > > > bit32 is always enabled. thus, in the M4U, we always enable the bit9
> > > > > > > for all PTEs which means to enable bit32 of physical address. Here is
> > > > > > > the detailed remap relationship in the "4GB mode":
> > > > > > > CPU PA         ->    HW PA
> > > > > > > 0x4000_0000          0x1_4000_0000 (Add bit32)
> > > > > > > 0x8000_0000          0x1_8000_0000 ...
> > > > > > > 0xc000_0000          0x1_c000_0000 ...
> > > > > > > 0x1_0000_0000        0x1_0000_0000 (No change)
> > 
> > [...]
> > 
> > > > > > The way I would like this quirk to work is that the io-pgtable code
> > > > > > basically sets bit 9 in the pte when bit 32 is set in the physical address,
> > > > > > and sets bit 4 in the pte when bit 33 is set in the physical address. It
> > > > > > would then do the opposite when converting a pte to a physical address.
> > > > > > 
> > > > > > That way, your driver can call the page table code directly with the high
> > > > > > addresses and we don't have to do any manual offsetting or range checking
> > > > > > in the page table code.
> > > > > 
> > > > > In this case, the mt8183 can work successfully while the "4gb
> > > > > mode"(mt8173/mt2712) can not.
> > > > > 
> > > > > In the "4gb mode", As the remap relationship above, we should always add
> > > > > bit32 in pte as we did in [2]. and need add bit32 in the
> > > > > "iova_to_phys"(Not always add.). That means the "4gb mode" has a special
> > > > > flow:
> > > > > a. Always add bit32 in paddr_to_iopte.
> > > > > b. Add bit32 only when PA < 0x40000000 in iopte_to_paddr.
> > > > 
> > > > I think this is probably at the heart of my misunderstanding. What is so
> > > > special about PAs (is this HW PA or CPU PA?) below 0x40000000? Is this RAM
> > > > or something else?
> > > 
> > > SRAM and HW register that IOMMU can not access.
> > 
> > Ok, so redrawing your table from above, I think we can say something like:
> > 
> > 
> > CPU Physical address
> > ====================
> > 
> > 0G	1G	2G	3G	4G	5G
> > |---A---|---B---|---C---|---D---|---E---|
> > +--I/O--+------------Memory-------------+
> > 
> > 
> > IOMMU output physical address
> > =============================
> > 
> > 				4G	5G	6G	7G	8G
> > 				|---E---|---B---|---C---|---D---|
> > 				+------------Memory-------------+
> > 
> > 
> > Do you agree? 
> 
> Quite right.

Woohoo! So I finally got something right about this :) I'd be up for
including the diagrams above either in the commit message or in the IOMMU
driver code, along with a comment saying that region 'A' cannot be mapped
by the IOMMU and that the page-table walker uses CPU physical addresses.

> > If so, what happens to region 'A' (the I/O region) in the
> > IOMMU output physical address space. Is it accessible?
> 
> No. IOMMU can not access region 'A' above.

Got it. Thanks.

> > Anyway, I think it's the job of the driver to convert between the two
> > address spaces, so that:
> > 
> >   - On ->map(), bit 32 of the CPU physical address is set before calling
> >     into the iopgtable code
> > 
> >   - The result from ->iova_to_phys() should be the result from the
> >     iopgtable code, but with the top bit cleared for addresses over
> >     5G.
> > 
> > This assumes that:
> > 
> >   1. We're ok setting bit 9 in the ptes mapping region 'E'.
> >   2. The IOMMU page-table walker uses CPU physical addresses
> > 
> > Are those true?
> 
> Yes. Then this patch would be close to the one[1] I sent in v8.
> 
> Do I need to split this patch into 2 ones?:

Up to you. If you want to fix the current mainline behaviour of always
setting bit 4, then that should be a separate patch at the start of the
series which can be backported to stable. Is there a reason this doesn't go
wrong in practice?

> a).the pagetable code that support 34bit PA when MTK quirk is enabled.
> It only has the symmetric code handle BIT32/BIT33. Besides, I will add
> CONFIG_PHYS_ADDR_T_64BIT in the iopte_to_addr as commented before.

Hmm. I would prefer that the iopgtable code:

	* Range checks the paddr against the oas in ->map()
	* Refuses to accept an oas > 32 in ->alloc()

Then it's up to you whether you just want to pass an oas of 34 from the
IOMMU driver.

Will

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply index

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-10  7:58 [PATCH v9 00/21] MT8183 IOMMU SUPPORT Yong Wu
2019-08-10  7:58 ` [PATCH v9 01/21] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI Yong Wu
2019-08-10  7:58 ` [PATCH v9 02/21] iommu/mediatek: Use a struct as the platform data Yong Wu
2019-08-10  7:58 ` [PATCH v9 03/21] memory: mtk-smi: Use a general config_port interface Yong Wu
2019-08-10  7:58 ` [PATCH v9 04/21] memory: mtk-smi: Use a struct for the platform data for smi-common Yong Wu
2019-08-10  7:58 ` [PATCH v9 05/21] iommu/io-pgtable-arm-v7s: Add paddr_to_iopte and iopte_to_paddr helpers Yong Wu
2019-08-10  7:58 ` [PATCH v9 06/21] iommu/io-pgtable-arm-v7s: Use ias/oas to check the valid iova/pa Yong Wu
2019-08-10  7:58 ` [PATCH v9 07/21] iommu/io-pgtable-arm-v7s: Rename the quirk from MTK_4GB to MTK_EXT Yong Wu
2019-08-10  7:58 ` [PATCH v9 08/21] iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB Mode Yong Wu
2019-08-14 14:41   ` Will Deacon
2019-08-15  8:47     ` Yong Wu
2019-08-15  9:51       ` Will Deacon
2019-08-15 10:03         ` Yong Wu
2019-08-15 10:04           ` Will Deacon
2019-08-15 10:18         ` Yong Wu
2019-08-15 11:50           ` Will Deacon
2019-08-16  7:22             ` Yong Wu
2019-08-19 11:24               ` Will Deacon [this message]
2019-08-10  7:58 ` [PATCH v9 09/21] iommu/mediatek: Add bclk can be supported optionally Yong Wu
2019-08-10  7:58 ` [PATCH v9 10/21] iommu/mediatek: Add larb-id remapped support Yong Wu
2019-08-10  7:58 ` [PATCH v9 11/21] iommu/mediatek: Refine protect memory definition Yong Wu
2019-08-10  7:58 ` [PATCH v9 12/21] iommu/mediatek: Move reset_axi into plat_data Yong Wu
2019-08-10  7:58 ` [PATCH v9 13/21] iommu/mediatek: Move vld_pa_rng " Yong Wu
2019-08-10  7:58 ` [PATCH v9 14/21] memory: mtk-smi: Add gals support Yong Wu
2019-08-10  7:58 ` [PATCH v9 15/21] iommu/mediatek: Add mt8183 IOMMU support Yong Wu
2019-08-10  7:58 ` [PATCH v9 16/21] iommu/mediatek: Add mmu1 support Yong Wu
2019-08-10  7:58 ` [PATCH v9 17/21] memory: mtk-smi: Invoke pm runtime_callback to enable clocks Yong Wu
2019-08-10  7:58 ` [PATCH v9 18/21] memory: mtk-smi: Add bus_sel for mt8183 Yong Wu
2019-08-10  7:58 ` [PATCH v9 19/21] iommu/mediatek: Fix VLD_PA_RNG register backup when suspend Yong Wu
2019-08-10  7:58 ` [PATCH v9 20/21] memory: mtk-smi: Get rid of need_larbid Yong Wu
2019-08-10  7:58 ` [PATCH v9 21/21] iommu/mediatek: Clean up struct mtk_smi_iommu Yong Wu
2019-08-14  8:18 ` [PATCH v9 00/21] MT8183 IOMMU SUPPORT Joerg Roedel
2019-08-14  8:24   ` Will Deacon

Reply instructions:

You may reply publically to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190819112438.fr233h5dgjkqb36r@willie-the-truck \
    --to=will@kernel.org \
    --cc=anan.sun@mediatek.com \
    --cc=chao.hao@mediatek.com \
    --cc=cui.zhang@mediatek.com \
    --cc=devicetree@vger.kernel.org \
    --cc=drinkcat@chromium.org \
    --cc=evgreen@chromium.org \
    --cc=iommu@lists.linux-foundation.org \
    --cc=joro@8bytes.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mediatek@lists.infradead.org \
    --cc=matthias.bgg@gmail.com \
    --cc=ming-fan.chen@mediatek.com \
    --cc=mka@chromium.org \
    --cc=robh+dt@kernel.org \
    --cc=robin.murphy@arm.com \
    --cc=srv_heupstream@mediatek.com \
    --cc=tfiga@google.com \
    --cc=yong.wu@mediatek.com \
    --cc=youlin.pei@mediatek.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Linux-ARM-Kernel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-arm-kernel/0 linux-arm-kernel/git/0.git
	git clone --mirror https://lore.kernel.org/linux-arm-kernel/1 linux-arm-kernel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-arm-kernel linux-arm-kernel/ https://lore.kernel.org/linux-arm-kernel \
		linux-arm-kernel@lists.infradead.org infradead-linux-arm-kernel@archiver.kernel.org
	public-inbox-index linux-arm-kernel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.infradead.lists.linux-arm-kernel


AGPL code for this site: git clone https://public-inbox.org/ public-inbox