* [PATCH 2/5] arm64: dts: imx8mq: Move usdhc clocks assignment to board DT
2019-10-16 2:14 [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT Anson Huang
@ 2019-10-16 2:14 ` Anson Huang
2019-10-16 2:14 ` [PATCH 3/5] arm64: dts: imx8mm: " Anson Huang
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Anson Huang @ 2019-10-16 2:14 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
jun.li, ping.bai, daniel.baluta, leonard.crestez, daniel.lezcano,
l.stach, ccaione, abel.vesa, andrew.smirnov, jon, baruch, angus,
pavel, agx, troy.kisky, gary.bisson, dafna.hirschfeld,
richard.hu, andradanciu1997, manivannan.sadhasivam, aisheng.dong,
peng.fan, fugang.duan, devicetree, linux-arm-kernel,
linux-kernel
Cc: Linux-imx
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++
arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts | 2 ++
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 4 ++++
arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts | 2 ++
arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts | 4 ++++
arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi | 2 ++
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 4 ++++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 --
8 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 4e0a281..40fa390 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -278,6 +278,8 @@
};
&usdhc1 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -291,6 +293,8 @@
};
&usdhc2 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
index f52e872..b8cb20c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
@@ -110,6 +110,8 @@
};
&usdhc2 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
index 683a110..2a759df 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
@@ -780,6 +780,8 @@
};
&usdhc1 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -790,6 +792,8 @@
};
&usdhc2 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
index c832bf0..81d2692 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
@@ -191,6 +191,8 @@
};
&usdhc1 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
index 8a4aee2..59da96b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
@@ -207,6 +207,8 @@
};
&usdhc1 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -217,6 +219,8 @@
};
&usdhc2 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
index d7f03c6..3dc44114 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
@@ -170,6 +170,8 @@
};
&usdhc1 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
index 087b5b6..333c4e2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
@@ -486,6 +486,8 @@
};
&usdhc1 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -499,6 +501,8 @@
};
&usdhc2 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index a6d57fb..7f93194 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -868,8 +868,6 @@
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
- assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
bus-width = <4>;
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/5] arm64: dts: imx8mm: Move usdhc clocks assignment to board DT
2019-10-16 2:14 [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT Anson Huang
2019-10-16 2:14 ` [PATCH 2/5] arm64: dts: imx8mq: " Anson Huang
@ 2019-10-16 2:14 ` Anson Huang
2019-10-16 2:14 ` [PATCH 4/5] arm64: dts: imx8mn: " Anson Huang
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Anson Huang @ 2019-10-16 2:14 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
jun.li, ping.bai, daniel.baluta, leonard.crestez, daniel.lezcano,
l.stach, ccaione, abel.vesa, andrew.smirnov, jon, baruch, angus,
pavel, agx, troy.kisky, gary.bisson, dafna.hirschfeld,
richard.hu, andradanciu1997, manivannan.sadhasivam, aisheng.dong,
peng.fan, fugang.duan, devicetree, linux-arm-kernel,
linux-kernel
Cc: Linux-imx
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 4 ++++
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 4 ----
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index faefb71..ac91f6d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -293,6 +293,8 @@
};
&usdhc2 {
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
@@ -304,6 +306,8 @@
};
&usdhc3 {
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 8aafad2..9258150 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -698,8 +698,6 @@
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
- assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
@@ -728,8 +726,6 @@
<&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 4/5] arm64: dts: imx8mn: Move usdhc clocks assignment to board DT
2019-10-16 2:14 [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT Anson Huang
2019-10-16 2:14 ` [PATCH 2/5] arm64: dts: imx8mq: " Anson Huang
2019-10-16 2:14 ` [PATCH 3/5] arm64: dts: imx8mm: " Anson Huang
@ 2019-10-16 2:14 ` Anson Huang
2019-10-16 2:14 ` [PATCH 5/5] ARM: dts: imx7ulp: " Anson Huang
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Anson Huang @ 2019-10-16 2:14 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
jun.li, ping.bai, daniel.baluta, leonard.crestez, daniel.lezcano,
l.stach, ccaione, abel.vesa, andrew.smirnov, jon, baruch, angus,
pavel, agx, troy.kisky, gary.bisson, dafna.hirschfeld,
richard.hu, andradanciu1997, manivannan.sadhasivam, aisheng.dong,
peng.fan, fugang.duan, devicetree, linux-arm-kernel,
linux-kernel
Cc: Linux-imx
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 ++++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 4 ----
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 1b90faac..5c96203 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -186,6 +186,8 @@
};
&usdhc2 {
+ assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
@@ -197,6 +199,8 @@
};
&usdhc3 {
+ assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 73e3711..46c218e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -598,8 +598,6 @@
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
- assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
@@ -628,8 +626,6 @@
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 5/5] ARM: dts: imx7ulp: Move usdhc clocks assignment to board DT
2019-10-16 2:14 [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT Anson Huang
` (2 preceding siblings ...)
2019-10-16 2:14 ` [PATCH 4/5] arm64: dts: imx8mn: " Anson Huang
@ 2019-10-16 2:14 ` Anson Huang
2019-10-20 14:35 ` [PATCH 1/5] arm64: dts: imx8qxp: " Abel Vesa
2019-10-26 12:09 ` Shawn Guo
5 siblings, 0 replies; 9+ messages in thread
From: Anson Huang @ 2019-10-16 2:14 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
jun.li, ping.bai, daniel.baluta, leonard.crestez, daniel.lezcano,
l.stach, ccaione, abel.vesa, andrew.smirnov, jon, baruch, angus,
pavel, agx, troy.kisky, gary.bisson, dafna.hirschfeld,
richard.hu, andradanciu1997, manivannan.sadhasivam, aisheng.dong,
peng.fan, fugang.duan, devicetree, linux-arm-kernel,
linux-kernel
Cc: Linux-imx
usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm/boot/dts/imx7ulp-evk.dts | 2 ++
arch/arm/boot/dts/imx7ulp.dtsi | 4 ----
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
index 4245b33..f1093d2 100644
--- a/arch/arm/boot/dts/imx7ulp-evk.dts
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -77,6 +77,8 @@
};
&usdhc0 {
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 25e6f09..d37a192 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -223,8 +223,6 @@
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
@@ -239,8 +237,6 @@
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT
2019-10-16 2:14 [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT Anson Huang
` (3 preceding siblings ...)
2019-10-16 2:14 ` [PATCH 5/5] ARM: dts: imx7ulp: " Anson Huang
@ 2019-10-20 14:35 ` Abel Vesa
2019-10-26 12:09 ` Shawn Guo
5 siblings, 0 replies; 9+ messages in thread
From: Abel Vesa @ 2019-10-20 14:35 UTC (permalink / raw)
To: Anson Huang
Cc: mark.rutland, baruch, dafna.hirschfeld, Jacky Bai, ccaione, agx,
angus, Peng Fan, Gary Bisson, pavel, manivannan.sadhasivam,
Leonard Crestez, festevam, Richard Hu, andrew.smirnov,
daniel.lezcano, jon, dl-linux-imx, devicetree, andradanciu1997,
s.hauer, Troy Kisky, robh+dt, Daniel Baluta, linux-arm-kernel,
Aisheng Dong, Andy Duan, linux-kernel, kernel, Jun Li, shawnguo,
l.stach
On 19-10-16 10:14:23, Anson Huang wrote:
> usdhc's clock rate is different according to different devices
> connected, so clock rate assignment should be placed in board
> DT according to different devices connected on each usdhc port.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
For the entire patchset:
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ------
> 3 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> index 91eef97..a3f8cf1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> @@ -133,6 +133,8 @@
> &usdhc1 {
> #address-cells = <1>;
> #size-cells = <0>;
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> bus-width = <4>;
> @@ -149,6 +151,8 @@
>
> /* SD */
> &usdhc2 {
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc2>;
> bus-width = <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> index 88dd9132..d3d26cc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -137,6 +137,8 @@
> };
>
> &usdhc1 {
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> bus-width = <8>;
> @@ -147,6 +149,8 @@
> };
>
> &usdhc2 {
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc2>;
> bus-width = <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 2d69f1a..9646a41 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -368,8 +368,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_0>;
> status = "disabled";
> };
> @@ -383,8 +381,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_1>;
> fsl,tuning-start-tap = <20>;
> fsl,tuning-step= <2>;
> @@ -400,8 +396,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_2>;
> status = "disabled";
> };
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT
2019-10-16 2:14 [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT Anson Huang
` (4 preceding siblings ...)
2019-10-20 14:35 ` [PATCH 1/5] arm64: dts: imx8qxp: " Abel Vesa
@ 2019-10-26 12:09 ` Shawn Guo
2019-10-28 1:29 ` Anson Huang
5 siblings, 1 reply; 9+ messages in thread
From: Shawn Guo @ 2019-10-26 12:09 UTC (permalink / raw)
To: Anson Huang
Cc: mark.rutland, baruch, dafna.hirschfeld, ping.bai, ccaione, agx,
angus, peng.fan, gary.bisson, pavel, manivannan.sadhasivam,
leonard.crestez, festevam, richard.hu, abel.vesa, andrew.smirnov,
daniel.lezcano, jon, Linux-imx, devicetree, andradanciu1997,
s.hauer, troy.kisky, robh+dt, daniel.baluta, linux-arm-kernel,
aisheng.dong, fugang.duan, linux-kernel, kernel, jun.li, l.stach
On Wed, Oct 16, 2019 at 10:14:23AM +0800, Anson Huang wrote:
> usdhc's clock rate is different according to different devices
> connected, so clock rate assignment should be placed in board
> DT according to different devices connected on each usdhc port.
I think it should be fine that we have a reasonable default settings in
soc.dtsi, and boards that need a different setup can overwrite the
settings in board.dts.
Shawn
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ------
> 3 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> index 91eef97..a3f8cf1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> @@ -133,6 +133,8 @@
> &usdhc1 {
> #address-cells = <1>;
> #size-cells = <0>;
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> bus-width = <4>;
> @@ -149,6 +151,8 @@
>
> /* SD */
> &usdhc2 {
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc2>;
> bus-width = <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> index 88dd9132..d3d26cc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -137,6 +137,8 @@
> };
>
> &usdhc1 {
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> bus-width = <8>;
> @@ -147,6 +149,8 @@
> };
>
> &usdhc2 {
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc2>;
> bus-width = <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 2d69f1a..9646a41 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -368,8 +368,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_0>;
> status = "disabled";
> };
> @@ -383,8 +381,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_1>;
> fsl,tuning-start-tap = <20>;
> fsl,tuning-step= <2>;
> @@ -400,8 +396,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_2>;
> status = "disabled";
> };
> --
> 2.7.4
>
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^ permalink raw reply [flat|nested] 9+ messages in thread* RE: [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT
2019-10-26 12:09 ` Shawn Guo
@ 2019-10-28 1:29 ` Anson Huang
2019-10-28 3:15 ` Shawn Guo
0 siblings, 1 reply; 9+ messages in thread
From: Anson Huang @ 2019-10-28 1:29 UTC (permalink / raw)
To: Shawn Guo
Cc: mark.rutland, baruch, dafna.hirschfeld, Jacky Bai, ccaione, agx,
angus, Peng Fan, Gary Bisson, pavel, manivannan.sadhasivam,
Leonard Crestez, festevam, Richard Hu, Abel Vesa, andrew.smirnov,
daniel.lezcano, jon, dl-linux-imx, devicetree, andradanciu1997,
s.hauer, Troy Kisky, robh+dt, Daniel Baluta, linux-arm-kernel,
Aisheng Dong, Andy Duan, linux-kernel, kernel, Jun Li, l.stach
Hi, Shawn
> On Wed, Oct 16, 2019 at 10:14:23AM +0800, Anson Huang wrote:
> > usdhc's clock rate is different according to different devices
> > connected, so clock rate assignment should be placed in board DT
> > according to different devices connected on each usdhc port.
>
> I think it should be fine that we have a reasonable default settings in soc.dtsi,
> and boards that need a different setup can overwrite the settings in
> board.dts.
Someone was complaining about the usdhc clock assignment in soc.dtsi, because some
usdhc nodes are having clock assignments while some are NOT. That is why I did this
patch set. I agree that we can have default settings in soc.dtsi, so do you think it makes
sense to add default clock assignment to all usdhc nodes? If yes, I will redo the patch
set.
Thanks,
Anson.
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT
2019-10-28 1:29 ` Anson Huang
@ 2019-10-28 3:15 ` Shawn Guo
0 siblings, 0 replies; 9+ messages in thread
From: Shawn Guo @ 2019-10-28 3:15 UTC (permalink / raw)
To: Anson Huang
Cc: mark.rutland, baruch, dafna.hirschfeld, Jacky Bai, ccaione, agx,
angus, Peng Fan, Gary Bisson, pavel, manivannan.sadhasivam,
Leonard Crestez, festevam, Richard Hu, Abel Vesa, andrew.smirnov,
daniel.lezcano, jon, dl-linux-imx, devicetree, andradanciu1997,
s.hauer, Troy Kisky, robh+dt, Daniel Baluta, linux-arm-kernel,
Aisheng Dong, Andy Duan, linux-kernel, kernel, Jun Li, l.stach
On Mon, Oct 28, 2019 at 01:29:32AM +0000, Anson Huang wrote:
> Hi, Shawn
>
> > On Wed, Oct 16, 2019 at 10:14:23AM +0800, Anson Huang wrote:
> > > usdhc's clock rate is different according to different devices
> > > connected, so clock rate assignment should be placed in board DT
> > > according to different devices connected on each usdhc port.
> >
> > I think it should be fine that we have a reasonable default settings in soc.dtsi,
> > and boards that need a different setup can overwrite the settings in
> > board.dts.
>
> Someone was complaining about the usdhc clock assignment in soc.dtsi, because some
> usdhc nodes are having clock assignments while some are NOT. That is why I did this
> patch set. I agree that we can have default settings in soc.dtsi, so do you think it makes
> sense to add default clock assignment to all usdhc nodes? If yes, I will redo the patch
> set.
I had a second thought on this. To ease the maintenance of soc.dtsi,
let's do clock assignments in board.dts.
Series applied, thanks.
Shawn
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^ permalink raw reply [flat|nested] 9+ messages in thread