* [PATCH v4 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings
2020-01-09 2:30 [PATCH v4 0/6] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
@ 2020-01-09 2:30 ` Hanjie Lin
2020-01-09 9:21 ` Neil Armstrong
2020-01-09 17:12 ` Martin Blumenstingl
2020-01-09 2:30 ` [PATCH v4 2/6] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings Hanjie Lin
` (4 subsequent siblings)
5 siblings, 2 replies; 18+ messages in thread
From: Hanjie Lin @ 2020-01-09 2:30 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
Add the Amlogic A1 Family USB2 PHY Bindings
It supports Host mode only.
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
---
.../bindings/phy/amlogic,meson-a1-usb2-phy.yaml | 56 ++++++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml
new file mode 100644
index 00000000..dd2e3a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Amlogic, Inc
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/amlogic,meson-a1-usb2-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic A1 USB2 PHY
+
+maintainers:
+ - Yue Wang <yue.wang@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,meson-a1-usb2-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: xtal_usb_phy
+
+ resets:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - "#phy-cells"
+ - power-domains
+
+examples:
+ - |
+ usb2_phy1: phy@40000 {
+ status = "okay";
+ compatible = "amlogic,a1-usb2-phy";
+ clocks = <&clkc_periphs 2>;
+ clock-names = "xtal_usb_phy";
+ reg = <0x0 0x40000 0x0 0x2000>;
+ resets = <&reset RESET_USBPHY>;
+ #phy-cells = <0>;
+ power-domains = <&pwrc PWRC_USB_ID>;
+ };
--
2.7.4
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v4 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings
2020-01-09 2:30 ` [PATCH v4 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings Hanjie Lin
@ 2020-01-09 9:21 ` Neil Armstrong
2020-01-09 11:55 ` Hanjie Lin
2020-01-09 17:12 ` Martin Blumenstingl
1 sibling, 1 reply; 18+ messages in thread
From: Neil Armstrong @ 2020-01-09 9:21 UTC (permalink / raw)
To: Hanjie Lin, Jerome Brunet, Rob Herring, Greg Kroah-Hartman, Kevin Hilman
Cc: devicetree, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
On 09/01/2020 03:30, Hanjie Lin wrote:
> Add the Amlogic A1 Family USB2 PHY Bindings
>
> It supports Host mode only.
>
> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
> ---
> .../bindings/phy/amlogic,meson-a1-usb2-phy.yaml | 56 ++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml
> new file mode 100644
> index 00000000..dd2e3a6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2019 Amlogic, Inc
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/amlogic,meson-a1-usb2-phy.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic A1 USB2 PHY
> +
> +maintainers:
> + - Yue Wang <yue.wang@amlogic.com>
> +
> +properties:
> + compatible:
> + const: amlogic,meson-a1-usb2-phy
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: xtal_usb_phy
> +
> + resets:
> + maxItems: 1
Please use reset-names like the g12a bindings.
Neil
> +
> + "#phy-cells":
> + const: 0
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - "#phy-cells"
> + - power-domains
> +
> +examples:
> + - |
> + usb2_phy1: phy@40000 {
> + status = "okay";
> + compatible = "amlogic,a1-usb2-phy";
> + clocks = <&clkc_periphs 2>;
> + clock-names = "xtal_usb_phy";
> + reg = <0x0 0x40000 0x0 0x2000>;
> + resets = <&reset RESET_USBPHY>;
> + #phy-cells = <0>;
> + power-domains = <&pwrc PWRC_USB_ID>;
> + };
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings
2020-01-09 9:21 ` Neil Armstrong
@ 2020-01-09 11:55 ` Hanjie Lin
0 siblings, 0 replies; 18+ messages in thread
From: Hanjie Lin @ 2020-01-09 11:55 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
On 2020/1/9 17:21, Neil Armstrong wrote:
> On 09/01/2020 03:30, Hanjie Lin wrote:
>> Add the Amlogic A1 Family USB2 PHY Bindings
>>
>> It supports Host mode only.
>>
>> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
>> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
>> ---
>> .../bindings/phy/amlogic,meson-a1-usb2-phy.yaml | 56 ++++++++++++++++++++++
>> 1 file changed, 56 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml
>> new file mode 100644
>> index 00000000..dd2e3a6
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-a1-usb2-phy.yaml
>> @@ -0,0 +1,56 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +# Copyright 2019 Amlogic, Inc
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/phy/amlogic,meson-a1-usb2-phy.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: Amlogic A1 USB2 PHY
>> +
>> +maintainers:
>> + - Yue Wang <yue.wang@amlogic.com>
>> +
>> +properties:
>> + compatible:
>> + const: amlogic,meson-a1-usb2-phy
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + clock-names:
>> + items:
>> + - const: xtal_usb_phy
>> +
>> + resets:
>> + maxItems: 1
>
> Please use reset-names like the g12a bindings.
>
> Neil
>
Ok, Neil
I will revert reset-names change to keep consistence with G12A in next version.
Thanks,
Hanjie
>> +
>> + "#phy-cells":
>> + const: 0
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - resets
>> + - "#phy-cells"
>> + - power-domains
>> +
>> +examples:
>> + - |
>> + usb2_phy1: phy@40000 {
>> + status = "okay";
>> + compatible = "amlogic,a1-usb2-phy";
>> + clocks = <&clkc_periphs 2>;
>> + clock-names = "xtal_usb_phy";
>> + reg = <0x0 0x40000 0x0 0x2000>;
>> + resets = <&reset RESET_USBPHY>;
>> + #phy-cells = <0>;
>> + power-domains = <&pwrc PWRC_USB_ID>;
>> + };
>>
>
> .
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings
2020-01-09 2:30 ` [PATCH v4 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings Hanjie Lin
2020-01-09 9:21 ` Neil Armstrong
@ 2020-01-09 17:12 ` Martin Blumenstingl
2020-01-10 1:27 ` Hanjie Lin
1 sibling, 1 reply; 18+ messages in thread
From: Martin Blumenstingl @ 2020-01-09 17:12 UTC (permalink / raw)
To: Hanjie Lin
Cc: Rob Herring, Victor Wan, Jianxin Pan, Neil Armstrong,
Stephen Boyd, Kevin Hilman, Michael Turquette, linux-usb,
Yue Wang, Qiufang Dai, devicetree, Liang Yang, Jian Hu,
Xingyu Chen, Greg Kroah-Hartman, Carlo Caione, linux-amlogic,
linux-arm-kernel, Jerome Brunet
On Thu, Jan 9, 2020 at 3:30 AM Hanjie Lin <hanjie.lin@amlogic.com> wrote:
[...]
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: xtal_usb_phy
the "usb_phy" part of "xtal_usb_phy" seems redundant to me:
it's the XTAL clock input (this is what I'd expect as clock-name) of
the USB PHY (this is already part of the node name).
in addition to keeping the reset-names consistent (as Neil suggested)
please also use the same clock-names as G12
Thank you!
Martin
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings
2020-01-09 17:12 ` Martin Blumenstingl
@ 2020-01-10 1:27 ` Hanjie Lin
0 siblings, 0 replies; 18+ messages in thread
From: Hanjie Lin @ 2020-01-10 1:27 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: Rob Herring, Victor Wan, Jianxin Pan, Neil Armstrong,
Stephen Boyd, Kevin Hilman, Michael Turquette, linux-usb,
Yue Wang, Qiufang Dai, devicetree, Liang Yang, Jian Hu,
Xingyu Chen, Greg Kroah-Hartman, Carlo Caione, linux-amlogic,
linux-arm-kernel, Jerome Brunet
On 2020/1/10 1:12, Martin Blumenstingl wrote:
> On Thu, Jan 9, 2020 at 3:30 AM Hanjie Lin <hanjie.lin@amlogic.com> wrote:
> [...]
>> + clocks:
>> + maxItems: 1
>> +
>> + clock-names:
>> + items:
>> + - const: xtal_usb_phy
> the "usb_phy" part of "xtal_usb_phy" seems redundant to me:
> it's the XTAL clock input (this is what I'd expect as clock-name) of
> the USB PHY (this is already part of the node name).
> in addition to keeping the reset-names consistent (as Neil suggested)
> please also use the same clock-names as G12
>
Of course.
I will use "xtal" name in next version.
Thanks,
Hanjie
>
> Thank you!
> Martin
>
> .
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 2/6] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings
2020-01-09 2:30 [PATCH v4 0/6] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
2020-01-09 2:30 ` [PATCH v4 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings Hanjie Lin
@ 2020-01-09 2:30 ` Hanjie Lin
2020-01-09 2:30 ` [PATCH v4 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver Hanjie Lin
` (3 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Hanjie Lin @ 2020-01-09 2:30 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
The Amlogic A1 SoC Family embeds 1 USB Controllers:
- a DWC3 IP configured as Host for USB2 and USB3
A glue connects the controllers to the USB2 PHY of A1 SoC.
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
---
.../devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
index 4efb77b..f4595a3 100644
--- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
+++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
@@ -9,6 +9,8 @@ title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
+ - Hanjie Lin <hanjie.lin@amlogic.com>
+ - Yue Wang <yue.wang@amlogic.com>
description: |
The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
@@ -22,10 +24,14 @@ description: |
The DWC3 Glue controls the PHY routing and power, an interrupt line is
connected to the Glue to serve as OTG ID change detection.
+ The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
+ host-only mode.
+
properties:
compatible:
enum:
- amlogic,meson-g12a-usb-ctrl
+ - amlogic,meson-a1-usb-ctrl
ranges: true
@@ -37,6 +43,11 @@ properties:
clocks:
minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
resets:
minItems: 1
--
2.7.4
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v4 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver
2020-01-09 2:30 [PATCH v4 0/6] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
2020-01-09 2:30 ` [PATCH v4 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings Hanjie Lin
2020-01-09 2:30 ` [PATCH v4 2/6] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings Hanjie Lin
@ 2020-01-09 2:30 ` Hanjie Lin
2020-01-09 9:22 ` Neil Armstrong
2020-01-09 2:30 ` [PATCH v4 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue Hanjie Lin
` (2 subsequent siblings)
5 siblings, 1 reply; 18+ messages in thread
From: Hanjie Lin @ 2020-01-09 2:30 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
This adds support for the USB2 PHY found in the Amlogic A1 SoC Family.
It supports host mode only.
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
---
drivers/phy/amlogic/phy-meson-g12a-usb2.c | 99 +++++++++++++++++++++----------
1 file changed, 69 insertions(+), 30 deletions(-)
diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
index 9065ffc..16a1c0e 100644
--- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c
+++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
@@ -146,11 +146,17 @@
#define RESET_COMPLETE_TIME 1000
#define PLL_RESET_COMPLETE_TIME 100
+enum meson_soc_id {
+ MESON_SOC_G12A = 0,
+ MESON_SOC_A1,
+};
+
struct phy_meson_g12a_usb2_priv {
struct device *dev;
struct regmap *regmap;
struct clk *clk;
struct reset_control *reset;
+ int soc_id;
};
static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = {
@@ -164,6 +170,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
{
struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
int ret;
+ unsigned int value;
ret = reset_control_reset(priv->reset);
if (ret)
@@ -192,18 +199,22 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
- regmap_write(priv->regmap, PHY_CTRL_R18,
- FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
- PHY_CTRL_R18_MPLL_ACG_RANGE);
+ value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
+ PHY_CTRL_R18_MPLL_ACG_RANGE;
+
+ if (priv->soc_id == MESON_SOC_A1)
+ value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
+
+ regmap_write(priv->regmap, PHY_CTRL_R18, value);
udelay(PLL_RESET_COMPLETE_TIME);
@@ -227,13 +238,24 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
- regmap_write(priv->regmap, PHY_CTRL_R4,
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
- PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
- FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
- FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ if (priv->soc_id == MESON_SOC_G12A)
+ regmap_write(priv->regmap, PHY_CTRL_R4,
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
+ PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ else if (priv->soc_id == MESON_SOC_A1) {
+ regmap_write(priv->regmap, PHY_CTRL_R21,
+ PHY_CTRL_R21_USB2_CAL_ACK_EN |
+ PHY_CTRL_R21_USB2_TX_STRG_PD |
+ FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
+
+ /* Analog Settings */
+ regmap_write(priv->regmap, PHY_CTRL_R13,
+ FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ }
/* Tuning Disconnect Threshold */
regmap_write(priv->regmap, PHY_CTRL_R3,
@@ -241,11 +263,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) |
FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
- /* Analog Settings */
- regmap_write(priv->regmap, PHY_CTRL_R14, 0);
- regmap_write(priv->regmap, PHY_CTRL_R13,
- PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
- FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ if (priv->soc_id == MESON_SOC_G12A) {
+ /* Analog Settings */
+ regmap_write(priv->regmap, PHY_CTRL_R14, 0);
+ regmap_write(priv->regmap, PHY_CTRL_R13,
+ PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
+ FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ }
return 0;
}
@@ -286,16 +310,24 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
+ priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
+
priv->regmap = devm_regmap_init_mmio(dev, base,
&phy_meson_g12a_usb2_regmap_conf);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
- priv->clk = devm_clk_get(dev, "xtal");
- if (IS_ERR(priv->clk))
- return PTR_ERR(priv->clk);
+ if (priv->soc_id == MESON_SOC_G12A) {
+ priv->clk = devm_clk_get(dev, "xtal");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+ } else if (priv->soc_id == MESON_SOC_A1) {
+ priv->clk = devm_clk_get(dev, "xtal_usb_phy");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+ }
- priv->reset = devm_reset_control_get(dev, "phy");
+ priv->reset = devm_reset_control_get(dev, NULL);
if (IS_ERR(priv->reset))
return PTR_ERR(priv->reset);
@@ -321,8 +353,15 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
}
static const struct of_device_id phy_meson_g12a_usb2_of_match[] = {
- { .compatible = "amlogic,g12a-usb2-phy", },
- { },
+ {
+ .compatible = "amlogic,g12a-usb2-phy",
+ .data = (void *)MESON_SOC_G12A,
+ },
+ {
+ .compatible = "amlogic,a1-usb2-phy",
+ .data = (void *)MESON_SOC_A1,
+ },
+ { /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match);
--
2.7.4
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v4 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver
2020-01-09 2:30 ` [PATCH v4 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver Hanjie Lin
@ 2020-01-09 9:22 ` Neil Armstrong
2020-01-09 11:55 ` Hanjie Lin
0 siblings, 1 reply; 18+ messages in thread
From: Neil Armstrong @ 2020-01-09 9:22 UTC (permalink / raw)
To: Hanjie Lin, Jerome Brunet, Rob Herring, Greg Kroah-Hartman, Kevin Hilman
Cc: devicetree, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
On 09/01/2020 03:30, Hanjie Lin wrote:
> This adds support for the USB2 PHY found in the Amlogic A1 SoC Family.
>
> It supports host mode only.
>
> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
> ---
> drivers/phy/amlogic/phy-meson-g12a-usb2.c | 99 +++++++++++++++++++++----------
> 1 file changed, 69 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> index 9065ffc..16a1c0e 100644
> --- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> @@ -146,11 +146,17 @@
> #define RESET_COMPLETE_TIME 1000
> #define PLL_RESET_COMPLETE_TIME 100
>
> +enum meson_soc_id {
> + MESON_SOC_G12A = 0,
> + MESON_SOC_A1,
> +};
> +
> struct phy_meson_g12a_usb2_priv {
> struct device *dev;
> struct regmap *regmap;
> struct clk *clk;
> struct reset_control *reset;
> + int soc_id;
> };
>
> static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = {
> @@ -164,6 +170,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
> {
> struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
> int ret;
> + unsigned int value;
>
> ret = reset_control_reset(priv->reset);
> if (ret)
> @@ -192,18 +199,22 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
> FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
> FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
>
> - regmap_write(priv->regmap, PHY_CTRL_R18,
> - FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
> - PHY_CTRL_R18_MPLL_ACG_RANGE);
> + value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
> + PHY_CTRL_R18_MPLL_ACG_RANGE;
> +
> + if (priv->soc_id == MESON_SOC_A1)
> + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
> +
> + regmap_write(priv->regmap, PHY_CTRL_R18, value);
>
> udelay(PLL_RESET_COMPLETE_TIME);
>
> @@ -227,13 +238,24 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
> FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
> FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
>
> - regmap_write(priv->regmap, PHY_CTRL_R4,
> - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
> - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
> - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
> - PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
> - FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
> - FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
> + if (priv->soc_id == MESON_SOC_G12A)
> + regmap_write(priv->regmap, PHY_CTRL_R4,
> + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
> + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
> + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
> + PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
> + FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
> + FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
> + else if (priv->soc_id == MESON_SOC_A1) {
> + regmap_write(priv->regmap, PHY_CTRL_R21,
> + PHY_CTRL_R21_USB2_CAL_ACK_EN |
> + PHY_CTRL_R21_USB2_TX_STRG_PD |
> + FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
> +
> + /* Analog Settings */
> + regmap_write(priv->regmap, PHY_CTRL_R13,
> + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
> + }
>
> /* Tuning Disconnect Threshold */
> regmap_write(priv->regmap, PHY_CTRL_R3,
> @@ -241,11 +263,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
> FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) |
> FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
>
> - /* Analog Settings */
> - regmap_write(priv->regmap, PHY_CTRL_R14, 0);
> - regmap_write(priv->regmap, PHY_CTRL_R13,
> - PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
> - FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
> + if (priv->soc_id == MESON_SOC_G12A) {
> + /* Analog Settings */
> + regmap_write(priv->regmap, PHY_CTRL_R14, 0);
> + regmap_write(priv->regmap, PHY_CTRL_R13,
> + PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
> + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
> + }
>
> return 0;
> }
> @@ -286,16 +310,24 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
> if (IS_ERR(base))
> return PTR_ERR(base);
>
> + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
> +
> priv->regmap = devm_regmap_init_mmio(dev, base,
> &phy_meson_g12a_usb2_regmap_conf);
> if (IS_ERR(priv->regmap))
> return PTR_ERR(priv->regmap);
>
> - priv->clk = devm_clk_get(dev, "xtal");
> - if (IS_ERR(priv->clk))
> - return PTR_ERR(priv->clk);
> + if (priv->soc_id == MESON_SOC_G12A) {
> + priv->clk = devm_clk_get(dev, "xtal");
> + if (IS_ERR(priv->clk))
> + return PTR_ERR(priv->clk);
> + } else if (priv->soc_id == MESON_SOC_A1) {
> + priv->clk = devm_clk_get(dev, "xtal_usb_phy");
> + if (IS_ERR(priv->clk))
> + return PTR_ERR(priv->clk);
> + }
>
> - priv->reset = devm_reset_control_get(dev, "phy");
> + priv->reset = devm_reset_control_get(dev, NULL);
PLease keep the reset-names in the bindings and leave this as-is.
> if (IS_ERR(priv->reset))
> return PTR_ERR(priv->reset);
>
> @@ -321,8 +353,15 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
> }
>
> static const struct of_device_id phy_meson_g12a_usb2_of_match[] = {
> - { .compatible = "amlogic,g12a-usb2-phy", },
> - { },
> + {
> + .compatible = "amlogic,g12a-usb2-phy",
> + .data = (void *)MESON_SOC_G12A,
> + },
> + {
> + .compatible = "amlogic,a1-usb2-phy",
> + .data = (void *)MESON_SOC_A1,
> + },
> + { /* Sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match);
>
>
With the devm_reset_control_get change reverted:
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Neil
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver
2020-01-09 9:22 ` Neil Armstrong
@ 2020-01-09 11:55 ` Hanjie Lin
0 siblings, 0 replies; 18+ messages in thread
From: Hanjie Lin @ 2020-01-09 11:55 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
On 2020/1/9 17:22, Neil Armstrong wrote:
> On 09/01/2020 03:30, Hanjie Lin wrote:
>> This adds support for the USB2 PHY found in the Amlogic A1 SoC Family.
>>
>> It supports host mode only.
>>
>> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
>> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
>> ---
>> drivers/phy/amlogic/phy-meson-g12a-usb2.c | 99 +++++++++++++++++++++----------
>> 1 file changed, 69 insertions(+), 30 deletions(-)
>>
>> diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
>> index 9065ffc..16a1c0e 100644
>> --- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c
>> +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
>> @@ -146,11 +146,17 @@
>> #define RESET_COMPLETE_TIME 1000
>> #define PLL_RESET_COMPLETE_TIME 100
>>
>> +enum meson_soc_id {
>> + MESON_SOC_G12A = 0,
>> + MESON_SOC_A1,
>> +};
>> +
>> struct phy_meson_g12a_usb2_priv {
>> struct device *dev;
>> struct regmap *regmap;
>> struct clk *clk;
>> struct reset_control *reset;
>> + int soc_id;
>> };
>>
>> static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = {
>> @@ -164,6 +170,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
>> {
>> struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
>> int ret;
>> + unsigned int value;
>>
>> ret = reset_control_reset(priv->reset);
>> if (ret)
>> @@ -192,18 +199,22 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
>> FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
>> FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
>>
>> - regmap_write(priv->regmap, PHY_CTRL_R18,
>> - FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
>> - FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
>> - FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
>> - FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
>> - FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
>> - FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
>> - FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
>> - FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
>> - FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
>> - FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
>> - PHY_CTRL_R18_MPLL_ACG_RANGE);
>> + value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
>> + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
>> + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
>> + FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
>> + FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
>> + FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
>> + FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
>> + FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
>> + FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
>> + FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
>> + PHY_CTRL_R18_MPLL_ACG_RANGE;
>> +
>> + if (priv->soc_id == MESON_SOC_A1)
>> + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
>> +
>> + regmap_write(priv->regmap, PHY_CTRL_R18, value);
>>
>> udelay(PLL_RESET_COMPLETE_TIME);
>>
>> @@ -227,13 +238,24 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
>> FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
>> FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
>>
>> - regmap_write(priv->regmap, PHY_CTRL_R4,
>> - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
>> - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
>> - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
>> - PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
>> - FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
>> - FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
>> + if (priv->soc_id == MESON_SOC_G12A)
>> + regmap_write(priv->regmap, PHY_CTRL_R4,
>> + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
>> + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
>> + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
>> + PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
>> + FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
>> + FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
>> + else if (priv->soc_id == MESON_SOC_A1) {
>> + regmap_write(priv->regmap, PHY_CTRL_R21,
>> + PHY_CTRL_R21_USB2_CAL_ACK_EN |
>> + PHY_CTRL_R21_USB2_TX_STRG_PD |
>> + FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
>> +
>> + /* Analog Settings */
>> + regmap_write(priv->regmap, PHY_CTRL_R13,
>> + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
>> + }
>>
>> /* Tuning Disconnect Threshold */
>> regmap_write(priv->regmap, PHY_CTRL_R3,
>> @@ -241,11 +263,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
>> FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) |
>> FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
>>
>> - /* Analog Settings */
>> - regmap_write(priv->regmap, PHY_CTRL_R14, 0);
>> - regmap_write(priv->regmap, PHY_CTRL_R13,
>> - PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
>> - FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
>> + if (priv->soc_id == MESON_SOC_G12A) {
>> + /* Analog Settings */
>> + regmap_write(priv->regmap, PHY_CTRL_R14, 0);
>> + regmap_write(priv->regmap, PHY_CTRL_R13,
>> + PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
>> + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
>> + }
>>
>> return 0;
>> }
>> @@ -286,16 +310,24 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
>> if (IS_ERR(base))
>> return PTR_ERR(base);
>>
>> + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
>> +
>> priv->regmap = devm_regmap_init_mmio(dev, base,
>> &phy_meson_g12a_usb2_regmap_conf);
>> if (IS_ERR(priv->regmap))
>> return PTR_ERR(priv->regmap);
>>
>> - priv->clk = devm_clk_get(dev, "xtal");
>> - if (IS_ERR(priv->clk))
>> - return PTR_ERR(priv->clk);
>> + if (priv->soc_id == MESON_SOC_G12A) {
>> + priv->clk = devm_clk_get(dev, "xtal");
>> + if (IS_ERR(priv->clk))
>> + return PTR_ERR(priv->clk);
>> + } else if (priv->soc_id == MESON_SOC_A1) {
>> + priv->clk = devm_clk_get(dev, "xtal_usb_phy");
>> + if (IS_ERR(priv->clk))
>> + return PTR_ERR(priv->clk);
>> + }
>>
>> - priv->reset = devm_reset_control_get(dev, "phy");
>> + priv->reset = devm_reset_control_get(dev, NULL);
>
>
> PLease keep the reset-names in the bindings and leave this as-is.
>
Ok, Neil
I will revert reset-names change to keep consistence with G12A.
Thanks,
Hanjie
>> if (IS_ERR(priv->reset))
>> return PTR_ERR(priv->reset);
>>
>> @@ -321,8 +353,15 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
>> }
>>
>> static const struct of_device_id phy_meson_g12a_usb2_of_match[] = {
>> - { .compatible = "amlogic,g12a-usb2-phy", },
>> - { },
>> + {
>> + .compatible = "amlogic,g12a-usb2-phy",
>> + .data = (void *)MESON_SOC_G12A,
>> + },
>> + {
>> + .compatible = "amlogic,a1-usb2-phy",
>> + .data = (void *)MESON_SOC_A1,
>> + },
>> + { /* Sentinel */ }
>> };
>> MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match);
>>
>>
>
> With the devm_reset_control_get change reverted:
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
>
> Neil
>
> .
>
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* [PATCH v4 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue
2020-01-09 2:30 [PATCH v4 0/6] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
` (2 preceding siblings ...)
2020-01-09 2:30 ` [PATCH v4 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver Hanjie Lin
@ 2020-01-09 2:30 ` Hanjie Lin
2020-01-09 9:13 ` Neil Armstrong
2020-01-15 8:44 ` Felipe Balbi
2020-01-09 2:30 ` [PATCH v4 5/6] arm64: dts: meson: a1: Enable USB2 PHY Hanjie Lin
2020-01-09 2:30 ` [PATCH v4 6/6] arm64: dts: meson: a1: Enable DWC3 controller Hanjie Lin
5 siblings, 2 replies; 18+ messages in thread
From: Hanjie Lin @ 2020-01-09 2:30 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
Adds support for Amlogic A1 USB Control Glue HW.
The Amlogic A1 SoC Family embeds 1 USB Controllers:
- a DWC3 IP configured as Host for USB2 and USB3
A glue connects the controllers to the USB2 PHY of A1 SoC.
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
---
drivers/usb/dwc3/dwc3-meson-g12a.c | 99 +++++++++++++++++++++++++++-----------
1 file changed, 71 insertions(+), 28 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index 8a3ec1a..957eda2 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -96,6 +96,11 @@
#define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
#define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
+enum meson_soc_id {
+ MESON_SOC_G12A = 0,
+ MESON_SOC_A1,
+};
+
enum {
USB2_HOST_PHY = 0,
USB2_OTG_PHY,
@@ -107,10 +112,21 @@ static const char *phy_names[PHY_COUNT] = {
"usb2-phy0", "usb2-phy1", "usb3-phy0",
};
+static const struct clk_bulk_data meson_g12a_clocks[] = {
+ { .id = NULL },
+};
+
+static const struct clk_bulk_data meson_a1_clocks[] = {
+ { .id = "usb_ctrl" },
+ { .id = "usb_bus" },
+ { .id = "xtal_usb_ctrl" },
+};
+
struct dwc3_meson_g12a {
struct device *dev;
struct regmap *regmap;
- struct clk *clk;
+ struct clk_bulk_data *clks;
+ int num_clks;
struct reset_control *reset;
struct phy *phys[PHY_COUNT];
enum usb_dr_mode otg_mode;
@@ -120,6 +136,7 @@ struct dwc3_meson_g12a {
struct regulator *vbus;
struct usb_role_switch_desc switch_desc;
struct usb_role_switch *role_switch;
+ int soc_id;
};
static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
@@ -151,7 +168,7 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
U2P_R0_POWER_ON_RESET,
U2P_R0_POWER_ON_RESET);
- if (i == USB2_OTG_PHY) {
+ if (priv->otg_mode == USB_DR_MODE_OTG && i == USB2_OTG_PHY) {
regmap_update_bits(priv->regmap,
U2P_R0 + (U2P_REG_SIZE * i),
U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
@@ -295,7 +312,7 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv,
{
int ret;
- if (!priv->phys[USB2_OTG_PHY])
+ if (priv->otg_mode != USB_DR_MODE_OTG || !priv->phys[USB2_OTG_PHY])
return -EINVAL;
if (mode == PHY_MODE_USB_HOST)
@@ -409,17 +426,32 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
priv->vbus = NULL;
}
- priv->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(priv->clk))
- return PTR_ERR(priv->clk);
+ priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
+
+ if (priv->soc_id == MESON_SOC_G12A) {
+ priv->clks = devm_kmemdup(dev, meson_g12a_clocks,
+ sizeof(meson_g12a_clocks),
+ GFP_KERNEL);
+ priv->num_clks = ARRAY_SIZE(meson_g12a_clocks);
+ } else if (priv->soc_id == MESON_SOC_A1) {
+ priv->clks = devm_kmemdup(dev, meson_a1_clocks,
+ sizeof(meson_a1_clocks),
+ GFP_KERNEL);
+ priv->num_clks = ARRAY_SIZE(meson_a1_clocks);
+ } else {
+ return -EINVAL;
+ }
+
+ if (!priv->clks)
+ return -ENOMEM;
- ret = clk_prepare_enable(priv->clk);
+ ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
if (ret)
return ret;
- devm_add_action_or_reset(dev,
- (void(*)(void *))clk_disable_unprepare,
- priv->clk);
+ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
+ if (ret)
+ return ret;
platform_set_drvdata(pdev, priv);
priv->dev = dev;
@@ -433,16 +465,16 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
ret = reset_control_reset(priv->reset);
if (ret)
- return ret;
+ goto err_disable_clks;
ret = dwc3_meson_g12a_get_phys(priv);
if (ret)
- return ret;
+ goto err_disable_clks;
if (priv->vbus) {
ret = regulator_enable(priv->vbus);
if (ret)
- return ret;
+ goto err_disable_clks;
}
/* Get dr_mode */
@@ -458,7 +490,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
dwc3_meson_g12a_irq_thread,
IRQF_ONESHOT, pdev->name, priv);
if (ret)
- return ret;
+ goto err_disable_clks;
}
dwc3_meson_g12a_usb_init(priv);
@@ -467,7 +499,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
for (i = 0 ; i < PHY_COUNT ; ++i) {
ret = phy_init(priv->phys[i]);
if (ret)
- return ret;
+ goto err_disable_clks;
}
/* Set PHY Power */
@@ -478,18 +510,17 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
}
ret = of_platform_populate(np, NULL, NULL, dev);
- if (ret) {
- clk_disable_unprepare(priv->clk);
+ if (ret)
goto err_phys_power;
- }
+
+ if (priv->otg_mode != USB_DR_MODE_OTG)
+ goto setup_pm_runtime;
/* Setup OTG mode corresponding to the ID pin */
- if (priv->otg_mode == USB_DR_MODE_OTG) {
- otg_id = dwc3_meson_g12a_get_id(priv);
- if (otg_id != priv->otg_phy_mode) {
- if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
- dev_warn(dev, "Failed to switch OTG mode\n");
- }
+ otg_id = dwc3_meson_g12a_get_id(priv);
+ if (otg_id != priv->otg_phy_mode) {
+ if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
+ dev_warn(dev, "Failed to switch OTG mode\n");
}
/* Setup role switcher */
@@ -504,6 +535,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
if (IS_ERR(priv->role_switch))
dev_warn(dev, "Unable to register Role Switch\n");
+setup_pm_runtime:
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
@@ -518,6 +550,9 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
for (i = 0 ; i < PHY_COUNT ; ++i)
phy_exit(priv->phys[i]);
+err_disable_clks:
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+
return ret;
}
@@ -527,7 +562,8 @@ static int dwc3_meson_g12a_remove(struct platform_device *pdev)
struct device *dev = &pdev->dev;
int i;
- usb_role_switch_unregister(priv->role_switch);
+ if (priv->otg_mode == USB_DR_MODE_OTG)
+ usb_role_switch_unregister(priv->role_switch);
of_platform_depopulate(dev);
@@ -547,7 +583,7 @@ static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev)
{
struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
- clk_disable(priv->clk);
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
return 0;
}
@@ -556,7 +592,7 @@ static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev)
{
struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
- return clk_enable(priv->clk);
+ return clk_bulk_prepare_enable(priv->num_clks, priv->clks);
}
static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev)
@@ -619,7 +655,14 @@ static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = {
};
static const struct of_device_id dwc3_meson_g12a_match[] = {
- { .compatible = "amlogic,meson-g12a-usb-ctrl" },
+ {
+ .compatible = "amlogic,meson-g12a-usb-ctrl",
+ .data = (void *)MESON_SOC_G12A,
+ },
+ {
+ .compatible = "amlogic,meson-a1-usb-ctrl",
+ .data = (void *)MESON_SOC_A1,
+ },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match);
--
2.7.4
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v4 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue
2020-01-09 2:30 ` [PATCH v4 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue Hanjie Lin
@ 2020-01-09 9:13 ` Neil Armstrong
2020-01-09 11:51 ` Hanjie Lin
2020-01-15 8:44 ` Felipe Balbi
1 sibling, 1 reply; 18+ messages in thread
From: Neil Armstrong @ 2020-01-09 9:13 UTC (permalink / raw)
To: Hanjie Lin, Jerome Brunet, Rob Herring, Greg Kroah-Hartman, Kevin Hilman
Cc: devicetree, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
Hi,
On 09/01/2020 03:30, Hanjie Lin wrote:
> Adds support for Amlogic A1 USB Control Glue HW.
>
> The Amlogic A1 SoC Family embeds 1 USB Controllers:
> - a DWC3 IP configured as Host for USB2 and USB3
>
> A glue connects the controllers to the USB2 PHY of A1 SoC.
>
> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
> ---
> drivers/usb/dwc3/dwc3-meson-g12a.c | 99 +++++++++++++++++++++++++++-----------
> 1 file changed, 71 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
> index 8a3ec1a..957eda2 100644
> --- a/drivers/usb/dwc3/dwc3-meson-g12a.c
> +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
> @@ -96,6 +96,11 @@
> #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
> #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
>
> +enum meson_soc_id {
> + MESON_SOC_G12A = 0,
> + MESON_SOC_A1,
> +};
> +
> enum {
> USB2_HOST_PHY = 0,
> USB2_OTG_PHY,
> @@ -107,10 +112,21 @@ static const char *phy_names[PHY_COUNT] = {
> "usb2-phy0", "usb2-phy1", "usb3-phy0",
> };
>
> +static const struct clk_bulk_data meson_g12a_clocks[] = {
> + { .id = NULL },
> +};
> +
> +static const struct clk_bulk_data meson_a1_clocks[] = {
> + { .id = "usb_ctrl" },
> + { .id = "usb_bus" },
> + { .id = "xtal_usb_ctrl" },
> +};
> +
> struct dwc3_meson_g12a {
> struct device *dev;
> struct regmap *regmap;
> - struct clk *clk;
> + struct clk_bulk_data *clks;
> + int num_clks;
> struct reset_control *reset;
> struct phy *phys[PHY_COUNT];
> enum usb_dr_mode otg_mode;
> @@ -120,6 +136,7 @@ struct dwc3_meson_g12a {
> struct regulator *vbus;
> struct usb_role_switch_desc switch_desc;
> struct usb_role_switch *role_switch;
> + int soc_id;
> };
>
> static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
> @@ -151,7 +168,7 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
> U2P_R0_POWER_ON_RESET,
> U2P_R0_POWER_ON_RESET);
>
> - if (i == USB2_OTG_PHY) {
> + if (priv->otg_mode == USB_DR_MODE_OTG && i == USB2_OTG_PHY) {
I as said on v2, this is wrong, we can/need/must allow switching even if the dr_mode is not USB_DR_MODE_OTG.
Please add a struct used in match data with a simple bool like "otg_switch_support" and use it here and below
instead of using USB_DR_MODE_OTG.
> regmap_update_bits(priv->regmap,
> U2P_R0 + (U2P_REG_SIZE * i),
> U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
> @@ -295,7 +312,7 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv,
> {
> int ret;
>
> - if (!priv->phys[USB2_OTG_PHY])
> + if (priv->otg_mode != USB_DR_MODE_OTG || !priv->phys[USB2_OTG_PHY])
Ditto
> return -EINVAL;
>
> if (mode == PHY_MODE_USB_HOST)
> @@ -409,17 +426,32 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
> priv->vbus = NULL;
> }
>
> - priv->clk = devm_clk_get(dev, NULL);
> - if (IS_ERR(priv->clk))
> - return PTR_ERR(priv->clk);
> + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
> +
> + if (priv->soc_id == MESON_SOC_G12A) {
> + priv->clks = devm_kmemdup(dev, meson_g12a_clocks,
> + sizeof(meson_g12a_clocks),
> + GFP_KERNEL);
> + priv->num_clks = ARRAY_SIZE(meson_g12a_clocks);
> + } else if (priv->soc_id == MESON_SOC_A1) {
> + priv->clks = devm_kmemdup(dev, meson_a1_clocks,
> + sizeof(meson_a1_clocks),
> + GFP_KERNEL);
> + priv->num_clks = ARRAY_SIZE(meson_a1_clocks);
> + } else {
> + return -EINVAL;
> + }
> +
> + if (!priv->clks)
> + return -ENOMEM;
>
> - ret = clk_prepare_enable(priv->clk);
> + ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
> if (ret)
> return ret;
>
> - devm_add_action_or_reset(dev,
> - (void(*)(void *))clk_disable_unprepare,
> - priv->clk);
> + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
> + if (ret)
> + return ret;
>
> platform_set_drvdata(pdev, priv);
> priv->dev = dev;
> @@ -433,16 +465,16 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
>
> ret = reset_control_reset(priv->reset);
> if (ret)
> - return ret;
> + goto err_disable_clks;
>
> ret = dwc3_meson_g12a_get_phys(priv);
> if (ret)
> - return ret;
> + goto err_disable_clks;
>
> if (priv->vbus) {
> ret = regulator_enable(priv->vbus);
> if (ret)
> - return ret;
> + goto err_disable_clks;
> }
>
> /* Get dr_mode */
> @@ -458,7 +490,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
> dwc3_meson_g12a_irq_thread,
> IRQF_ONESHOT, pdev->name, priv);
> if (ret)
> - return ret;
> + goto err_disable_clks;
> }
>
> dwc3_meson_g12a_usb_init(priv);
> @@ -467,7 +499,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
> for (i = 0 ; i < PHY_COUNT ; ++i) {
> ret = phy_init(priv->phys[i]);
> if (ret)
> - return ret;
> + goto err_disable_clks;
> }
>
> /* Set PHY Power */
> @@ -478,18 +510,17 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
> }
>
> ret = of_platform_populate(np, NULL, NULL, dev);
> - if (ret) {
> - clk_disable_unprepare(priv->clk);
> + if (ret)
> goto err_phys_power;
> - }
> +
> + if (priv->otg_mode != USB_DR_MODE_OTG)
> + goto setup_pm_runtime;
>
> /* Setup OTG mode corresponding to the ID pin */
> - if (priv->otg_mode == USB_DR_MODE_OTG) {
> - otg_id = dwc3_meson_g12a_get_id(priv);
> - if (otg_id != priv->otg_phy_mode) {
> - if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
> - dev_warn(dev, "Failed to switch OTG mode\n");
> - }
> + otg_id = dwc3_meson_g12a_get_id(priv);
> + if (otg_id != priv->otg_phy_mode) {
> + if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
> + dev_warn(dev, "Failed to switch OTG mode\n");
> }
>
> /* Setup role switcher */
> @@ -504,6 +535,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
> if (IS_ERR(priv->role_switch))
> dev_warn(dev, "Unable to register Role Switch\n");
>
> +setup_pm_runtime:
Ditto
> pm_runtime_set_active(dev);
> pm_runtime_enable(dev);
> pm_runtime_get_sync(dev);
> @@ -518,6 +550,9 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
> for (i = 0 ; i < PHY_COUNT ; ++i)
> phy_exit(priv->phys[i]);
>
> +err_disable_clks:
> + clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
> +
> return ret;
> }
>
> @@ -527,7 +562,8 @@ static int dwc3_meson_g12a_remove(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> int i;
>
> - usb_role_switch_unregister(priv->role_switch);
> + if (priv->otg_mode == USB_DR_MODE_OTG)
> + usb_role_switch_unregister(priv->role_switch);
>
> of_platform_depopulate(dev);
>
> @@ -547,7 +583,7 @@ static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev)
> {
> struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
>
> - clk_disable(priv->clk);
> + clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
>
> return 0;
> }
> @@ -556,7 +592,7 @@ static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev)
> {
> struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
>
> - return clk_enable(priv->clk);
> + return clk_bulk_prepare_enable(priv->num_clks, priv->clks);
> }
>
> static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev)
> @@ -619,7 +655,14 @@ static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = {
> };
>
> static const struct of_device_id dwc3_meson_g12a_match[] = {
> - { .compatible = "amlogic,meson-g12a-usb-ctrl" },
> + {
> + .compatible = "amlogic,meson-g12a-usb-ctrl",
> + .data = (void *)MESON_SOC_G12A,
> + },
> + {
> + .compatible = "amlogic,meson-a1-usb-ctrl",
> + .data = (void *)MESON_SOC_A1,
> + },
> { /* Sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match);
>
Neil
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue
2020-01-09 9:13 ` Neil Armstrong
@ 2020-01-09 11:51 ` Hanjie Lin
0 siblings, 0 replies; 18+ messages in thread
From: Hanjie Lin @ 2020-01-09 11:51 UTC (permalink / raw)
To: Neil Armstrong, Jerome Brunet, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Jian Hu, linux-arm-kernel, Qiufang Dai,
linux-amlogic, Carlo Caione, Xingyu Chen
On 2020/1/9 17:13, Neil Armstrong wrote:
> Hi,
>
> On 09/01/2020 03:30, Hanjie Lin wrote:
>> Adds support for Amlogic A1 USB Control Glue HW.
>>
>> The Amlogic A1 SoC Family embeds 1 USB Controllers:
>> - a DWC3 IP configured as Host for USB2 and USB3
>>
>> A glue connects the controllers to the USB2 PHY of A1 SoC.
>>
>> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
>> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
>> ---
>> drivers/usb/dwc3/dwc3-meson-g12a.c | 99 +++++++++++++++++++++++++++-----------
>> 1 file changed, 71 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
>> index 8a3ec1a..957eda2 100644
>> --- a/drivers/usb/dwc3/dwc3-meson-g12a.c
>> +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
>> @@ -96,6 +96,11 @@
>> #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
>> #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
>>
>> +enum meson_soc_id {
>> + MESON_SOC_G12A = 0,
>> + MESON_SOC_A1,
>> +};
>> +
>> enum {
>> USB2_HOST_PHY = 0,
>> USB2_OTG_PHY,
>> @@ -107,10 +112,21 @@ static const char *phy_names[PHY_COUNT] = {
>> "usb2-phy0", "usb2-phy1", "usb3-phy0",
>> };
>>
>> +static const struct clk_bulk_data meson_g12a_clocks[] = {
>> + { .id = NULL },
>> +};
>> +
>> +static const struct clk_bulk_data meson_a1_clocks[] = {
>> + { .id = "usb_ctrl" },
>> + { .id = "usb_bus" },
>> + { .id = "xtal_usb_ctrl" },
>> +};
>> +
>> struct dwc3_meson_g12a {
>> struct device *dev;
>> struct regmap *regmap;
>> - struct clk *clk;
>> + struct clk_bulk_data *clks;
>> + int num_clks;
>> struct reset_control *reset;
>> struct phy *phys[PHY_COUNT];
>> enum usb_dr_mode otg_mode;
>> @@ -120,6 +136,7 @@ struct dwc3_meson_g12a {
>> struct regulator *vbus;
>> struct usb_role_switch_desc switch_desc;
>> struct usb_role_switch *role_switch;
>> + int soc_id;
>> };
>>
>> static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
>> @@ -151,7 +168,7 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
>> U2P_R0_POWER_ON_RESET,
>> U2P_R0_POWER_ON_RESET);
>>
>> - if (i == USB2_OTG_PHY) {
>> + if (priv->otg_mode == USB_DR_MODE_OTG && i == USB2_OTG_PHY) {
>
> I as said on v2, this is wrong, we can/need/must allow switching even if the dr_mode is not USB_DR_MODE_OTG.
>
> Please add a struct used in match data with a simple bool like "otg_switch_support" and use it here and below
> instead of using USB_DR_MODE_OTG.
>
Hi neil,
Right, I thought only otg dr_mode(from dts) can allow switching by mistake.
I will add a drvdata struct includes both otg_switch_supported and clock info for each SoC comaptible in next version.
Thanks,
Hanjie
>> regmap_update_bits(priv->regmap,
>> U2P_R0 + (U2P_REG_SIZE * i),
>> U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
>> @@ -295,7 +312,7 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv,
>> {
>> int ret;
>>
>> - if (!priv->phys[USB2_OTG_PHY])
>> + if (priv->otg_mode != USB_DR_MODE_OTG || !priv->phys[USB2_OTG_PHY])
>
> Ditto
>
>> return -EINVAL;
>>
>> if (mode == PHY_MODE_USB_HOST)
>> @@ -409,17 +426,32 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
>> priv->vbus = NULL;
>> }
>>
>> - priv->clk = devm_clk_get(dev, NULL);
>> - if (IS_ERR(priv->clk))
>> - return PTR_ERR(priv->clk);
>> + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
>> +
>> + if (priv->soc_id == MESON_SOC_G12A) {
>> + priv->clks = devm_kmemdup(dev, meson_g12a_clocks,
>> + sizeof(meson_g12a_clocks),
>> + GFP_KERNEL);
>> + priv->num_clks = ARRAY_SIZE(meson_g12a_clocks);
>> + } else if (priv->soc_id == MESON_SOC_A1) {
>> + priv->clks = devm_kmemdup(dev, meson_a1_clocks,
>> + sizeof(meson_a1_clocks),
>> + GFP_KERNEL);
>> + priv->num_clks = ARRAY_SIZE(meson_a1_clocks);
>> + } else {
>> + return -EINVAL;
>> + }
>> +
>> + if (!priv->clks)
>> + return -ENOMEM;
>>
>> - ret = clk_prepare_enable(priv->clk);
>> + ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
>> if (ret)
>> return ret;
>>
>> - devm_add_action_or_reset(dev,
>> - (void(*)(void *))clk_disable_unprepare,
>> - priv->clk);
>> + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
>> + if (ret)
>> + return ret;
>>
>> platform_set_drvdata(pdev, priv);
>> priv->dev = dev;
>> @@ -433,16 +465,16 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
>>
>> ret = reset_control_reset(priv->reset);
>> if (ret)
>> - return ret;
>> + goto err_disable_clks;
>>
>> ret = dwc3_meson_g12a_get_phys(priv);
>> if (ret)
>> - return ret;
>> + goto err_disable_clks;
>>
>> if (priv->vbus) {
>> ret = regulator_enable(priv->vbus);
>> if (ret)
>> - return ret;
>> + goto err_disable_clks;
>> }
>>
>> /* Get dr_mode */
>> @@ -458,7 +490,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
>> dwc3_meson_g12a_irq_thread,
>> IRQF_ONESHOT, pdev->name, priv);
>> if (ret)
>> - return ret;
>> + goto err_disable_clks;
>> }
>>
>> dwc3_meson_g12a_usb_init(priv);
>> @@ -467,7 +499,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
>> for (i = 0 ; i < PHY_COUNT ; ++i) {
>> ret = phy_init(priv->phys[i]);
>> if (ret)
>> - return ret;
>> + goto err_disable_clks;
>> }
>>
>> /* Set PHY Power */
>> @@ -478,18 +510,17 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
>> }
>>
>> ret = of_platform_populate(np, NULL, NULL, dev);
>> - if (ret) {
>> - clk_disable_unprepare(priv->clk);
>> + if (ret)
>> goto err_phys_power;
>> - }
>> +
>> + if (priv->otg_mode != USB_DR_MODE_OTG)
>> + goto setup_pm_runtime;
>>
>> /* Setup OTG mode corresponding to the ID pin */
>> - if (priv->otg_mode == USB_DR_MODE_OTG) {
>> - otg_id = dwc3_meson_g12a_get_id(priv);
>> - if (otg_id != priv->otg_phy_mode) {
>> - if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
>> - dev_warn(dev, "Failed to switch OTG mode\n");
>> - }
>> + otg_id = dwc3_meson_g12a_get_id(priv);
>> + if (otg_id != priv->otg_phy_mode) {
>> + if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
>> + dev_warn(dev, "Failed to switch OTG mode\n");
>> }
>>
>> /* Setup role switcher */
>> @@ -504,6 +535,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
>> if (IS_ERR(priv->role_switch))
>> dev_warn(dev, "Unable to register Role Switch\n");
>>
>> +setup_pm_runtime:
>
> Ditto
>
>> pm_runtime_set_active(dev);
>> pm_runtime_enable(dev);
>> pm_runtime_get_sync(dev);
>> @@ -518,6 +550,9 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
>> for (i = 0 ; i < PHY_COUNT ; ++i)
>> phy_exit(priv->phys[i]);
>>
>> +err_disable_clks:
>> + clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
>> +
>> return ret;
>> }
>>
>> @@ -527,7 +562,8 @@ static int dwc3_meson_g12a_remove(struct platform_device *pdev)
>> struct device *dev = &pdev->dev;
>> int i;
>>
>> - usb_role_switch_unregister(priv->role_switch);
>> + if (priv->otg_mode == USB_DR_MODE_OTG)
>> + usb_role_switch_unregister(priv->role_switch);
>>
>> of_platform_depopulate(dev);
>>
>> @@ -547,7 +583,7 @@ static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev)
>> {
>> struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
>>
>> - clk_disable(priv->clk);
>> + clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
>>
>> return 0;
>> }
>> @@ -556,7 +592,7 @@ static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev)
>> {
>> struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
>>
>> - return clk_enable(priv->clk);
>> + return clk_bulk_prepare_enable(priv->num_clks, priv->clks);
>> }
>>
>> static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev)
>> @@ -619,7 +655,14 @@ static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = {
>> };
>>
>> static const struct of_device_id dwc3_meson_g12a_match[] = {
>> - { .compatible = "amlogic,meson-g12a-usb-ctrl" },
>> + {
>> + .compatible = "amlogic,meson-g12a-usb-ctrl",
>> + .data = (void *)MESON_SOC_G12A,
>> + },
>> + {
>> + .compatible = "amlogic,meson-a1-usb-ctrl",
>> + .data = (void *)MESON_SOC_A1,
>> + },
>> { /* Sentinel */ }
>> };
>> MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match);
>>
>
> Neil
>
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>
> .
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue
2020-01-09 2:30 ` [PATCH v4 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue Hanjie Lin
2020-01-09 9:13 ` Neil Armstrong
@ 2020-01-15 8:44 ` Felipe Balbi
2020-01-15 12:41 ` Martin Blumenstingl
1 sibling, 1 reply; 18+ messages in thread
From: Felipe Balbi @ 2020-01-15 8:44 UTC (permalink / raw)
To: Hanjie Lin, Jerome Brunet, Neil Armstrong, Rob Herring,
Greg Kroah-Hartman, Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
[-- Attachment #1.1: Type: text/plain, Size: 984 bytes --]
Hi,
Hanjie Lin <hanjie.lin@amlogic.com> writes:
> Adds support for Amlogic A1 USB Control Glue HW.
>
> The Amlogic A1 SoC Family embeds 1 USB Controllers:
> - a DWC3 IP configured as Host for USB2 and USB3
>
> A glue connects the controllers to the USB2 PHY of A1 SoC.
>
> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
you're not really adding a new glue. Rather, you're adding support for a
new platform in an existing glue. Make sure subject is clearer
> @@ -409,17 +426,32 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
> priv->vbus = NULL;
> }
>
> - priv->clk = devm_clk_get(dev, NULL);
> - if (IS_ERR(priv->clk))
> - return PTR_ERR(priv->clk);
> + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
> +
> + if (priv->soc_id == MESON_SOC_G12A) {
you can use of_device_is_compatible() and get rid of the enumeration you added.
--
balbi
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue
2020-01-15 8:44 ` Felipe Balbi
@ 2020-01-15 12:41 ` Martin Blumenstingl
2020-01-15 12:46 ` Felipe Balbi
0 siblings, 1 reply; 18+ messages in thread
From: Martin Blumenstingl @ 2020-01-15 12:41 UTC (permalink / raw)
To: Felipe Balbi
Cc: Rob Herring, Hanjie Lin, Victor Wan, Jianxin Pan, Neil Armstrong,
Stephen Boyd, Kevin Hilman, Michael Turquette, linux-usb,
Yue Wang, Qiufang Dai, devicetree, Liang Yang, Jian Hu,
Xingyu Chen, Greg Kroah-Hartman, Carlo Caione, linux-amlogic,
linux-arm-kernel, Jerome Brunet
On Wed, Jan 15, 2020 at 9:43 AM Felipe Balbi <balbi@kernel.org> wrote:
[...]
> > - priv->clk = devm_clk_get(dev, NULL);
> > - if (IS_ERR(priv->clk))
> > - return PTR_ERR(priv->clk);
> > + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
> > +
> > + if (priv->soc_id == MESON_SOC_G12A) {
>
> you can use of_device_is_compatible() and get rid of the enumeration you added.
Hanjie switched to a struct (instead of an enum) that is passed as
"match data" in v5 [0] of this series
personally I prefer what Hanjie has in v5 over
of_device_is_compatible() (because that match data pattern is what we
also use on other Amlogic drivers)
Martin
[0] https://patchwork.kernel.org/patch/11326669/
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue
2020-01-15 12:41 ` Martin Blumenstingl
@ 2020-01-15 12:46 ` Felipe Balbi
0 siblings, 0 replies; 18+ messages in thread
From: Felipe Balbi @ 2020-01-15 12:46 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: Rob Herring, Hanjie Lin, Victor Wan, Jianxin Pan, Neil Armstrong,
Stephen Boyd, Kevin Hilman, Michael Turquette, linux-usb,
Yue Wang, Qiufang Dai, devicetree, Liang Yang, Jian Hu,
Xingyu Chen, Greg Kroah-Hartman, Carlo Caione, linux-amlogic,
linux-arm-kernel, Jerome Brunet
[-- Attachment #1.1: Type: text/plain, Size: 1058 bytes --]
Hi,
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> On Wed, Jan 15, 2020 at 9:43 AM Felipe Balbi <balbi@kernel.org> wrote:
> [...]
>> > - priv->clk = devm_clk_get(dev, NULL);
>> > - if (IS_ERR(priv->clk))
>> > - return PTR_ERR(priv->clk);
>> > + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
>> > +
>> > + if (priv->soc_id == MESON_SOC_G12A) {
>>
>> you can use of_device_is_compatible() and get rid of the enumeration you added.
> Hanjie switched to a struct (instead of an enum) that is passed as
> "match data" in v5 [0] of this series
> personally I prefer what Hanjie has in v5 over
> of_device_is_compatible() (because that match data pattern is what we
> also use on other Amlogic drivers)
but you end up duplicating functionality that already exists by means of
of_device_is_compatible(). Frankly, I don't have a hard opinion about
this anyway, since it's not touching dwc3 core.
In this case, I'll defer to whatever you guys prefer.
--
balbi
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^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 5/6] arm64: dts: meson: a1: Enable USB2 PHY
2020-01-09 2:30 [PATCH v4 0/6] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
` (3 preceding siblings ...)
2020-01-09 2:30 ` [PATCH v4 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue Hanjie Lin
@ 2020-01-09 2:30 ` Hanjie Lin
2020-01-09 2:30 ` [PATCH v4 6/6] arm64: dts: meson: a1: Enable DWC3 controller Hanjie Lin
5 siblings, 0 replies; 18+ messages in thread
From: Hanjie Lin @ 2020-01-09 2:30 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
Enable USB2 PHY for Meson A1 SoC.
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 6fdc0dd..3cae8e9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/meson-a1-power.h>
+#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
/ {
compatible = "amlogic,a1";
@@ -100,6 +101,17 @@
#power-domain-cells = <1>;
status = "okay";
};
+
+ usb2_phy1: phy@40000 {
+ status = "okay";
+ compatible = "amlogic,a1-usb2-phy";
+ clocks = <&clkc_periphs CLKID_XTAL_USB_PHY>;
+ clock-names = "xtal_usb_phy";
+ reg = <0x0 0x40000 0x0 0x2000>;
+ resets = <&reset RESET_USBPHY>;
+ #phy-cells = <0>;
+ power-domains = <&pwrc PWRC_USB_ID>;
+ };
};
gic: interrupt-controller@ff901000 {
--
2.7.4
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v4 6/6] arm64: dts: meson: a1: Enable DWC3 controller
2020-01-09 2:30 [PATCH v4 0/6] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
` (4 preceding siblings ...)
2020-01-09 2:30 ` [PATCH v4 5/6] arm64: dts: meson: a1: Enable USB2 PHY Hanjie Lin
@ 2020-01-09 2:30 ` Hanjie Lin
5 siblings, 0 replies; 18+ messages in thread
From: Hanjie Lin @ 2020-01-09 2:30 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
Enable DWC3 controller for Meson A1 SoC.
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 3cae8e9..009d2c4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -7,6 +7,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/meson-a1-power.h>
#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
+#include <dt-bindings/clock/a1-pll-clkc.h>
+#include <dt-bindings/clock/a1-clkc.h>
/ {
compatible = "amlogic,a1";
@@ -126,6 +128,35 @@
#interrupt-cells = <3>;
#address-cells = <0>;
};
+
+ usb: usb@ffe09000 {
+ status = "okay";
+ compatible = "amlogic,meson-a1-usb-ctrl";
+ reg = <0x0 0xffe09000 0x0 0xa0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc_periphs CLKID_USB_CTRL>,
+ <&clkc_periphs CLKID_USB_BUS>,
+ <&clkc_periphs CLKID_XTAL_USB_CTRL>;
+ clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
+ resets = <&reset RESET_USBCTRL>;
+
+ dr_mode = "host";
+
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+
+ dwc3: usb@ff400000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff400000 0x0 0x100000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,dis_u2_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
};
timer {
--
2.7.4
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^ permalink raw reply related [flat|nested] 18+ messages in thread