From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org
Cc: mike.leach@linaro.org,
Anshuman Khandual <anshuman.khandual@arm.com>,
linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org,
suzuki.poulose@arm.com
Subject: [RFC 11/11] dts: bindings: Document device tree binding for Arm TRBE
Date: Tue, 10 Nov 2020 18:15:09 +0530 [thread overview]
Message-ID: <1605012309-24812-12-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1605012309-24812-1-git-send-email-anshuman.khandual@arm.com>
This patch documents the device tree binding in use for Arm TRBE.
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Documentation/devicetree/bindings/arm/trbe.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/trbe.txt
diff --git a/Documentation/devicetree/bindings/arm/trbe.txt b/Documentation/devicetree/bindings/arm/trbe.txt
new file mode 100644
index 0000000..4bb5b09
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/trbe.txt
@@ -0,0 +1,20 @@
+* Trace Buffer Extension (TRBE)
+
+Trace Buffer Extension (TRBE) is used for collecting trace data generated
+from a corresponding trace unit (ETE) using an in memory trace buffer.
+
+** TRBE Required properties:
+
+- compatible : should be one of:
+ "arm,arm-trbe"
+
+- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
+ TRBE is only supported on a subset of the CPUs, please consult
+ the arm,gic-v3 binding for details on describing a PPI partition.
+
+** Example:
+
+trbe {
+ compatible = "arm,arm-trbe";
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-11-10 12:47 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-10 12:44 [RFC 00/11] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2020-11-10 12:44 ` [RFC 01/11] arm64: Add TRBE definitions Anshuman Khandual
2020-11-10 12:45 ` [RFC 02/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2020-11-12 9:21 ` Suzuki K Poulose
2020-11-12 10:37 ` Linu Cherian
2020-11-12 11:09 ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 03/11] coresight: Do not scan for graph if none is present Anshuman Khandual
2020-11-10 12:45 ` [RFC 04/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2020-11-10 12:45 ` [RFC 05/11] coresight: ete: Add support for sysreg support Anshuman Khandual
2020-11-10 12:45 ` [RFC 06/11] coresight: ete: Detect ETE as one of the supported ETMs Anshuman Khandual
2020-11-14 5:36 ` Tingwei Zhang
2020-11-23 9:56 ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 07/11] coresight: sink: Add TRBE driver Anshuman Khandual
2020-11-12 10:13 ` Suzuki K Poulose
2020-11-25 5:25 ` Anshuman Khandual
2020-11-14 5:38 ` Tingwei Zhang
2020-11-23 3:51 ` Anshuman Khandual
2020-11-10 12:45 ` [RFC 08/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual
2020-11-10 12:45 ` [RFC 09/11] coresight: etm-perf: Disable the path before capturing the trace data Anshuman Khandual
2020-11-12 9:27 ` Suzuki K Poulose
2020-11-23 6:08 ` Anshuman Khandual
2020-11-23 10:01 ` Suzuki K Poulose
2020-11-27 10:32 ` Suzuki K Poulose
2020-12-11 20:31 ` Mathieu Poirier
2020-12-14 10:00 ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 10/11] coresgith: etm-perf: Connect TRBE sink with ETE source Anshuman Khandual
2020-11-12 9:31 ` Suzuki K Poulose
2020-11-23 5:37 ` Anshuman Khandual
2020-12-11 21:31 ` Mathieu Poirier
2020-11-10 12:45 ` Anshuman Khandual [this message]
2020-11-10 18:25 ` [RFC 00/11] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2020-11-14 5:17 ` Tingwei Zhang
2020-11-16 15:00 ` Mike Leach
2020-11-23 3:40 ` Anshuman Khandual
2020-11-23 12:30 ` Mike Leach
2020-11-23 2:43 ` Anshuman Khandual
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1605012309-24812-12-git-send-email-anshuman.khandual@arm.com \
--to=anshuman.khandual@arm.com \
--cc=coresight@lists.linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mathieu.poirier@linaro.org \
--cc=mike.leach@linaro.org \
--cc=suzuki.poulose@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).