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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Linu Cherian <linuc.decode@gmail.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	Coresight ML <coresight@lists.linaro.org>,
	linux-kernel@vger.kernel.org, Linu Cherian <lcherian@marvell.com>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	Mike Leach <mike.leach@linaro.org>
Subject: Re: [RFC 02/11] coresight: etm-perf: Allow an event to use different sinks
Date: Thu, 12 Nov 2020 11:09:49 +0000	[thread overview]
Message-ID: <2e51db24-5d37-7f3f-c306-adde5fbe0dff@arm.com> (raw)
In-Reply-To: <CAAHhmWiWbUTt-BvjeqGm3mfN2L8A8gUOVVDNX0P=WCEDj=Mc4A@mail.gmail.com>

On 11/12/20 10:37 AM, Linu Cherian wrote:
> Hi Suzuki,
> 
> On Thu, Nov 12, 2020 at 2:51 PM Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>>
>> Hi Linu,
>>
>> Please could you test this slightly modified version and give us
>> a Tested-by tag if you are happy with the results ?
>>
>> Suzuki
>>
>>
>> On 11/10/20 12:45 PM, Anshuman Khandual wrote:
>>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>
>>> When there are multiple sinks on the system, in the absence
>>> of a specified sink, it is quite possible that a default sink
>>> for an ETM could be different from that of another ETM. However
>>> we do not support having multiple sinks for an event yet. This
>>> patch allows the event to use the default sinks on the ETMs
>>> where they are scheduled as long as the sinks are of the same
>>> type.
>>>
>>> e.g, if we have 1x1 topology with per-CPU ETRs, the event can
>>> use the per-CPU ETR for the session. However, if the sinks
>>> are of different type, e.g TMC-ETR on one and a custom sink
>>> on another, the event will only trace on the first detected
>>> sink.
>>>
>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>>> ---


>>> @@ -284,7 +307,12 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
>>>        if (!sink_ops(sink)->alloc_buffer || !sink_ops(sink)->free_buffer)
>>>                goto err;
>>>
>>> -     /* Allocate the sink buffer for this session */
>>> +     /*
>>> +      * Allocate the sink buffer for this session. All the sinks
>>> +      * where this event can be scheduled are ensured to be of the
>>> +      * same type. Thus the same sink configuration is used by the
>>> +      * sinks.
>>> +      */
>>>        event_data->snk_config =
>>>                        sink_ops(sink)->alloc_buffer(sink, event, pages,
>>>                                                     nr_pages, overwrite);
>>>
>>
> 
> Perf record and report worked fine with this as well, with formatting
> related opencsd hacks.
> 
> Tested-by : Linu Cherian <lcherian@marvell.com>

Thanks Linu, much appreciated.

Suzuki

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  reply	other threads:[~2020-11-12 11:11 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-10 12:44 [RFC 00/11] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2020-11-10 12:44 ` [RFC 01/11] arm64: Add TRBE definitions Anshuman Khandual
2020-11-10 12:45 ` [RFC 02/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2020-11-12  9:21   ` Suzuki K Poulose
2020-11-12 10:37     ` Linu Cherian
2020-11-12 11:09       ` Suzuki K Poulose [this message]
2020-11-10 12:45 ` [RFC 03/11] coresight: Do not scan for graph if none is present Anshuman Khandual
2020-11-10 12:45 ` [RFC 04/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2020-11-10 12:45 ` [RFC 05/11] coresight: ete: Add support for sysreg support Anshuman Khandual
2020-11-10 12:45 ` [RFC 06/11] coresight: ete: Detect ETE as one of the supported ETMs Anshuman Khandual
2020-11-14  5:36   ` Tingwei Zhang
2020-11-23  9:56     ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 07/11] coresight: sink: Add TRBE driver Anshuman Khandual
2020-11-12 10:13   ` Suzuki K Poulose
2020-11-25  5:25     ` Anshuman Khandual
2020-11-14  5:38   ` Tingwei Zhang
2020-11-23  3:51     ` Anshuman Khandual
2020-11-10 12:45 ` [RFC 08/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual
2020-11-10 12:45 ` [RFC 09/11] coresight: etm-perf: Disable the path before capturing the trace data Anshuman Khandual
2020-11-12  9:27   ` Suzuki K Poulose
2020-11-23  6:08     ` Anshuman Khandual
2020-11-23 10:01       ` Suzuki K Poulose
2020-11-27 10:32   ` Suzuki K Poulose
2020-12-11 20:31     ` Mathieu Poirier
2020-12-14 10:00       ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 10/11] coresgith: etm-perf: Connect TRBE sink with ETE source Anshuman Khandual
2020-11-12  9:31   ` Suzuki K Poulose
2020-11-23  5:37     ` Anshuman Khandual
2020-12-11 21:31   ` Mathieu Poirier
2020-11-10 12:45 ` [RFC 11/11] dts: bindings: Document device tree binding for Arm TRBE Anshuman Khandual
2020-11-10 18:25 ` [RFC 00/11] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2020-11-14  5:17 ` Tingwei Zhang
2020-11-16 15:00   ` Mike Leach
2020-11-23  3:40     ` Anshuman Khandual
2020-11-23 12:30       ` Mike Leach
2020-11-23  2:43   ` Anshuman Khandual

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