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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>,
	linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org
Cc: linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org,
	mike.leach@linaro.org
Subject: Re: [RFC 09/11] coresight: etm-perf: Disable the path before capturing the trace data
Date: Mon, 23 Nov 2020 10:01:32 +0000	[thread overview]
Message-ID: <9973ce74-fca5-6d68-5a0f-c53677a113d6@arm.com> (raw)
In-Reply-To: <b947b100-0393-36da-68e8-36254fe823f9@arm.com>

On 11/23/20 6:08 AM, Anshuman Khandual wrote:
> 
> 
> On 11/12/20 2:57 PM, Suzuki K Poulose wrote:
>> On 11/10/20 12:45 PM, Anshuman Khandual wrote:
>>> perf handle structure needs to be shared with the TRBE IRQ handler for
>>> capturing trace data and restarting the handle. There is a probability
>>> of an undefined reference based crash when etm event is being stopped
>>> while a TRBE IRQ also getting processed. This happens due the release
>>> of perf handle via perf_aux_output_end(). This stops the sinks via the
>>> link before releasing the handle, which will ensure that a simultaneous
>>> TRBE IRQ could not happen.
>>>
>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>>> ---
>>> This might cause problem with traditional sink devices which can be
>>> operated in both sysfs and perf mode. This needs to be addressed
>>> correctly. One option would be to move the update_buffer callback
>>> into the respective sink devices. e.g, disable().
>>>
>>>    drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++
>>>    1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
>>> index 534e205..1a37991 100644
>>> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
>>> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
>>> @@ -429,7 +429,9 @@ static void etm_event_stop(struct perf_event *event, int mode)
>>>              size = sink_ops(sink)->update_buffer(sink, handle,
>>>                              event_data->snk_config);
>>> +        coresight_disable_path(path);
>>>            perf_aux_output_end(handle, size);
>>> +        return;
>>>        }
>>
>> As you mentioned, this is not ideal where another session could be triggered on
>> the sink from a different ETM (not for per-CPU sink) in a different mode before
>> you collect the buffer. I believe the best option is to leave the
>> update_buffer() to disable_hw. This would need to pass on the "handle" to the
>> disable_path.
> 
> Passing 'handle' into coresight_ops_sink->disable() would enable pushing
> updated trace data into perf aux buffer. But do you propose to drop the
> update_buffer() call back completely or just move it into disable() call
> back (along with PERF_EF_UPDATE mode check) for all individual sinks for
> now. May be, later it can be dropped off completely.

Yes, once we update the buffer from within the sink_ops->disable(), we don't
need the update buffer anymore. It is pointless to have a function that
is provided to the external user.

> 
>>
>> That way the races can be handled inside the sinks. Also, this aligns the
>> perf mode of the sinks with that of the sysfs mode.
> 
> Did not get that, could you please elaborate ?
> 

In sysfs mode, we already do an action similar to "update buffer" for all
the sinks. (e.g, see tmc_etr_sync_sysfs_buf() ). i.e, update the buffer
before the sink is disabled. That is the same we propose above.

Suzuki

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  reply	other threads:[~2020-11-23 10:02 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-10 12:44 [RFC 00/11] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2020-11-10 12:44 ` [RFC 01/11] arm64: Add TRBE definitions Anshuman Khandual
2020-11-10 12:45 ` [RFC 02/11] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2020-11-12  9:21   ` Suzuki K Poulose
2020-11-12 10:37     ` Linu Cherian
2020-11-12 11:09       ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 03/11] coresight: Do not scan for graph if none is present Anshuman Khandual
2020-11-10 12:45 ` [RFC 04/11] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2020-11-10 12:45 ` [RFC 05/11] coresight: ete: Add support for sysreg support Anshuman Khandual
2020-11-10 12:45 ` [RFC 06/11] coresight: ete: Detect ETE as one of the supported ETMs Anshuman Khandual
2020-11-14  5:36   ` Tingwei Zhang
2020-11-23  9:56     ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 07/11] coresight: sink: Add TRBE driver Anshuman Khandual
2020-11-12 10:13   ` Suzuki K Poulose
2020-11-25  5:25     ` Anshuman Khandual
2020-11-14  5:38   ` Tingwei Zhang
2020-11-23  3:51     ` Anshuman Khandual
2020-11-10 12:45 ` [RFC 08/11] coresight: etm-perf: Truncate the perf record if handle has no space Anshuman Khandual
2020-11-10 12:45 ` [RFC 09/11] coresight: etm-perf: Disable the path before capturing the trace data Anshuman Khandual
2020-11-12  9:27   ` Suzuki K Poulose
2020-11-23  6:08     ` Anshuman Khandual
2020-11-23 10:01       ` Suzuki K Poulose [this message]
2020-11-27 10:32   ` Suzuki K Poulose
2020-12-11 20:31     ` Mathieu Poirier
2020-12-14 10:00       ` Suzuki K Poulose
2020-11-10 12:45 ` [RFC 10/11] coresgith: etm-perf: Connect TRBE sink with ETE source Anshuman Khandual
2020-11-12  9:31   ` Suzuki K Poulose
2020-11-23  5:37     ` Anshuman Khandual
2020-12-11 21:31   ` Mathieu Poirier
2020-11-10 12:45 ` [RFC 11/11] dts: bindings: Document device tree binding for Arm TRBE Anshuman Khandual
2020-11-10 18:25 ` [RFC 00/11] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2020-11-14  5:17 ` Tingwei Zhang
2020-11-16 15:00   ` Mike Leach
2020-11-23  3:40     ` Anshuman Khandual
2020-11-23 12:30       ` Mike Leach
2020-11-23  2:43   ` Anshuman Khandual

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