[PATCH 0/5] Change mmsys compatible for mt8195 mediatek-drm

[PATCH 0/5] Change mmsys compatible for mt8195 mediatek-drm

[Jason-JH.Lin]

For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.

For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.

Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.

Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's not
including in VDOSYS0.

To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.

Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.

Jason-JH.Lin (5):
  dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
  soc: mediatek: change compatible name for mt8195
  drm/mediatek: change compatible name for mt8195
  arm64: dts: change compatible of vdosys0 and vdosys1 for mt8195
  dt-bindings: arm: mediatek: mmsys: remove the unused compatible for
    mt8195

 .../bindings/arm/mediatek/mediatek,mmsys.yaml |   3 +-
 arch/arm64/boot/dts/mediatek/mt8195.dtsi      |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        | 124 ++-------------
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   6 -
 drivers/soc/mediatek/mtk-mmsys.c              | 141 +++---------------
 drivers/soc/mediatek/mtk-mmsys.h              |   6 -
 6 files changed, 36 insertions(+), 248 deletions(-)

-- 
2.18.0


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[PATCH 1/5] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195

[Jason-JH.Lin]

For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.

For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.

Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.

Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's not
including in VDOSYS0.

To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.

Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.

Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding")
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml        | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 6ad023eec193..a53b32c0a608 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -32,6 +32,8 @@ properties:
               - mediatek,mt8186-mmsys
               - mediatek,mt8192-mmsys
               - mediatek,mt8195-mmsys
+              - mediatek,mt8195-vdosys0
+              - mediatek,mt8195-vdosys1
               - mediatek,mt8365-mmsys
           - const: syscon
       - items:
-- 
2.18.0


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Re: [PATCH 1/5] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195

[Matthias Brugger]

On 14/09/2022 20:23, Jason-JH.Lin wrote:
> For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> pipelines binding to 1 mmsys with the same power domain, the same
> clock driver and the same mediatek-drm driver.
> 
> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
> 2 different power domains, different clock drivers and different
> mediatek-drm drivers.
> 
> Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
> CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
> and they makes VDOSYS0 supports PQ function while they are not
> including in VDOSYS1.
> 
> Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
> component). It makes VDOSYS1 supports the HDR function while it's not
> including in VDOSYS0.
> 
> To summarize0:
> Only VDOSYS0 can support PQ adjustment.
> Only VDOSYS1 can support HDR adjustment.
> 
> Therefore, we need to separate these two different mmsys hardwares to
> 2 different compatibles for MT8195.
> 
> Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding")
> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

I'm not sure Krzysztof gave his Acked-by tag.

> ---
>   .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml        | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index 6ad023eec193..a53b32c0a608 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -32,6 +32,8 @@ properties:
>                 - mediatek,mt8186-mmsys
>                 - mediatek,mt8192-mmsys
>                 - mediatek,mt8195-mmsys
> +              - mediatek,mt8195-vdosys0

As I said in the last submission, we should make mediatek,mt8195-mmsys as a 
fallback of vdosys0. Actually mediatek,mt8195-mmsys is only used for the 
fallback of vdosys0.

Regards,
Matthias

> +              - mediatek,mt8195-vdosys1
>                 - mediatek,mt8365-mmsys
>             - const: syscon
>         - items:

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Re: [PATCH 1/5] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195

[Jason-JH Lin]

Hi Matthias,

Thanks for the reviews.

On Wed, 2022-09-14 at 23:24 +0200, Matthias Brugger wrote:
> 
> On 14/09/2022 20:23, Jason-JH.Lin wrote:
> > For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> > pipelines binding to 1 mmsys with the same power domain, the same
> > clock driver and the same mediatek-drm driver.
> > 
> > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
> > to
> > 2 different power domains, different clock drivers and different
> > mediatek-drm drivers.
> > 
> > Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
> > CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture
> > Quality)
> > and they makes VDOSYS0 supports PQ function while they are not
> > including in VDOSYS1.
> > 
> > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
> > component). It makes VDOSYS1 supports the HDR function while it's
> > not
> > including in VDOSYS0.
> > 
> > To summarize0:
> > Only VDOSYS0 can support PQ adjustment.
> > Only VDOSYS1 can support HDR adjustment.
> > 
> > Therefore, we need to separate these two different mmsys hardwares
> > to
> > 2 different compatibles for MT8195.
> > 
> > Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195
> > SoC binding")
> > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> I'm not sure Krzysztof gave his Acked-by tag.

I'll remove this tag.
> 
> > ---
> >   .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml        |
> > 2 ++
> >   1 file changed, 2 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > index 6ad023eec193..a53b32c0a608 100644
> > ---
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > @@ -32,6 +32,8 @@ properties:
> >                 - mediatek,mt8186-mmsys
> >                 - mediatek,mt8192-mmsys
> >                 - mediatek,mt8195-mmsys
> > +              - mediatek,mt8195-vdosys0
> 
> As I said in the last submission, we should make mediatek,mt8195-
> mmsys as a 
> fallback of vdosys0. Actually mediatek,mt8195-mmsys is only used for
> the 
> fallback of vdosys0.

I think adding both vdosys0 and vdosys1 can make the description of
this patch clearer. 

It's find to me to only add "mediatek,mt8195-vdosys0" in this patch.
So I'll remove the "mediatek,mt8195-vdosys1" at the next version.

Regards,
Jason-JH.Lin
> 
> Regards,
> Matthias
> 
> > +              - mediatek,mt8195-vdosys1
> >                 - mediatek,mt8365-mmsys
> >             - const: syscon
> >         - items:
> 
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


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Re: [PATCH 1/5] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195

[Matthias Brugger]

Hi Jason,

On 15/09/2022 03:24, Jason-JH Lin wrote:
> Hi Matthias,
> 
> Thanks for the reviews.
> 
> On Wed, 2022-09-14 at 23:24 +0200, Matthias Brugger wrote:
>>
>> On 14/09/2022 20:23, Jason-JH.Lin wrote:
>>> For previous MediaTek SoCs, such as MT8173, there are 2 display HW
>>> pipelines binding to 1 mmsys with the same power domain, the same
>>> clock driver and the same mediatek-drm driver.
>>>
>>> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
>>> to
>>> 2 different power domains, different clock drivers and different
>>> mediatek-drm drivers.
>>>
>>> Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
>>> CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture
>>> Quality)
>>> and they makes VDOSYS0 supports PQ function while they are not
>>> including in VDOSYS1.
>>>
>>> Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
>>> component). It makes VDOSYS1 supports the HDR function while it's
>>> not
>>> including in VDOSYS0.
>>>
>>> To summarize0:
>>> Only VDOSYS0 can support PQ adjustment.
>>> Only VDOSYS1 can support HDR adjustment.
>>>
>>> Therefore, we need to separate these two different mmsys hardwares
>>> to
>>> 2 different compatibles for MT8195.
>>>
>>> Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195
>>> SoC binding")
>>> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
>>> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> I'm not sure Krzysztof gave his Acked-by tag.
> 
> I'll remove this tag.
>>
>>> ---
>>>    .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml        |
>>> 2 ++
>>>    1 file changed, 2 insertions(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
>>> l
>>> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
>>> l
>>> index 6ad023eec193..a53b32c0a608 100644
>>> ---
>>> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
>>> l
>>> +++
>>> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
>>> l
>>> @@ -32,6 +32,8 @@ properties:
>>>                  - mediatek,mt8186-mmsys
>>>                  - mediatek,mt8192-mmsys
>>>                  - mediatek,mt8195-mmsys
>>> +              - mediatek,mt8195-vdosys0
>>
>> As I said in the last submission, we should make mediatek,mt8195-
>> mmsys as a
>> fallback of vdosys0. Actually mediatek,mt8195-mmsys is only used for
>> the
>> fallback of vdosys0.
> 
> I think adding both vdosys0 and vdosys1 can make the description of
> this patch clearer.
> 
> It's find to me to only add "mediatek,mt8195-vdosys0" in this patch.
> So I'll remove the "mediatek,mt8195-vdosys1" at the next version.
> 

That's not what I wanted to suggest. Up to now in upstream kernel compatible 
mediatek,mt8195-mmsys enables support fro vdosys0. The vdosys1 is not yet 
upstream, so no support.
If we change the compatible, we should keep mediatek,mt8195-mmsys as fallback of 
"mediatek,mt8195-vdosys0" so that older device tree blobs won't break with a 
newer kernel.
For "mediatek,mt8195-vdosys1" we do not need a fallback compatible as the code 
never reached upstream, so no breakage expected.

Hope I explain myself now.

Regards,
Matthias


> Regards,
> Jason-JH.Lin
>>
>> Regards,
>> Matthias
>>
>>> +              - mediatek,mt8195-vdosys1
>>>                  - mediatek,mt8365-mmsys
>>>              - const: syscon
>>>          - items:
>>
>>

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Re: [PATCH 1/5] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195

[Jason-JH Lin]

On Thu, 2022-09-15 at 18:20 +0200, Matthias Brugger wrote:
> Hi Jason,
> 
> On 15/09/2022 03:24, Jason-JH Lin wrote:
> > Hi Matthias,
> > 
> > Thanks for the reviews.
> > 
> > On Wed, 2022-09-14 at 23:24 +0200, Matthias Brugger wrote:
> > > 
> > > On 14/09/2022 20:23, Jason-JH.Lin wrote:
> > > > For previous MediaTek SoCs, such as MT8173, there are 2 display
> > > > HW
> > > > pipelines binding to 1 mmsys with the same power domain, the
> > > > same
> > > > clock driver and the same mediatek-drm driver.
> > > > 
> > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines
> > > > binding
> > > > to
> > > > 2 different power domains, different clock drivers and
> > > > different
> > > > mediatek-drm drivers.
> > > > 
> > > > Moreover, Hardware pipeline of VDOSYS0 has these components:
> > > > COLOR,
> > > > CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture
> > > > Quality)
> > > > and they makes VDOSYS0 supports PQ function while they are not
> > > > including in VDOSYS1.
> > > > 
> > > > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR
> > > > related
> > > > component). It makes VDOSYS1 supports the HDR function while
> > > > it's
> > > > not
> > > > including in VDOSYS0.
> > > > 
> > > > To summarize0:
> > > > Only VDOSYS0 can support PQ adjustment.
> > > > Only VDOSYS1 can support HDR adjustment.
> > > > 
> > > > Therefore, we need to separate these two different mmsys
> > > > hardwares
> > > > to
> > > > 2 different compatibles for MT8195.
> > > > 
> > > > Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add
> > > > mt8195
> > > > SoC binding")
> > > > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> > > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > > 
> > > I'm not sure Krzysztof gave his Acked-by tag.
> > 
> > I'll remove this tag.
> > > 
> > > > ---
> > > >    .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml    
> > > >     |
> > > > 2 ++
> > > >    1 file changed, 2 insertions(+)
> > > > 
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > index 6ad023eec193..a53b32c0a608 100644
> > > > ---
> > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > +++
> > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > @@ -32,6 +32,8 @@ properties:
> > > >                  - mediatek,mt8186-mmsys
> > > >                  - mediatek,mt8192-mmsys
> > > >                  - mediatek,mt8195-mmsys
> > > > +              - mediatek,mt8195-vdosys0
> > > 
> > > As I said in the last submission, we should make mediatek,mt8195-
> > > mmsys as a
> > > fallback of vdosys0. Actually mediatek,mt8195-mmsys is only used
> > > for
> > > the
> > > fallback of vdosys0.
> > 
> > I think adding both vdosys0 and vdosys1 can make the description of
> > this patch clearer.
> > 
> > It's find to me to only add "mediatek,mt8195-vdosys0" in this
> > patch.
> > So I'll remove the "mediatek,mt8195-vdosys1" at the next version.
> > 
> 
> That's not what I wanted to suggest. Up to now in upstream kernel
> compatible 
> mediatek,mt8195-mmsys enables support fro vdosys0. The vdosys1 is not
> yet 
> upstream, so no support.
> If we change the compatible, we should keep mediatek,mt8195-mmsys as
> fallback of 
> "mediatek,mt8195-vdosys0" so that older device tree blobs won't break
> with a 
> newer kernel.
> For "mediatek,mt8195-vdosys1" we do not need a fallback compatible as
> the code 
> never reached upstream, so no breakage expected.
> 
> Hope I explain myself now.
> 
> Regards,
> Matthias
> 

I think I misunderstood your reply to the patch "dt-bindings: arm:
mediatek: mmsys: remove the unused compatible for mt8195", so I merge
it into this patch.

Thanks for your patient explanation.
I will keep the "mediatek,mt8195-
mmsys" in this patch.

Regards,
Jason-JH.Lin

> 
> > Regards,
> > Jason-JH.Lin
> > > 
> > > Regards,
> > > Matthias
> > > 
> > > > +              - mediatek,mt8195-vdosys1
> > > >                  - mediatek,mt8365-mmsys
> > > >              - const: syscon
> > > >          - items:
> > > 
> > > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


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Re: [PATCH 1/5] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195

[Jason-JH Lin]

On Thu, 2022-09-15 at 18:20 +0200, Matthias Brugger wrote:
> Hi Jason,
> 
> On 15/09/2022 03:24, Jason-JH Lin wrote:
> > Hi Matthias,
> > 
> > Thanks for the reviews.
> > 
> > On Wed, 2022-09-14 at 23:24 +0200, Matthias Brugger wrote:
> > > 
> > > On 14/09/2022 20:23, Jason-JH.Lin wrote:
> > > > For previous MediaTek SoCs, such as MT8173, there are 2 display
> > > > HW
> > > > pipelines binding to 1 mmsys with the same power domain, the
> > > > same
> > > > clock driver and the same mediatek-drm driver.
> > > > 
> > > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines
> > > > binding
> > > > to
> > > > 2 different power domains, different clock drivers and
> > > > different
> > > > mediatek-drm drivers.
> > > > 
> > > > Moreover, Hardware pipeline of VDOSYS0 has these components:
> > > > COLOR,
> > > > CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture
> > > > Quality)
> > > > and they makes VDOSYS0 supports PQ function while they are not
> > > > including in VDOSYS1.
> > > > 
> > > > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR
> > > > related
> > > > component). It makes VDOSYS1 supports the HDR function while
> > > > it's
> > > > not
> > > > including in VDOSYS0.
> > > > 
> > > > To summarize0:
> > > > Only VDOSYS0 can support PQ adjustment.
> > > > Only VDOSYS1 can support HDR adjustment.
> > > > 
> > > > Therefore, we need to separate these two different mmsys
> > > > hardwares
> > > > to
> > > > 2 different compatibles for MT8195.
> > > > 
> > > > Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add
> > > > mt8195
> > > > SoC binding")
> > > > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> > > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > > 
> > > I'm not sure Krzysztof gave his Acked-by tag.
> > 
> > I'll remove this tag.
> > > 
> > > > ---
> > > >    .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml    
> > > >     |
> > > > 2 ++
> > > >    1 file changed, 2 insertions(+)
> > > > 
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > index 6ad023eec193..a53b32c0a608 100644
> > > > ---
> > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > +++
> > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys
> > > > .yam
> > > > l
> > > > @@ -32,6 +32,8 @@ properties:
> > > >                  - mediatek,mt8186-mmsys
> > > >                  - mediatek,mt8192-mmsys
> > > >                  - mediatek,mt8195-mmsys
> > > > +              - mediatek,mt8195-vdosys0
> > > 
> > > As I said in the last submission, we should make mediatek,mt8195-
> > > mmsys as a
> > > fallback of vdosys0. Actually mediatek,mt8195-mmsys is only used
> > > for
> > > the
> > > fallback of vdosys0.
> > 
> > I think adding both vdosys0 and vdosys1 can make the description of
> > this patch clearer.
> > 
> > It's find to me to only add "mediatek,mt8195-vdosys0" in this
> > patch.
> > So I'll remove the "mediatek,mt8195-vdosys1" at the next version.
> > 
> 
> That's not what I wanted to suggest. Up to now in upstream kernel
> compatible 
> mediatek,mt8195-mmsys enables support fro vdosys0. The vdosys1 is not
> yet 
> upstream, so no support.
> If we change the compatible, we should keep mediatek,mt8195-mmsys as
> fallback of 
> "mediatek,mt8195-vdosys0" so that older device tree blobs won't break
> with a Mtk811
> newer kernel.
> For "mediatek,mt8195-vdosys1" we do not need a fallback compatible as
> the code 
> never reached upstream, so no breakage expected.
> 
> Hope I explain myself now.
> 
> Regards,
> Matthias
> 

I think I misunderstood your reply to the patch "dt-bindings: arm:
mediatek: mmsys: remove the unused compatible for mt8195", so I merge
it into this patch.

Thanks for your patient explanation.
I will keep the "mediatek,mt8195-
mmsys" in this patch.

Regards,
Jason-JH.Lin

> 
> > Regards,
> > Jason-JH.Lin
> > > 
> > > Regards,
> > > Matthias
> > > 
> > > > +              - mediatek,mt8195-vdosys1
> > > >                  - mediatek,mt8365-mmsys
> > > >              - const: syscon
> > > >          - items:
> > > 
> > > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


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[PATCH 2/5] soc: mediatek: change compatible name for mt8195

[Jason-JH.Lin]

In mt8195, vdosys0 and vdosys1 are 2 different function blocks
for mediatek-drm, so using 2 compatible instead of identifying
multiple mmsys by io_start.

Fixes: b804923b7ccb ("soc: mediatek: add mtk-mmsys support for mt8195 vdosys0")
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
---
 drivers/soc/mediatek/mtk-mmsys.c | 141 +++++--------------------------
 drivers/soc/mediatek/mtk-mmsys.h |   6 --
 2 files changed, 21 insertions(+), 126 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 06d8e83a2cb5..e1c653f3abc0 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -26,61 +26,26 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 };
 
-static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt2701_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.clk_driver = "clk-mt2712-mm",
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 };
 
-static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt2712_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
 	.clk_driver = "clk-mt6779-mm",
 };
 
-static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt6779_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
 	.clk_driver = "clk-mt6797-mm",
 };
 
-static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt6797_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
 	.clk_driver = "clk-mt8167-mm",
 	.routes = mt8167_mmsys_routing_table,
 	.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
 };
 
-static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8167_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.clk_driver = "clk-mt8173-mm",
 	.routes = mmsys_default_routing_table,
@@ -88,13 +53,6 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
-static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8173_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.clk_driver = "clk-mt8183-mm",
 	.routes = mmsys_mt8183_routing_table,
@@ -102,13 +60,6 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
-static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8183_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.clk_driver = "clk-mt8186-mm",
 	.routes = mmsys_mt8186_routing_table,
@@ -116,13 +67,6 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
 };
 
-static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8186_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.clk_driver = "clk-mt8192-mm",
 	.routes = mmsys_mt8192_routing_table,
@@ -130,66 +74,29 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
 };
 
-static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8192_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
-	.io_start = 0x1c01a000,
 	.clk_driver = "clk-mt8195-vdo0",
 	.routes = mmsys_mt8195_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
 };
 
 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
-	.io_start = 0x1c100000,
 	.clk_driver = "clk-mt8195-vdo1",
 };
 
-static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
-	.num_drv_data = 2,
-	.drv_data = {
-		&mt8195_vdosys0_driver_data,
-		&mt8195_vdosys1_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
 	.clk_driver = "clk-mt8365-mm",
 	.routes = mt8365_mmsys_routing_table,
 	.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
 };
 
-static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8365_mmsys_driver_data,
-	},
-};
-
 struct mtk_mmsys {
 	void __iomem *regs;
 	const struct mtk_mmsys_driver_data *data;
 	spinlock_t lock; /* protects mmsys_sw_rst_b reg */
 	struct reset_controller_dev rcdev;
-	phys_addr_t io_start;
 };
 
-static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
-					const struct mtk_mmsys_match_data *match)
-{
-	int i;
-
-	for (i = 0; i < match->num_drv_data; i++)
-		if (mmsys->io_start == match->drv_data[i]->io_start)
-			return i;
-
-	return -EINVAL;
-}
-
 void mtk_mmsys_ddp_connect(struct device *dev,
 			   enum mtk_ddp_comp_id cur,
 			   enum mtk_ddp_comp_id next)
@@ -284,7 +191,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct platform_device *clks;
 	struct platform_device *drm;
-	const struct mtk_mmsys_match_data *match_data;
 	struct mtk_mmsys *mmsys;
 	struct resource *res;
 	int ret;
@@ -317,20 +223,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		dev_err(dev, "Couldn't get mmsys resource\n");
 		return -EINVAL;
 	}
-	mmsys->io_start = res->start;
-
-	match_data = of_device_get_match_data(dev);
-	if (match_data->num_drv_data > 1) {
-		/* This SoC has multiple mmsys channels */
-		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
-		if (ret < 0) {
-			dev_err(dev, "Couldn't get match driver data\n");
-			return ret;
-		}
-		mmsys->data = match_data->drv_data[ret];
-	} else {
-		dev_dbg(dev, "Using single mmsys channel\n");
-		mmsys->data = match_data->drv_data[0];
+
+	mmsys->data = of_device_get_match_data(&pdev->dev);
+	if (!mmsys->data) {
+		dev_err(dev, "Couldn't get match driver data\n");
+		return -EINVAL;
 	}
 
 	platform_set_drvdata(pdev, mmsys);
@@ -353,47 +250,51 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 static const struct of_device_id of_match_mtk_mmsys[] = {
 	{
 		.compatible = "mediatek,mt2701-mmsys",
-		.data = &mt2701_mmsys_match_data,
+		.data = &mt2701_mmsys_driver_data,
 	},
 	{
 		.compatible = "mediatek,mt2712-mmsys",
-		.data = &mt2712_mmsys_match_data,
+		.data = &mt2712_mmsys_driver_data,
 	},
 	{
 		.compatible = "mediatek,mt6779-mmsys",
-		.data = &mt6779_mmsys_match_data,
+		.data = &mt6779_mmsys_driver_data,
 	},
 	{
 		.compatible = "mediatek,mt6797-mmsys",
-		.data = &mt6797_mmsys_match_data,
+		.data = &mt6797_mmsys_driver_data,
 	},
 	{
 		.compatible = "mediatek,mt8167-mmsys",
-		.data = &mt8167_mmsys_match_data,
+		.data = &mt8167_mmsys_driver_data,
 	},
 	{
 		.compatible = "mediatek,mt8173-mmsys",
-		.data = &mt8173_mmsys_match_data,
+		.data = &mt8173_mmsys_driver_data,
 	},
 	{
 		.compatible = "mediatek,mt8183-mmsys",
-		.data = &mt8183_mmsys_match_data,
+		.data = &mt8183_mmsys_driver_data,
 	},
 	{
 		.compatible = "mediatek,mt8186-mmsys",
-		.data = &mt8186_mmsys_match_data,
+		.data = &mt8186_mmsys_driver_data,
 	},
 	{
 		.compatible = "mediatek,mt8192-mmsys",
-		.data = &mt8192_mmsys_match_data,
+		.data = &mt8192_mmsys_driver_data,
+	},
+	{
+		.compatible = "mediatek,mt8195-vdosys0",
+		.data = &mt8195_vdosys0_driver_data,
 	},
 	{
-		.compatible = "mediatek,mt8195-mmsys",
-		.data = &mt8195_mmsys_match_data,
+		.compatible = "mediatek,mt8195-vdosys1",
+		.data = &mt8195_vdosys1_driver_data,
 	},
 	{
 		.compatible = "mediatek,mt8365-mmsys",
-		.data = &mt8365_mmsys_match_data,
+		.data = &mt8365_mmsys_driver_data,
 	},
 	{ }
 };
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index f01ba206481d..77f37f8c715b 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,18 +87,12 @@ struct mtk_mmsys_routes {
 };
 
 struct mtk_mmsys_driver_data {
-	const resource_size_t io_start;
 	const char *clk_driver;
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
 };
 
-struct mtk_mmsys_match_data {
-	unsigned short num_drv_data;
-	const struct mtk_mmsys_driver_data *drv_data[];
-};
-
 /*
  * Routes in mt8173, mt2701, mt2712 are different. That means
  * in the same register address, it controls different input/output
-- 
2.18.0


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Re: [PATCH 2/5] soc: mediatek: change compatible name for mt8195

[Matthias Brugger]

On 14/09/2022 20:23, Jason-JH.Lin wrote:
> In mt8195, vdosys0 and vdosys1 are 2 different function blocks
> for mediatek-drm, so using 2 compatible instead of identifying
> multiple mmsys by io_start.
> 
> Fixes: b804923b7ccb ("soc: mediatek: add mtk-mmsys support for mt8195 vdosys0")
> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>

 From what I have seen we can just revert the commit. No fixes tag needed, it 
does not fix any (runtime) bug.

Regards,
Matthias

> ---
>   drivers/soc/mediatek/mtk-mmsys.c | 141 +++++--------------------------
>   drivers/soc/mediatek/mtk-mmsys.h |   6 --
>   2 files changed, 21 insertions(+), 126 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 06d8e83a2cb5..e1c653f3abc0 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -26,61 +26,26 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>   	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
>   };
>   
> -static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
> -	.num_drv_data = 1,
> -	.drv_data = {
> -		&mt2701_mmsys_driver_data,
> -	},
> -};
> -
>   static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
>   	.clk_driver = "clk-mt2712-mm",
>   	.routes = mmsys_default_routing_table,
>   	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
>   };
>   
> -static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
> -	.num_drv_data = 1,
> -	.drv_data = {
> -		&mt2712_mmsys_driver_data,
> -	},
> -};
> -
>   static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
>   	.clk_driver = "clk-mt6779-mm",
>   };
>   
> -static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
> -	.num_drv_data = 1,
> -	.drv_data = {
> -		&mt6779_mmsys_driver_data,
> -	},
> -};
> -
>   static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
>   	.clk_driver = "clk-mt6797-mm",
>   };
>   
> -static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
> -	.num_drv_data = 1,
> -	.drv_data = {
> -		&mt6797_mmsys_driver_data,
> -	},
> -};
> -
>   static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8167-mm",
>   	.routes = mt8167_mmsys_routing_table,
>   	.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
>   };
>   
> -static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
> -	.num_drv_data = 1,
> -	.drv_data = {
> -		&mt8167_mmsys_driver_data,
> -	},
> -};
> -
>   static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8173-mm",
>   	.routes = mmsys_default_routing_table,
> @@ -88,13 +53,6 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>   	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
>   };
>   
> -static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> -	.num_drv_data = 1,
> -	.drv_data = {
> -		&mt8173_mmsys_driver_data,
> -	},
> -};
> -
>   static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8183-mm",
>   	.routes = mmsys_mt8183_routing_table,
> @@ -102,13 +60,6 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>   	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
>   };
>   
> -static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> -	.num_drv_data = 1,
> -	.drv_data = {
> -		&mt8183_mmsys_driver_data,
> -	},
> -};
> -
>   static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8186-mm",
>   	.routes = mmsys_mt8186_routing_table,
> @@ -116,13 +67,6 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
>   	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
>   };
>   
> -static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
> -	.num_drv_data = 1,
> -	.drv_data = {
> -		&mt8186_mmsys_driver_data,
> -	},
> -};
> -
>   static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8192-mm",
>   	.routes = mmsys_mt8192_routing_table,
> @@ -130,66 +74,29 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
>   	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
>   };
>   
> -static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
> -	.num_drv_data = 1,
> -	.drv_data = {
> -		&mt8192_mmsys_driver_data,
> -	},
> -};
> -
>   static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> -	.io_start = 0x1c01a000,
>   	.clk_driver = "clk-mt8195-vdo0",
>   	.routes = mmsys_mt8195_routing_table,
>   	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>   };
>   
>   static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> -	.io_start = 0x1c100000,
>   	.clk_driver = "clk-mt8195-vdo1",
>   };
>   
> -static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> -	.num_drv_data = 2,
> -	.drv_data = {
> -		&mt8195_vdosys0_driver_data,
> -		&mt8195_vdosys1_driver_data,
> -	},
> -};
> -
>   static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
>   	.clk_driver = "clk-mt8365-mm",
>   	.routes = mt8365_mmsys_routing_table,
>   	.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
>   };
>   
> -static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
> -	.num_drv_data = 1,
> -	.drv_data = {
> -		&mt8365_mmsys_driver_data,
> -	},
> -};
> -
>   struct mtk_mmsys {
>   	void __iomem *regs;
>   	const struct mtk_mmsys_driver_data *data;
>   	spinlock_t lock; /* protects mmsys_sw_rst_b reg */
>   	struct reset_controller_dev rcdev;
> -	phys_addr_t io_start;
>   };
>   
> -static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> -					const struct mtk_mmsys_match_data *match)
> -{
> -	int i;
> -
> -	for (i = 0; i < match->num_drv_data; i++)
> -		if (mmsys->io_start == match->drv_data[i]->io_start)
> -			return i;
> -
> -	return -EINVAL;
> -}
> -
>   void mtk_mmsys_ddp_connect(struct device *dev,
>   			   enum mtk_ddp_comp_id cur,
>   			   enum mtk_ddp_comp_id next)
> @@ -284,7 +191,6 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
>   	struct device *dev = &pdev->dev;
>   	struct platform_device *clks;
>   	struct platform_device *drm;
> -	const struct mtk_mmsys_match_data *match_data;
>   	struct mtk_mmsys *mmsys;
>   	struct resource *res;
>   	int ret;
> @@ -317,20 +223,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
>   		dev_err(dev, "Couldn't get mmsys resource\n");
>   		return -EINVAL;
>   	}
> -	mmsys->io_start = res->start;
> -
> -	match_data = of_device_get_match_data(dev);
> -	if (match_data->num_drv_data > 1) {
> -		/* This SoC has multiple mmsys channels */
> -		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> -		if (ret < 0) {
> -			dev_err(dev, "Couldn't get match driver data\n");
> -			return ret;
> -		}
> -		mmsys->data = match_data->drv_data[ret];
> -	} else {
> -		dev_dbg(dev, "Using single mmsys channel\n");
> -		mmsys->data = match_data->drv_data[0];
> +
> +	mmsys->data = of_device_get_match_data(&pdev->dev);
> +	if (!mmsys->data) {
> +		dev_err(dev, "Couldn't get match driver data\n");
> +		return -EINVAL;
>   	}
>   
>   	platform_set_drvdata(pdev, mmsys);
> @@ -353,47 +250,51 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
>   static const struct of_device_id of_match_mtk_mmsys[] = {
>   	{
>   		.compatible = "mediatek,mt2701-mmsys",
> -		.data = &mt2701_mmsys_match_data,
> +		.data = &mt2701_mmsys_driver_data,
>   	},
>   	{
>   		.compatible = "mediatek,mt2712-mmsys",
> -		.data = &mt2712_mmsys_match_data,
> +		.data = &mt2712_mmsys_driver_data,
>   	},
>   	{
>   		.compatible = "mediatek,mt6779-mmsys",
> -		.data = &mt6779_mmsys_match_data,
> +		.data = &mt6779_mmsys_driver_data,
>   	},
>   	{
>   		.compatible = "mediatek,mt6797-mmsys",
> -		.data = &mt6797_mmsys_match_data,
> +		.data = &mt6797_mmsys_driver_data,
>   	},
>   	{
>   		.compatible = "mediatek,mt8167-mmsys",
> -		.data = &mt8167_mmsys_match_data,
> +		.data = &mt8167_mmsys_driver_data,
>   	},
>   	{
>   		.compatible = "mediatek,mt8173-mmsys",
> -		.data = &mt8173_mmsys_match_data,
> +		.data = &mt8173_mmsys_driver_data,
>   	},
>   	{
>   		.compatible = "mediatek,mt8183-mmsys",
> -		.data = &mt8183_mmsys_match_data,
> +		.data = &mt8183_mmsys_driver_data,
>   	},
>   	{
>   		.compatible = "mediatek,mt8186-mmsys",
> -		.data = &mt8186_mmsys_match_data,
> +		.data = &mt8186_mmsys_driver_data,
>   	},
>   	{
>   		.compatible = "mediatek,mt8192-mmsys",
> -		.data = &mt8192_mmsys_match_data,
> +		.data = &mt8192_mmsys_driver_data,
> +	},
> +	{
> +		.compatible = "mediatek,mt8195-vdosys0",
> +		.data = &mt8195_vdosys0_driver_data,
>   	},
>   	{
> -		.compatible = "mediatek,mt8195-mmsys",
> -		.data = &mt8195_mmsys_match_data,
> +		.compatible = "mediatek,mt8195-vdosys1",
> +		.data = &mt8195_vdosys1_driver_data,
>   	},
>   	{
>   		.compatible = "mediatek,mt8365-mmsys",
> -		.data = &mt8365_mmsys_match_data,
> +		.data = &mt8365_mmsys_driver_data,
>   	},
>   	{ }
>   };
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index f01ba206481d..77f37f8c715b 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,18 +87,12 @@ struct mtk_mmsys_routes {
>   };
>   
>   struct mtk_mmsys_driver_data {
> -	const resource_size_t io_start;
>   	const char *clk_driver;
>   	const struct mtk_mmsys_routes *routes;
>   	const unsigned int num_routes;
>   	const u16 sw0_rst_offset;
>   };
>   
> -struct mtk_mmsys_match_data {
> -	unsigned short num_drv_data;
> -	const struct mtk_mmsys_driver_data *drv_data[];
> -};
> -
>   /*
>    * Routes in mt8173, mt2701, mt2712 are different. That means
>    * in the same register address, it controls different input/output

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Re: [PATCH 2/5] soc: mediatek: change compatible name for mt8195

[Jason-JH Lin]

Hi Matthias,

Thanks for the reviews.

On Wed, 2022-09-14 at 22:42 +0200, Matthias Brugger wrote:
> 
> On 14/09/2022 20:23, Jason-JH.Lin wrote:
> > In mt8195, vdosys0 and vdosys1 are 2 different function blocks
> > for mediatek-drm, so using 2 compatible instead of identifying
> > multiple mmsys by io_start.
> > 
> > Fixes: b804923b7ccb ("soc: mediatek: add mtk-mmsys support for
> > mt8195 vdosys0")
> > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> 
>  From what I have seen we can just revert the commit. No fixes tag
> needed, it 
> does not fix any (runtime) bug.
> 
OK, I'll revert the original patch then add a new patch for
adding driver data of "mediatek,mt8195-vdosys0" compatible.

Regards,
Jason-JH.Lin

> Regards,
> Matthias
> 
> > ---
> >   drivers/soc/mediatek/mtk-mmsys.c | 141 +++++---------------------
> > -----
> >   drivers/soc/mediatek/mtk-mmsys.h |   6 --
> >   2 files changed, 21 insertions(+), 126 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 06d8e83a2cb5..e1c653f3abc0 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -26,61 +26,26 @@ static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> >   	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> > {
> > -	.num_drv_data = 1,
> > -	.drv_data = {
> > -		&mt2701_mmsys_driver_data,
> > -	},
> > -};
> > -
> >   static const struct mtk_mmsys_driver_data
> > mt2712_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt2712-mm",
> >   	.routes = mmsys_default_routing_table,
> >   	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> > {
> > -	.num_drv_data = 1,
> > -	.drv_data = {
> > -		&mt2712_mmsys_driver_data,
> > -	},
> > -};
> > -
> >   static const struct mtk_mmsys_driver_data
> > mt6779_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt6779-mm",
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt6779_mmsys_match_data =
> > {
> > -	.num_drv_data = 1,
> > -	.drv_data = {
> > -		&mt6779_mmsys_driver_data,
> > -	},
> > -};
> > -
> >   static const struct mtk_mmsys_driver_data
> > mt6797_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt6797-mm",
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt6797_mmsys_match_data =
> > {
> > -	.num_drv_data = 1,
> > -	.drv_data = {
> > -		&mt6797_mmsys_driver_data,
> > -	},
> > -};
> > -
> >   static const struct mtk_mmsys_driver_data
> > mt8167_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt8167-mm",
> >   	.routes = mt8167_mmsys_routing_table,
> >   	.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> > {
> > -	.num_drv_data = 1,
> > -	.drv_data = {
> > -		&mt8167_mmsys_driver_data,
> > -	},
> > -};
> > -
> >   static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt8173-mm",
> >   	.routes = mmsys_default_routing_table,
> > @@ -88,13 +53,6 @@ static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> >   	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> > {
> > -	.num_drv_data = 1,
> > -	.drv_data = {
> > -		&mt8173_mmsys_driver_data,
> > -	},
> > -};
> > -
> >   static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt8183-mm",
> >   	.routes = mmsys_mt8183_routing_table,
> > @@ -102,13 +60,6 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> >   	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> > {
> > -	.num_drv_data = 1,
> > -	.drv_data = {
> > -		&mt8183_mmsys_driver_data,
> > -	},
> > -};
> > -
> >   static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt8186-mm",
> >   	.routes = mmsys_mt8186_routing_table,
> > @@ -116,13 +67,6 @@ static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> >   	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt8186_mmsys_match_data =
> > {
> > -	.num_drv_data = 1,
> > -	.drv_data = {
> > -		&mt8186_mmsys_driver_data,
> > -	},
> > -};
> > -
> >   static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt8192-mm",
> >   	.routes = mmsys_mt8192_routing_table,
> > @@ -130,66 +74,29 @@ static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> >   	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> > {
> > -	.num_drv_data = 1,
> > -	.drv_data = {
> > -		&mt8192_mmsys_driver_data,
> > -	},
> > -};
> > -
> >   static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > -	.io_start = 0x1c01a000,
> >   	.clk_driver = "clk-mt8195-vdo0",
> >   	.routes = mmsys_mt8195_routing_table,
> >   	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> >   };
> >   
> >   static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > -	.io_start = 0x1c100000,
> >   	.clk_driver = "clk-mt8195-vdo1",
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> > {
> > -	.num_drv_data = 2,
> > -	.drv_data = {
> > -		&mt8195_vdosys0_driver_data,
> > -		&mt8195_vdosys1_driver_data,
> > -	},
> > -};
> > -
> >   static const struct mtk_mmsys_driver_data
> > mt8365_mmsys_driver_data = {
> >   	.clk_driver = "clk-mt8365-mm",
> >   	.routes = mt8365_mmsys_routing_table,
> >   	.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> >   };
> >   
> > -static const struct mtk_mmsys_match_data mt8365_mmsys_match_data =
> > {
> > -	.num_drv_data = 1,
> > -	.drv_data = {
> > -		&mt8365_mmsys_driver_data,
> > -	},
> > -};
> > -
> >   struct mtk_mmsys {
> >   	void __iomem *regs;
> >   	const struct mtk_mmsys_driver_data *data;
> >   	spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> >   	struct reset_controller_dev rcdev;
> > -	phys_addr_t io_start;
> >   };
> >   
> > -static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> > -					const struct
> > mtk_mmsys_match_data *match)
> > -{
> > -	int i;
> > -
> > -	for (i = 0; i < match->num_drv_data; i++)
> > -		if (mmsys->io_start == match->drv_data[i]->io_start)
> > -			return i;
> > -
> > -	return -EINVAL;
> > -}
> > -
> >   void mtk_mmsys_ddp_connect(struct device *dev,
> >   			   enum mtk_ddp_comp_id cur,
> >   			   enum mtk_ddp_comp_id next)
> > @@ -284,7 +191,6 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> >   	struct device *dev = &pdev->dev;
> >   	struct platform_device *clks;
> >   	struct platform_device *drm;
> > -	const struct mtk_mmsys_match_data *match_data;
> >   	struct mtk_mmsys *mmsys;
> >   	struct resource *res;
> >   	int ret;
> > @@ -317,20 +223,11 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> >   		dev_err(dev, "Couldn't get mmsys resource\n");
> >   		return -EINVAL;
> >   	}
> > -	mmsys->io_start = res->start;
> > -
> > -	match_data = of_device_get_match_data(dev);
> > -	if (match_data->num_drv_data > 1) {
> > -		/* This SoC has multiple mmsys channels */
> > -		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> > -		if (ret < 0) {
> > -			dev_err(dev, "Couldn't get match driver
> > data\n");
> > -			return ret;
> > -		}
> > -		mmsys->data = match_data->drv_data[ret];
> > -	} else {
> > -		dev_dbg(dev, "Using single mmsys channel\n");
> > -		mmsys->data = match_data->drv_data[0];
> > +
> > +	mmsys->data = of_device_get_match_data(&pdev->dev);
> > +	if (!mmsys->data) {
> > +		dev_err(dev, "Couldn't get match driver data\n");
> > +		return -EINVAL;
> >   	}
> >   
> >   	platform_set_drvdata(pdev, mmsys);
> > @@ -353,47 +250,51 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> >   static const struct of_device_id of_match_mtk_mmsys[] = {
> >   	{
> >   		.compatible = "mediatek,mt2701-mmsys",
> > -		.data = &mt2701_mmsys_match_data,
> > +		.data = &mt2701_mmsys_driver_data,
> >   	},
> >   	{
> >   		.compatible = "mediatek,mt2712-mmsys",
> > -		.data = &mt2712_mmsys_match_data,
> > +		.data = &mt2712_mmsys_driver_data,
> >   	},
> >   	{
> >   		.compatible = "mediatek,mt6779-mmsys",
> > -		.data = &mt6779_mmsys_match_data,
> > +		.data = &mt6779_mmsys_driver_data,
> >   	},
> >   	{
> >   		.compatible = "mediatek,mt6797-mmsys",
> > -		.data = &mt6797_mmsys_match_data,
> > +		.data = &mt6797_mmsys_driver_data,
> >   	},
> >   	{
> >   		.compatible = "mediatek,mt8167-mmsys",
> > -		.data = &mt8167_mmsys_match_data,
> > +		.data = &mt8167_mmsys_driver_data,
> >   	},
> >   	{
> >   		.compatible = "mediatek,mt8173-mmsys",
> > -		.data = &mt8173_mmsys_match_data,
> > +		.data = &mt8173_mmsys_driver_data,
> >   	},
> >   	{
> >   		.compatible = "mediatek,mt8183-mmsys",
> > -		.data = &mt8183_mmsys_match_data,
> > +		.data = &mt8183_mmsys_driver_data,
> >   	},
> >   	{
> >   		.compatible = "mediatek,mt8186-mmsys",
> > -		.data = &mt8186_mmsys_match_data,
> > +		.data = &mt8186_mmsys_driver_data,
> >   	},
> >   	{
> >   		.compatible = "mediatek,mt8192-mmsys",
> > -		.data = &mt8192_mmsys_match_data,
> > +		.data = &mt8192_mmsys_driver_data,
> > +	},
> > +	{
> > +		.compatible = "mediatek,mt8195-vdosys0",
> > +		.data = &mt8195_vdosys0_driver_data,
> >   	},
> >   	{
> > -		.compatible = "mediatek,mt8195-mmsys",
> > -		.data = &mt8195_mmsys_match_data,
> > +		.compatible = "mediatek,mt8195-vdosys1",
> > +		.data = &mt8195_vdosys1_driver_data,
> >   	},
> >   	{
> >   		.compatible = "mediatek,mt8365-mmsys",
> > -		.data = &mt8365_mmsys_match_data,
> > +		.data = &mt8365_mmsys_driver_data,
> >   	},
> >   	{ }
> >   };
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index f01ba206481d..77f37f8c715b 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -87,18 +87,12 @@ struct mtk_mmsys_routes {
> >   };
> >   
> >   struct mtk_mmsys_driver_data {
> > -	const resource_size_t io_start;
> >   	const char *clk_driver;
> >   	const struct mtk_mmsys_routes *routes;
> >   	const unsigned int num_routes;
> >   	const u16 sw0_rst_offset;
> >   };
> >   
> > -struct mtk_mmsys_match_data {
> > -	unsigned short num_drv_data;
> > -	const struct mtk_mmsys_driver_data *drv_data[];
> > -};
> > -
> >   /*
> >    * Routes in mt8173, mt2701, mt2712 are different. That means
> >    * in the same register address, it controls different
> > input/output
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


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[PATCH 3/5] drm/mediatek: change compatible name for mt8195

[Jason-JH.Lin]

In mt8195, vdosys0 and vdosys1 are 2 different function blocks
for mediatek-drm, so using 2 compatible instead of identifying
multiple mmsys by io_start.

Fixes: 7266e90a51a3 ("drm/mediatek: Add mediatek-drm of vdosys0 support for mt8195")
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 124 +++----------------------
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |   6 --
 2 files changed, 11 insertions(+), 119 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 5f02f8d0e4fc..8b45bdea7aca 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -218,13 +218,6 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.shadow_register = true,
 };
 
-static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt2701_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 	.main_path = mt7623_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
@@ -233,13 +226,6 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 	.shadow_register = true,
 };
 
-static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt7623_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.main_path = mt2712_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
@@ -249,25 +235,11 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
 };
 
-static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt2712_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
 	.main_path = mt8167_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
 };
 
-static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8167_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.main_path = mt8173_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -275,13 +247,6 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
 };
 
-static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8173_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.main_path = mt8183_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
@@ -289,13 +254,6 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
-static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8183_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.main_path = mt8186_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
@@ -303,13 +261,6 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
 };
 
-static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8186_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.main_path = mt8192_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -317,31 +268,11 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
 };
 
-static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8192_mmsys_driver_data,
-	},
-};
-
 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
-	.io_start = 0x1c01a000,
 	.main_path = mt8195_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
 };
 
-static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
-	.io_start = 0x1c100000,
-};
-
-static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
-	.num_drv_data = 1,
-	.drv_data = {
-		&mt8195_vdosys0_driver_data,
-		&mt8195_vdosys1_driver_data,
-	},
-};
-
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -648,53 +579,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 
 static const struct of_device_id mtk_drm_of_ids[] = {
 	{ .compatible = "mediatek,mt2701-mmsys",
-	  .data = &mt2701_mmsys_match_data},
+	  .data = &mt2701_mmsys_driver_data},
 	{ .compatible = "mediatek,mt7623-mmsys",
-	  .data = &mt7623_mmsys_match_data},
+	  .data = &mt7623_mmsys_driver_data},
 	{ .compatible = "mediatek,mt2712-mmsys",
-	  .data = &mt2712_mmsys_match_data},
+	  .data = &mt2712_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8167-mmsys",
-	  .data = &mt8167_mmsys_match_data},
+	  .data = &mt8167_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8173-mmsys",
-	  .data = &mt8173_mmsys_match_data},
+	  .data = &mt8173_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8183-mmsys",
-	  .data = &mt8183_mmsys_match_data},
+	  .data = &mt8183_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8186-mmsys",
-	  .data = &mt8186_mmsys_match_data},
+	  .data = &mt8186_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
-	  .data = &mt8192_mmsys_match_data},
-	{ .compatible = "mediatek,mt8195-mmsys",
-	  .data = &mt8195_mmsys_match_data},
+	  .data = &mt8192_mmsys_driver_data},
+	{ .compatible = "mediatek,mt8195-vdosys0",
+	  .data = &mt8195_vdosys0_driver_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
 
-static int mtk_drm_find_match_data(struct device *dev,
-				   const struct mtk_mmsys_match_data *match_data)
-{
-	int i;
-	struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
-	struct resource *res;
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		dev_err(dev, "failed to get parent resource\n");
-		return -EINVAL;
-	}
-
-	for (i = 0; i < match_data->num_drv_data; i++)
-		if (match_data->drv_data[i]->io_start == res->start)
-			return i;
-
-	return -EINVAL;
-}
-
 static int mtk_drm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *phandle = dev->parent->of_node;
 	const struct of_device_id *of_id;
-	const struct mtk_mmsys_match_data *match_data;
 	struct mtk_drm_private *private;
 	struct device_node *node;
 	struct component_match *match = NULL;
@@ -715,19 +625,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 	if (!of_id)
 		return -ENODEV;
 
-	match_data = of_id->data;
-	if (match_data->num_drv_data > 1) {
-		/* This SoC has multiple mmsys channels */
-		ret = mtk_drm_find_match_data(dev, match_data);
-		if (ret < 0) {
-			dev_err(dev, "Couldn't get match driver data\n");
-			return ret;
-		}
-		private->data = match_data->drv_data[ret];
-	} else {
-		dev_dbg(dev, "Using single mmsys channel\n");
-		private->data = match_data->drv_data[0];
-	}
+	private->data = of_id->data;
 
 	/* Iterate over sibling DISP function blocks */
 	for_each_child_of_node(phandle->parent, node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 7b37b5cf9629..64a1f66df26a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -21,7 +21,6 @@ struct drm_property;
 struct regmap;
 
 struct mtk_mmsys_driver_data {
-	const resource_size_t io_start;
 	const enum mtk_ddp_comp_id *main_path;
 	unsigned int main_len;
 	const enum mtk_ddp_comp_id *ext_path;
@@ -32,11 +31,6 @@ struct mtk_mmsys_driver_data {
 	bool shadow_register;
 };
 
-struct mtk_mmsys_match_data {
-	unsigned short num_drv_data;
-	const struct mtk_mmsys_driver_data *drv_data[];
-};
-
 struct mtk_drm_private {
 	struct drm_device *drm;
 	struct device *dma_dev;
-- 
2.18.0


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[PATCH 4/5] arm64: dts: change compatible of vdosys0 and vdosys1 for mt8195

[Jason-JH.Lin]

For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.

For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.

Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.

Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's not
including in VDOSYS0.

To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.

Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.

Fixes: b852ee68fd72 ("arm64: dts: mt8195: Add display node for vdosys0")
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..6ec6d59a16ec 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1966,7 +1966,7 @@
 		};
 
 		vdosys0: syscon@1c01a000 {
-			compatible = "mediatek,mt8195-mmsys", "syscon";
+			compatible = "mediatek,mt8195-vdosys0", "syscon";
 			reg = <0 0x1c01a000 0 0x1000>;
 			mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
 			#clock-cells = <1>;
@@ -2101,7 +2101,7 @@
 		};
 
 		vdosys1: syscon@1c100000 {
-			compatible = "mediatek,mt8195-mmsys", "syscon";
+			compatible = "mediatek,mt8195-vdosys1", "syscon";
 			reg = <0 0x1c100000 0 0x1000>;
 			#clock-cells = <1>;
 		};
-- 
2.18.0


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Re: [PATCH 4/5] arm64: dts: change compatible of vdosys0 and vdosys1 for mt8195

[Matthias Brugger]

On 14/09/2022 20:23, Jason-JH.Lin wrote:
> For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> pipelines binding to 1 mmsys with the same power domain, the same
> clock driver and the same mediatek-drm driver.
> 
> For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
> 2 different power domains, different clock drivers and different
> mediatek-drm drivers.
> 
> Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
> CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
> and they makes VDOSYS0 supports PQ function while they are not
> including in VDOSYS1.
> 
> Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
> component). It makes VDOSYS1 supports the HDR function while it's not
> including in VDOSYS0.
> 
> To summarize0:
> Only VDOSYS0 can support PQ adjustment.
> Only VDOSYS1 can support HDR adjustment.
> 
> Therefore, we need to separate these two different mmsys hardwares to
> 2 different compatibles for MT8195.
> 
> Fixes: b852ee68fd72 ("arm64: dts: mt8195: Add display node for vdosys0")

No fixes tag needed, there is no runtime bug.

Regards,
Matthias

> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..6ec6d59a16ec 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1966,7 +1966,7 @@
>   		};
>   
>   		vdosys0: syscon@1c01a000 {
> -			compatible = "mediatek,mt8195-mmsys", "syscon";
> +			compatible = "mediatek,mt8195-vdosys0", "syscon";
>   			reg = <0 0x1c01a000 0 0x1000>;
>   			mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
>   			#clock-cells = <1>;
> @@ -2101,7 +2101,7 @@
>   		};
>   
>   		vdosys1: syscon@1c100000 {
> -			compatible = "mediatek,mt8195-mmsys", "syscon";
> +			compatible = "mediatek,mt8195-vdosys1", "syscon";
>   			reg = <0 0x1c100000 0 0x1000>;
>   			#clock-cells = <1>;
>   		};

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Re: [PATCH 4/5] arm64: dts: change compatible of vdosys0 and vdosys1 for mt8195

[Jason-JH Lin]

Hi Matthias,

Thanks for the review.

On Thu, 2022-09-15 at 18:15 +0200, Matthias Brugger wrote:
> 
> On 14/09/2022 20:23, Jason-JH.Lin wrote:
> > For previous MediaTek SoCs, such as MT8173, there are 2 display HW
> > pipelines binding to 1 mmsys with the same power domain, the same
> > clock driver and the same mediatek-drm driver.
> > 
> > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding
> > to
> > 2 different power domains, different clock drivers and different
> > mediatek-drm drivers.
> > 
> > Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
> > CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture
> > Quality)
> > and they makes VDOSYS0 supports PQ function while they are not
> > including in VDOSYS1.
> > 
> > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
> > component). It makes VDOSYS1 supports the HDR function while it's
> > not
> > including in VDOSYS0.
> > 
> > To summarize0:
> > Only VDOSYS0 can support PQ adjustment.
> > Only VDOSYS1 can support HDR adjustment.
> > 
> > Therefore, we need to separate these two different mmsys hardwares
> > to
> > 2 different compatibles for MT8195.
> > 
> > Fixes: b852ee68fd72 ("arm64: dts: mt8195: Add display node for
> > vdosys0")
> 
> No fixes tag needed, there is no runtime bug.
> 
> Regards,
> Matthias
> 
OK, I'll remove this.

But I think this dts change should be sent after the vdosys1 series are
accepted.
So I'll drop this dts patch at the next version.

Regards,
Jason-JH.Lin

> > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 905d1a90b406..6ec6d59a16ec 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1966,7 +1966,7 @@
> >   		};
> >   
> >   		vdosys0: syscon@1c01a000 {
> > -			compatible = "mediatek,mt8195-mmsys", "syscon";
> > +			compatible = "mediatek,mt8195-vdosys0",
> > "syscon";
> >   			reg = <0 0x1c01a000 0 0x1000>;
> >   			mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
> >   			#clock-cells = <1>;
> > @@ -2101,7 +2101,7 @@
> >   		};
> >   
> >   		vdosys1: syscon@1c100000 {
> > -			compatible = "mediatek,mt8195-mmsys", "syscon";
> > +			compatible = "mediatek,mt8195-vdosys1",
> > "syscon";
> >   			reg = <0 0x1c100000 0 0x1000>;
> >   			#clock-cells = <1>;
> >   		};
> 
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


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[PATCH 5/5] dt-bindings: arm: mediatek: mmsys: remove the unused compatible for mt8195

[Jason-JH.Lin]

The compatible properties of mt8195 have changed to mediatek,mt8195-vdosys0
and mediatek,mt8195-vdosys1 from mediatek,mt895-mmsys, so remove the unused
compatible.

Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding")
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
---
 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml         | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index a53b32c0a608..bfbdd30d2092 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,7 +31,6 @@ properties:
               - mediatek,mt8183-mmsys
               - mediatek,mt8186-mmsys
               - mediatek,mt8192-mmsys
-              - mediatek,mt8195-mmsys
               - mediatek,mt8195-vdosys0
               - mediatek,mt8195-vdosys1
               - mediatek,mt8365-mmsys
-- 
2.18.0


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Re: [PATCH 5/5] dt-bindings: arm: mediatek: mmsys: remove the unused compatible for mt8195

[Matthias Brugger]

On 14/09/2022 20:23, Jason-JH.Lin wrote:
> The compatible properties of mt8195 have changed to mediatek,mt8195-vdosys0
> and mediatek,mt8195-vdosys1 from mediatek,mt895-mmsys, so remove the unused
> compatible.
> 
> Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding")
> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> ---
>   .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml         | 1 -
>   1 file changed, 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> index a53b32c0a608..bfbdd30d2092 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -31,7 +31,6 @@ properties:
>                 - mediatek,mt8183-mmsys
>                 - mediatek,mt8186-mmsys
>                 - mediatek,mt8192-mmsys
> -              - mediatek,mt8195-mmsys

Should be part of the first patch. As described in the review.

Regards,
Matthias

>                 - mediatek,mt8195-vdosys0
>                 - mediatek,mt8195-vdosys1
>                 - mediatek,mt8365-mmsys

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Re: [PATCH 5/5] dt-bindings: arm: mediatek: mmsys: remove the unused compatible for mt8195

[Jason-JH Lin]

On Wed, 2022-09-14 at 22:45 +0200, Matthias Brugger wrote:
> 
> On 14/09/2022 20:23, Jason-JH.Lin wrote:
> > The compatible properties of mt8195 have changed to
> > mediatek,mt8195-vdosys0
> > and mediatek,mt8195-vdosys1 from mediatek,mt895-mmsys, so remove
> > the unused
> > compatible.
> > 
> > Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195
> > SoC binding")
> > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> > ---
> >  
> > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml         |
> > 1 -
> >   1 file changed, 1 deletion(-)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > index a53b32c0a608..bfbdd30d2092 100644
> > ---
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yam
> > l
> > @@ -31,7 +31,6 @@ properties:
> >                 - mediatek,mt8183-mmsys
> >                 - mediatek,mt8186-mmsys
> >                 - mediatek,mt8192-mmsys
> > -              - mediatek,mt8195-mmsys
> 
> Should be part of the first patch. As described in the review.

Ok, I'll merge this patch into the first patch.

Regards,
Jason-JH.Lin

> 
> Regards,
> Matthias
> 
> >                 - mediatek,mt8195-vdosys0
> >                 - mediatek,mt8195-vdosys1
> >                 - mediatek,mt8365-mmsys
> 
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


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