From: Jordan Crouse <jcrouse@codeaurora.org>
To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org,
linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org,
dianders@chromium.org, vireshk@kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 1/2] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings
Date: Wed, 12 Dec 2018 14:18:47 -0700 [thread overview]
Message-ID: <20181212211848.26768-2-jcrouse@codeaurora.org> (raw)
In-Reply-To: <20181212211848.26768-1-jcrouse@codeaurora.org>
Update the GPU bindings and document the new bindings for the GMU
device found with Adreno a6xx targets.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
.../devicetree/bindings/display/msm/gmu.txt | 56 +++++++++++++++++++
.../devicetree/bindings/display/msm/gpu.txt | 41 +++++++++++++-
2 files changed, 94 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt
new file mode 100644
index 000000000000..6152cb551d29
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/gmu.txt
@@ -0,0 +1,56 @@
+Qualcomm adreno/snapdragon GMU (Graphics management unit)
+
+The GMU is a programmable power controller for the GPU. the CPU controls the
+GMU which in turn handles power controls for the GPU.
+
+Required properties:
+- compatible:
+ * "qcom,adreno-gmu"
+- reg: Physical base address and length of the GMU registers.
+- reg-names: Matching names for the register regions
+ * "gmu"
+ * "gmu_pdc"
+ * "gmu_pdc_seg"
+- interrupts: The interrupt signals from the GMU.
+- interrupt-names: Matching names for the interrupts
+ * "hfi"
+ * "gmu"
+- clocks: phandles to the device clocks
+- clock-names: Matching names for the clocks
+ * "gmu"
+ * "cxo"
+ * "axi"
+ * "mnoc"
+- power-domains: should be <&clock_gpucc GPU_CX_GDSC>
+- iommus: phandle to the adreno iommu
+- operating-points-v2: phandle to the OPP operating points
+
+Example:
+
+/ {
+ ...
+
+ gmu: gmu@506a000 {
+ compatible="qcom,adreno-gmu";
+
+ reg = <0x506a000 0x30000>,
+ <0xb280000 0x10000>,
+ <0xb480000 0x10000>;
+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "gmu", "cxo", "axi", "memnoc";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ iommus = <&adreno_smmu 5>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt
index 43fac0fe09bb..8d9415180c22 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -8,14 +8,21 @@ Required properties:
with the chip-id.
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt signal from the gpu.
-- clocks: device clocks
+- interrupt-names: List of names for the interrupt signals. The following can be
+ provided:
+ * "kgsl_3d0_irq"
+- clocks: device clocks (if applicable)
See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required:
+- clock-names: the following clocks can be provided:
* "core"
* "iface"
* "mem_iface"
+- iommus: optional phandle to an adreno iommu instance
+- operating-points-v2: optional phandle to the OPP operating points
+- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that will
+ control the power for the GPU
-Example:
+Example 3xx/4xx/a5xx:
/ {
...
@@ -36,3 +43,31 @@ Example:
<&mmcc MMSS_IMEM_AHB_CLK>;
};
};
+
+Example a6xx (with GMU):
+
+/ {
+ ...
+
+ gpu@5000000 {
+ compatible = "qcom,adreno-630.2", "qcom,adreno";
+ #stream-id-cells = <16>;
+
+ reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+ /*
+ * Look ma, no clocks! The GPU clocks and power are
+ * controlled entirely by the GMU
+ */
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ iommus = <&adreno_smmu 0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+ };
+};
--
2.18.0
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next prev parent reply other threads:[~2018-12-12 21:20 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-12 21:18 [PATCH v6 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU Jordan Crouse
2018-12-12 21:18 ` Jordan Crouse [this message]
2018-12-13 18:39 ` [PATCH v6 1/2] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings Doug Anderson
2018-12-17 21:20 ` Rob Herring
2018-12-17 22:01 ` Jordan Crouse
2018-12-12 21:18 ` [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes Jordan Crouse
2018-12-13 18:40 ` Doug Anderson
2018-12-14 4:40 ` Viresh Kumar
2018-12-14 17:04 ` Doug Anderson
2018-12-17 7:06 ` Viresh Kumar
2018-12-18 0:34 ` Doug Anderson
2018-12-18 18:40 ` Stephen Boyd
2018-12-18 19:05 ` Doug Anderson
2018-12-19 4:49 ` Viresh Kumar
2018-12-19 20:08 ` Rob Herring
2018-12-19 20:40 ` Doug Anderson
2018-12-19 22:40 ` Doug Anderson
2018-12-19 23:47 ` Rob Herring
2018-12-20 21:29 ` Stephen Boyd
2018-12-21 4:52 ` Rajendra Nayak
2018-12-29 1:29 ` Stephen Boyd
2019-01-03 8:45 ` Rajendra Nayak
2019-01-04 20:59 ` Stephen Boyd
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