From: Jordan Crouse <jcrouse@codeaurora.org>
To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org,
linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org,
dianders@chromium.org, vireshk@kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes
Date: Wed, 12 Dec 2018 14:18:48 -0700 [thread overview]
Message-ID: <20181212211848.26768-3-jcrouse@codeaurora.org> (raw)
In-Reply-To: <20181212211848.26768-1-jcrouse@codeaurora.org>
Add the nodes to describe the Adreno GPU and GMU devices.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 123 +++++++++++++++++++++++++++
1 file changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 233a5898ebc2..a608afed502e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
@@ -1349,6 +1350,128 @@
};
};
+
+ gpu@5000000 {
+ compatible = "qcom,adreno-630.2", "qcom,adreno";
+ #stream-id-cells = <16>;
+
+ reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+ /*
+ * Look ma, no clocks! The GPU clocks and power are
+ * controlled entirely by the GMU
+ */
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ iommus = <&adreno_smmu 0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2-qcom-level";
+
+ opp-710000000 {
+ opp-hz = /bits/ 64 <710000000>;
+ qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ opp-675000000 {
+ opp-hz = /bits/ 64 <675000000>;
+ qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-596000000 {
+ opp-hz = /bits/ 64 <596000000>;
+ qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-520000000 {
+ opp-hz = /bits/ 64 <520000000>;
+ qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-414000000 {
+ opp-hz = /bits/ 64 <414000000>;
+ qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-342000000 {
+ opp-hz = /bits/ 64 <342000000>;
+ qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-257000000 {
+ opp-hz = /bits/ 64 <257000000>;
+ qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+ };
+
+ adreno_smmu: iommu@5040000 {
+ compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
+ reg = <0x5040000 0x10000>;
+ #iommu-cells = <1>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_CFG_AHB_CLK>;
+ clock-names = "bus", "iface";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ };
+
+ gmu: gmu@506a000 {
+ compatible="qcom,adreno-gmu";
+
+ reg = <0x506a000 0x30000>,
+ <0xb280000 0x10000>,
+ <0xb480000 0x10000>;
+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "gmu", "cxo", "axi", "memnoc";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ iommus = <&adreno_smmu 5>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2-qcom-level";
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ qcom,level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
gpucc: clock-controller@5090000 {
compatible = "qcom,sdm845-gpucc";
reg = <0x5090000 0x9000>;
--
2.18.0
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next prev parent reply other threads:[~2018-12-12 21:20 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-12 21:18 [PATCH v6 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU Jordan Crouse
2018-12-12 21:18 ` [PATCH v6 1/2] dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings Jordan Crouse
2018-12-13 18:39 ` Doug Anderson
2018-12-17 21:20 ` Rob Herring
2018-12-17 22:01 ` Jordan Crouse
2018-12-12 21:18 ` Jordan Crouse [this message]
2018-12-13 18:40 ` [PATCH v6 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes Doug Anderson
2018-12-14 4:40 ` Viresh Kumar
2018-12-14 17:04 ` Doug Anderson
2018-12-17 7:06 ` Viresh Kumar
2018-12-18 0:34 ` Doug Anderson
2018-12-18 18:40 ` Stephen Boyd
2018-12-18 19:05 ` Doug Anderson
2018-12-19 4:49 ` Viresh Kumar
2018-12-19 20:08 ` Rob Herring
2018-12-19 20:40 ` Doug Anderson
2018-12-19 22:40 ` Doug Anderson
2018-12-19 23:47 ` Rob Herring
2018-12-20 21:29 ` Stephen Boyd
2018-12-21 4:52 ` Rajendra Nayak
2018-12-29 1:29 ` Stephen Boyd
2019-01-03 8:45 ` Rajendra Nayak
2019-01-04 20:59 ` Stephen Boyd
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