Re: [PATCH 04/17 v1] irqchip: Add driver for IXP4xx

From: Marc Zyngier <marc.zyngier@arm.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>,
	Arnd Bergmann <arnd@arndb.de>, Tim Harvey <tharvey@gateworks.com>,
	Krzysztof Halasa <khalasa@piap.pl>,
	Olof Johansson <olof@lixom.net>,
	Thomas Gleixner <tglx@linutronix.de>,
	Imre Kaloz <kaloz@openwrt.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 04/17 v1] irqchip: Add driver for IXP4xx
Date: Mon, 11 Feb 2019 22:11:56 +0000	[thread overview]
Message-ID: <20190211221156.10036ad8@why.wild-wind.fr.eu.org> (raw)
In-Reply-To: <CACRpkdZK7OU9rb-qw9tTjJLNvfQG-VmN_VBXUz9DPqVV11zuww@mail.gmail.com>

On Mon, 11 Feb 2019 21:58:41 +0100
Linus Walleij <linus.walleij@linaro.org> wrote:

> On Mon, Feb 11, 2019 at 4:30 PM Marc Zyngier <marc.zyngier@arm.com> wrote:

[...]

> > How about using something that enforces the endianness of the accesses,
> > as I suspect the bus is hardcoded to BE?  
> 
> So, IIUC (Krzysztof can confirm) IXP4xx works like this that when the
> CPU is brought up in LE mode, all bytes on the address bus are
> swizzled so that the access can always use the CPU native
> endianness.
> 
> Isn't it crazy :D

It's spelled BE32! ;-) I vaguely remember doing some of that on vulcan,
but that's a decade ago, and I've paged it out... ;-)

> This means __raw_writel() will always do the right thing, because
> that uses native endianness, and that is why it is used quite a lot
> in IXP4xx drivers.

OK, it now makes some sense. Maybe a comment somewhere will help if
someone tries to reverse engineer it again in the next decade!

> > Aren't you guaranteed to only have one such irqchip? If so, this could
> > become a static const object, instead of allocating it dynamically. Not
> > a big deal though.  
> 
> Force of habit. Comes from the GPIO side of things where we
> never know how many instances there are of stuff, if it's OK
> I'd like to keep it.

No problem.

> 
> > > +     fwnode = irq_domain_alloc_fwnode(base);  
> >
> > I assume this is a temporary solution until the SoC gains a DT port (and
> > the irqchip a DT node)?  
> 
> Yes, see the later DT patch that passes the parent as
> fwnode, once all boards are converted we can drop this.
> 
> BTW here is how I then use the hierarchical parent in the
> GPIO chip:
> https://marc.info/?l=linux-arm-kernel&m=154923023907623&w=2
> https://marc.info/?l=linux-arm-kernel&m=154923038707686&w=2

Looks pretty cool, and surely even better once entirely converted to DT
(I'm sure I can revive this FSG-3 that has been collecting dust on the
shelf for a number of years).

Please CC me on the whole series next time you respin it!

Thanks,

	M.
-- 
Without deviation from the norm, progress is not possible.

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