Why doesn't arm-smmu (v2) driver take VA_BITS into consideration?

Why doesn't arm-smmu (v2) driver take VA_BITS into consideration?

[Nicolin Chen]

Hello Will/Robin,

I am using an Soc that contains arm-smmu v2 engines. I found that
the arm-smmu driver reads GR_ID2 register and defines ias and oas
of each domain based on the corresponding fields of that GR_ID2.

Using my platform for example, it gets 48-bit for all ias and oas,
being translated from those fields so I got these 2 stages:
        Stage-1: 48-bit VA -> 48-bit IPA
        Stage-2: 48-bit IPA -> 48-bit PA

Then the code does below to configure aperture_end to 48-bit:
 914         domain->geometry.aperture_end = (1UL << ias) - 1;

However, my system configures VA_BITS to 39. So aperture_end==48
is a mismatch comparing to VA_BITS_39. Although the aperture_end
is supposed to cap IOVA allocation, this 48-bit cap won't really
do the job at all.

I saw that arm-smmu-v3 driver takes VA_BITS into consideration:
 1765         switch (smmu_domain->stage) {
 1766         case ARM_SMMU_DOMAIN_S1:
 1767                 ias = (smmu->features & ARM_SMMU_FEAT_VAX) ?
 1768                 ias = min_t(unsigned long, ias, VA_BITS);

So I am wondering if it is intentionally designed so by ignoring
VA_BITS? Would you please help me understand this a bit?

Thank you
Nicolin

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Re: Why doesn't arm-smmu (v2) driver take VA_BITS into consideration?

[Will Deacon]

On Wed, Jun 26, 2019 at 05:19:33PM -0700, Nicolin Chen wrote:
> I am using an Soc that contains arm-smmu v2 engines. I found that
> the arm-smmu driver reads GR_ID2 register and defines ias and oas
> of each domain based on the corresponding fields of that GR_ID2.
> 
> Using my platform for example, it gets 48-bit for all ias and oas,
> being translated from those fields so I got these 2 stages:
>         Stage-1: 48-bit VA -> 48-bit IPA
>         Stage-2: 48-bit IPA -> 48-bit PA
> 
> Then the code does below to configure aperture_end to 48-bit:
>  914         domain->geometry.aperture_end = (1UL << ias) - 1;
> 
> However, my system configures VA_BITS to 39. So aperture_end==48
> is a mismatch comparing to VA_BITS_39. Although the aperture_end
> is supposed to cap IOVA allocation, this 48-bit cap won't really
> do the job at all.

What actually goes wrong, though? IOVAs should only be handed over to
devices, so VA_BITS doesn't strictly matter. It's the DMA masks that are
important.

> I saw that arm-smmu-v3 driver takes VA_BITS into consideration:
>  1765         switch (smmu_domain->stage) {
>  1766         case ARM_SMMU_DOMAIN_S1:
>  1767                 ias = (smmu->features & ARM_SMMU_FEAT_VAX) ?
>  1768                 ias = min_t(unsigned long, ias, VA_BITS);
> 
> So I am wondering if it is intentionally designed so by ignoring
> VA_BITS? Would you please help me understand this a bit?

I think it's simply that SMMUv3 doesn't provide an ID field to tell you
what to use, so we chose to go with VA_BITS since it's what we're using
on the CPU.

Will

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Re: Why doesn't arm-smmu (v2) driver take VA_BITS into consideration?

[Nicolin Chen]

Hi Will,

On Thu, Jun 27, 2019 at 11:26:40AM +0100, Will Deacon wrote:
> On Wed, Jun 26, 2019 at 05:19:33PM -0700, Nicolin Chen wrote:
> > I am using an Soc that contains arm-smmu v2 engines. I found that
> > the arm-smmu driver reads GR_ID2 register and defines ias and oas
> > of each domain based on the corresponding fields of that GR_ID2.
> > 
> > Using my platform for example, it gets 48-bit for all ias and oas,
> > being translated from those fields so I got these 2 stages:
> >         Stage-1: 48-bit VA -> 48-bit IPA
> >         Stage-2: 48-bit IPA -> 48-bit PA
> > 
> > Then the code does below to configure aperture_end to 48-bit:
> >  914         domain->geometry.aperture_end = (1UL << ias) - 1;
> > 
> > However, my system configures VA_BITS to 39. So aperture_end==48
> > is a mismatch comparing to VA_BITS_39. Although the aperture_end
> > is supposed to cap IOVA allocation, this 48-bit cap won't really
> > do the job at all.
> 
> What actually goes wrong, though? IOVAs should only be handed over to
> devices, so VA_BITS doesn't strictly matter. It's the DMA masks that are
> important.

Ah..that's true. I think I misunderstood one of my situations here.

> > I saw that arm-smmu-v3 driver takes VA_BITS into consideration:
> >  1765         switch (smmu_domain->stage) {
> >  1766         case ARM_SMMU_DOMAIN_S1:
> >  1767                 ias = (smmu->features & ARM_SMMU_FEAT_VAX) ?
> >  1768                 ias = min_t(unsigned long, ias, VA_BITS);
> > 
> > So I am wondering if it is intentionally designed so by ignoring
> > VA_BITS? Would you please help me understand this a bit?
> 
> I think it's simply that SMMUv3 doesn't provide an ID field to tell you
> what to use, so we chose to go with VA_BITS since it's what we're using
> on the CPU.

I see. Thanks for explaining!

Nicolin

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