[PATCH V5 1/5] clocksource: imx-sysctr: Add internal clock divider handle

[PATCH V5 1/5] clocksource: imx-sysctr: Add internal clock divider handle

[Anson.Huang]

From: Anson Huang <Anson.Huang@nxp.com>

The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V4:
	- to solve the clock driver probed after system counter driver issue, now we can easily switch to
	  use fixed clock defined in DT and get its rate, then divided by 3 to get real clock rate for
	  system counter driver, no need to add "clock-frequency" property in DT.
---
 drivers/clocksource/timer-imx-sysctr.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c
index fd7d680..b7c80a3 100644
--- a/drivers/clocksource/timer-imx-sysctr.c
+++ b/drivers/clocksource/timer-imx-sysctr.c
@@ -20,6 +20,8 @@
 #define SYS_CTR_EN		0x1
 #define SYS_CTR_IRQ_MASK	0x2
 
+#define SYS_CTR_CLK_DIV		0x3
+
 static void __iomem *sys_ctr_base;
 static u32 cmpcr;
 
@@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node *np)
 	if (ret)
 		return ret;
 
+	/* system counter clock is divided by 3 internally */
+	to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
+
 	sys_ctr_base = timer_of_base(&to_sysctr);
 	cmpcr = readl(sys_ctr_base + CMPCR);
 	cmpcr &= ~SYS_CTR_EN;
-- 
2.7.4


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[PATCH V5 2/5] arm64: Enable TIMER_IMX_SYS_CTR for ARCH_MXC platforms

[Anson.Huang]

From: Anson Huang <Anson.Huang@nxp.com>

ARCH_MXC platforms needs system counter as broadcast timer
to support cpuidle, enable it by default.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
New patch, now that system counter driver lands in main line, we can enable it by default.
---
 arch/arm64/Kconfig.platforms | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 4778c77..f5e623f 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -173,6 +173,7 @@ config ARCH_MXC
 	select PM
 	select PM_GENERIC_DOMAINS
 	select SOC_BUS
+	select TIMER_IMX_SYS_CTR
 	help
 	  This enables support for the ARMv8 based SoCs in the
 	  NXP i.MX family.
-- 
2.7.4


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[PATCH V5 3/5] arm64: dts: imx8mm: Add system counter node

[Anson.Huang]

From: Anson Huang <Anson.Huang@nxp.com>

Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V4:
	- update the clock info using fixed clock node;
	- correct the reg range;
	- update the interrupt number as the system counter driver ONLY uses 1 irq now.
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index b5637f8..8cf7f34 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -560,6 +560,14 @@
 				#pwm-cells = <2>;
 				status = "disabled";
 			};
+
+			system_counter: timer@306a0000 {
+				compatible = "nxp,sysctr-timer";
+				reg = <0x306a0000 0x20000>;
+				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&osc_24m>;
+				clock-names = "per";
+			};
 		};
 
 		aips3: bus@30800000 {
-- 
2.7.4


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[PATCH V5 4/5] arm64: dts: imx8mq: Add system counter node

[Anson.Huang]

From: Anson Huang <Anson.Huang@nxp.com>

Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V4:
	- update the clock info using fixed clock node;
	- correct the reg range;
	- update the interrupt number as the system counter driver ONLY uses 1 irq now.
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index a1bbd80..2991172 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -644,6 +644,14 @@
 				#pwm-cells = <2>;
 				status = "disabled";
 			};
+
+			system_counter: timer@306a0000 {
+				compatible = "nxp,sysctr-timer";
+				reg = <0x306a0000 0x20000>;
+				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&osc_25m>;
+				clock-names = "per";
+			};
 		};
 
 		bus@30800000 { /* AIPS3 */
-- 
2.7.4


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[PATCH V5 5/5] arm64: dts: imx8mm: Enable cpu-idle driver

[Anson.Huang]

From: Anson Huang <Anson.Huang@nxp.com>

Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states
are supported, details as below:

root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/name
WFI
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/usage
3973
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/name
cpu-sleep-wait
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
6647

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
New patch, as this patch is based on other patches in this series, so I include it.
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 8cf7f34..8f3ed39 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -44,6 +44,20 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		idle-states {
+			entry-method = "psci";
+
+			cpu_sleep_wait: cpu-sleep-wait {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010033>;
+				local-timer-stop;
+				entry-latency-us = <1000>;
+				exit-latency-us = <700>;
+				min-residency-us = <2700>;
+				wakeup-latency-us = <1500>;
+			};
+		};
+
 		A53_0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
@@ -56,6 +70,7 @@
 			nvmem-cells = <&cpu_speed_grade>;
 			nvmem-cell-names = "speed_grade";
 			#cooling-cells = <2>;
+			cpu-idle-states = <&cpu_sleep_wait>;
 		};
 
 		A53_1: cpu@1 {
@@ -68,6 +83,7 @@
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&cpu_sleep_wait>;
 		};
 
 		A53_2: cpu@2 {
@@ -80,6 +96,7 @@
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&cpu_sleep_wait>;
 		};
 
 		A53_3: cpu@3 {
@@ -92,6 +109,7 @@
 			next-level-cache = <&A53_L2>;
 			operating-points-v2 = <&a53_opp_table>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&cpu_sleep_wait>;
 		};
 
 		A53_L2: l2-cache0 {
-- 
2.7.4


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Re: [PATCH V5 2/5] arm64: Enable TIMER_IMX_SYS_CTR for ARCH_MXC platforms

[Shawn Guo]

On Wed, Jul 10, 2019 at 02:30:53PM +0800, Anson.Huang@nxp.com wrote:
> From: Anson Huang <Anson.Huang@nxp.com>
> 
> ARCH_MXC platforms needs system counter as broadcast timer
> to support cpuidle, enable it by default.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

This one is identical to what I just picked up from v4 series, right?

Shawn

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Re: [PATCH V5 3/5] arm64: dts: imx8mm: Add system counter node

[Shawn Guo]

On Wed, Jul 10, 2019 at 02:30:54PM +0800, Anson.Huang@nxp.com wrote:
> From: Anson Huang <Anson.Huang@nxp.com>
> 
> Add i.MX8MM system counter node to enable timer-imx-sysctr
> broadcast timer driver.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Do I need to wait for patch #1 landing before I apply #3 ~ #5, or can
they be applied independently (no breaking on anything)?

Shawn

> ---
> Changes since V4:
> 	- update the clock info using fixed clock node;
> 	- correct the reg range;
> 	- update the interrupt number as the system counter driver ONLY uses 1 irq now.
> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index b5637f8..8cf7f34 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -560,6 +560,14 @@
>  				#pwm-cells = <2>;
>  				status = "disabled";
>  			};
> +
> +			system_counter: timer@306a0000 {
> +				compatible = "nxp,sysctr-timer";
> +				reg = <0x306a0000 0x20000>;
> +				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&osc_24m>;
> +				clock-names = "per";
> +			};
>  		};
>  
>  		aips3: bus@30800000 {
> -- 
> 2.7.4
> 

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RE: [PATCH V5 3/5] arm64: dts: imx8mm: Add system counter node

[Anson Huang]

Hi, Shawn

> On Wed, Jul 10, 2019 at 02:30:54PM +0800, Anson.Huang@nxp.com wrote:
> > From: Anson Huang <Anson.Huang@nxp.com>
> >
> > Add i.MX8MM system counter node to enable timer-imx-sysctr broadcast
> > timer driver.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> 
> Do I need to wait for patch #1 landing before I apply #3 ~ #5, or can they be
> applied independently (no breaking on anything)?

Without #1, system can bootup, but the system counter's freq will be incorrect,
although it does NOT impact normal function. So I think it is better to wait for
#1 landing. @daniel.lezcano@linaro.org, can you help review the #1 patch, since
I use a different way to fix the clock issue which is more simple.

Anson

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RE: [PATCH V5 1/5] clocksource: imx-sysctr: Add internal clock divider handle

[Anson Huang]

Gentle ping...

> From: Anson Huang <Anson.Huang@nxp.com>
> 
> The system counter block guide states that the base clock is internally divided
> by 3 before use, that means the clock input of system counter defined in DT
> should be base clock which is normally from OSC, and then internally divided
> by 3 before use.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> Changes since V4:
> 	- to solve the clock driver probed after system counter driver issue,
> now we can easily switch to
> 	  use fixed clock defined in DT and get its rate, then divided by 3 to
> get real clock rate for
> 	  system counter driver, no need to add "clock-frequency" property in
> DT.
> ---
>  drivers/clocksource/timer-imx-sysctr.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/clocksource/timer-imx-sysctr.c
> b/drivers/clocksource/timer-imx-sysctr.c
> index fd7d680..b7c80a3 100644
> --- a/drivers/clocksource/timer-imx-sysctr.c
> +++ b/drivers/clocksource/timer-imx-sysctr.c
> @@ -20,6 +20,8 @@
>  #define SYS_CTR_EN		0x1
>  #define SYS_CTR_IRQ_MASK	0x2
> 
> +#define SYS_CTR_CLK_DIV		0x3
> +
>  static void __iomem *sys_ctr_base;
>  static u32 cmpcr;
> 
> @@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node
> *np)
>  	if (ret)
>  		return ret;
> 
> +	/* system counter clock is divided by 3 internally */
> +	to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
> +
>  	sys_ctr_base = timer_of_base(&to_sysctr);
>  	cmpcr = readl(sys_ctr_base + CMPCR);
>  	cmpcr &= ~SYS_CTR_EN;
> --
> 2.7.4

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Re: [PATCH V5 1/5] clocksource: imx-sysctr: Add internal clock divider handle

[Daniel Lezcano]

On 06/08/2019 03:55, Anson Huang wrote:
> Gentle ping...

Coming back from vacation. It is in the pipe ... :)

>> From: Anson Huang <Anson.Huang@nxp.com>
>>
>> The system counter block guide states that the base clock is internally divided
>> by 3 before use, that means the clock input of system counter defined in DT
>> should be base clock which is normally from OSC, and then internally divided
>> by 3 before use.
>>
>> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
>> ---
>> Changes since V4:
>> 	- to solve the clock driver probed after system counter driver issue,
>> now we can easily switch to
>> 	  use fixed clock defined in DT and get its rate, then divided by 3 to
>> get real clock rate for
>> 	  system counter driver, no need to add "clock-frequency" property in
>> DT.
>> ---
>>  drivers/clocksource/timer-imx-sysctr.c | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/clocksource/timer-imx-sysctr.c
>> b/drivers/clocksource/timer-imx-sysctr.c
>> index fd7d680..b7c80a3 100644
>> --- a/drivers/clocksource/timer-imx-sysctr.c
>> +++ b/drivers/clocksource/timer-imx-sysctr.c
>> @@ -20,6 +20,8 @@
>>  #define SYS_CTR_EN		0x1
>>  #define SYS_CTR_IRQ_MASK	0x2
>>
>> +#define SYS_CTR_CLK_DIV		0x3
>> +
>>  static void __iomem *sys_ctr_base;
>>  static u32 cmpcr;
>>
>> @@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node
>> *np)
>>  	if (ret)
>>  		return ret;
>>
>> +	/* system counter clock is divided by 3 internally */
>> +	to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
>> +
>>  	sys_ctr_base = timer_of_base(&to_sysctr);
>>  	cmpcr = readl(sys_ctr_base + CMPCR);
>>  	cmpcr &= ~SYS_CTR_EN;
>> --
>> 2.7.4
> 


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Re: [PATCH V5 5/5] arm64: dts: imx8mm: Enable cpu-idle driver

[Daniel Lezcano]

Hi Anson,

sorry for the late review, I've been pretty busy.

If Shawn is ok, I can pick the patches 1-4 in my tree and then this one
after you fix the comments below.

On 10/07/2019 08:30, Anson.Huang@nxp.com wrote:

[ ... ]

> +		idle-states {
> +			entry-method = "psci";
> +
> +			cpu_sleep_wait: cpu-sleep-wait {

Is that a retention state or a powerdown? It is preferable to change the
name to the idle state naming convention given in the PSCI documentation
[1] page 16-17


> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x0010033>;
> +				local-timer-stop;
> +				entry-latency-us = <1000>;
> +				exit-latency-us = <700>;
> +				min-residency-us = <2700>;
> +				wakeup-latency-us = <1500>;

It is pointless to specify the entry + exit *and* the wakeup-latency [2].

Thanks

  -- Daniel

[1]
http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf

[2]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/cpuidle/dt_idle_states.c#n41



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RE: [PATCH V5 5/5] arm64: dts: imx8mm: Enable cpu-idle driver

[Anson Huang]

Hi, Daniel

> Hi Anson,
> 
> sorry for the late review, I've been pretty busy.

That is OK for sure.

> 
> If Shawn is ok, I can pick the patches 1-4 in my tree and then this one after
> you fix the comments below.

Shawn should be OK for it, and he already took patch [PATCH V5 2/5] arm64: Enable TIMER_IMX_SYS_CTR for ARCH_MXC platforms
since I ever sent it before in other series when system counter driver is NOT landing on main line, now it landed, Shawn just apply
that old patch, so in V6 patch I just sent, I did NOT include this patch, you can just apply the 4 patches in V6.

Hi, Shawn
	Daniel will pick this whole patch series, please raise if you have any concern, thanks.

> 
> On 10/07/2019 08:30, Anson.Huang@nxp.com wrote:
> 
> [ ... ]
> 
> > +		idle-states {
> > +			entry-method = "psci";
> > +
> > +			cpu_sleep_wait: cpu-sleep-wait {
> 
> Is that a retention state or a powerdown? It is preferable to change the name
> to the idle state naming convention given in the PSCI documentation [1] page
> 16-17

Thanks for your detail reference, it is a power down state with SoC entering WAIT mode,
so in V6, I change the name to "cpu_pd_wait:cpu-pd-wait".

> 
> 
> > +				compatible = "arm,idle-state";
> > +				arm,psci-suspend-param = <0x0010033>;
> > +				local-timer-stop;
> > +				entry-latency-us = <1000>;
> > +				exit-latency-us = <700>;
> > +				min-residency-us = <2700>;
> > +				wakeup-latency-us = <1500>;
> 
> It is pointless to specify the entry + exit *and* the wakeup-latency [2].

Ah, yes, this is new to me, I will just remove the “wakeup-latency-us” property.

Thanks,
Anson.

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Re: [PATCH V5 5/5] arm64: dts: imx8mm: Enable cpu-idle driver

[Shawn Guo]

On Thu, Aug 15, 2019 at 06:12:50PM +0200, Daniel Lezcano wrote:
> 
> Hi Anson,
> 
> sorry for the late review, I've been pretty busy.
> 
> If Shawn is ok, I can pick the patches 1-4 in my tree and then this one
> after you fix the comments below.

I'm okay, so:

Acked-by: Shawn Guo <shawnguo@kernel.org>

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