From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 15/17] coresight: tmc: Make memory width mask computation into a function
Date: Thu, 29 Aug 2019 14:28:40 -0600 [thread overview]
Message-ID: <20190829202842.580-16-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20190829202842.580-1-mathieu.poirier@linaro.org>
Make the computation of a memory mask representing the width of the memory
bus into a function so that it can be re-used by the ETR driver.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Leo Yan <leo.yan@linaro.org>
---
.../hwtracing/coresight/coresight-tmc-etf.c | 23 ++-------------
drivers/hwtracing/coresight/coresight-tmc.c | 28 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
3 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 23b7ff00af5c..807416b75ecc 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -479,30 +479,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
* traces.
*/
if (!buf->snapshot && to_read > handle->size) {
- u32 mask = 0;
-
- /*
- * The value written to RRP must be byte-address aligned to
- * the width of the trace memory databus _and_ to a frame
- * boundary (16 byte), whichever is the biggest. For example,
- * for 32-bit, 64-bit and 128-bit wide trace memory, the four
- * LSBs must be 0s. For 256-bit wide trace memory, the five
- * LSBs must be 0s.
- */
- switch (drvdata->memwidth) {
- case TMC_MEM_INTF_WIDTH_32BITS:
- case TMC_MEM_INTF_WIDTH_64BITS:
- case TMC_MEM_INTF_WIDTH_128BITS:
- mask = GENMASK(31, 4);
- break;
- case TMC_MEM_INTF_WIDTH_256BITS:
- mask = GENMASK(31, 5);
- break;
- }
+ u32 mask = tmc_get_memwidth_mask(drvdata);
/*
* Make sure the new size is aligned in accordance with the
- * requirement explained above.
+ * requirement explained in function tmc_get_memwidth_mask().
*/
to_read = handle->size & mask;
/* Move the RAM read pointer up */
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 3055bf8e2236..1cf82fa58289 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -70,6 +70,34 @@ void tmc_disable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(0x0, drvdata->base + TMC_CTL);
}
+u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)
+{
+ u32 mask = 0;
+
+ /*
+ * When moving RRP or an offset address forward, the new values must
+ * be byte-address aligned to the width of the trace memory databus
+ * _and_ to a frame boundary (16 byte), whichever is the biggest. For
+ * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four
+ * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must
+ * be 0s.
+ */
+ switch (drvdata->memwidth) {
+ case TMC_MEM_INTF_WIDTH_32BITS:
+ /* fallthrough */
+ case TMC_MEM_INTF_WIDTH_64BITS:
+ /* fallthrough */
+ case TMC_MEM_INTF_WIDTH_128BITS:
+ mask = GENMASK(31, 4);
+ break;
+ case TMC_MEM_INTF_WIDTH_256BITS:
+ mask = GENMASK(31, 5);
+ break;
+ }
+
+ return mask;
+}
+
static int tmc_read_prepare(struct tmc_drvdata *drvdata)
{
int ret = 0;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 9dbcdf453e22..71de978575f3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -255,6 +255,7 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
void tmc_enable_hw(struct tmc_drvdata *drvdata);
void tmc_disable_hw(struct tmc_drvdata *drvdata);
+u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
/* ETB/ETF functions */
int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
--
2.17.1
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next prev parent reply other threads:[~2019-08-29 20:32 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 20:28 [PATCH 00/17] coresight: next v5.3-rc6 Mathieu Poirier
2019-08-29 20:28 ` [PATCH 01/17] coresight: etm4x: Two function calls less Mathieu Poirier
2019-08-29 20:28 ` [PATCH 02/17] coresight: etm4x: Add ETM PIDs for SDM845 and MSM8996 Mathieu Poirier
2019-08-29 20:28 ` [PATCH 03/17] coresight: cpu-debug: Add support for Qualcomm Kryo Mathieu Poirier
2019-08-29 20:28 ` [PATCH 04/17] coresight: etr_buf: Consolidate refcount initialization Mathieu Poirier
2019-08-29 20:28 ` [PATCH 05/17] coresight: tmc-etr: Handle memory errors Mathieu Poirier
2019-08-29 20:28 ` [PATCH 06/17] coresight: tmc-etr: Check if non-secure access is enabled Mathieu Poirier
2019-08-29 20:28 ` [PATCH 07/17] coresight: Convert pr_warn to dev_warn for obsolete bindings Mathieu Poirier
2019-08-29 20:28 ` [PATCH 08/17] coresight: acpi: Static funnel support Mathieu Poirier
2019-08-29 20:28 ` [PATCH 09/17] coresight: etm4x: Remove superfluous setting of os_unlock Mathieu Poirier
2019-08-29 20:28 ` [PATCH 10/17] coresight: etm4x: Use explicit barriers on enable/disable Mathieu Poirier
2019-08-29 20:28 ` [PATCH 11/17] coresight: etm4x: use module_param instead of module_param_named Mathieu Poirier
2019-08-29 20:28 ` [PATCH 12/17] coresight: etm4x: improve clarity of etm4_os_unlock comment Mathieu Poirier
2019-08-29 20:28 ` [PATCH 13/17] coresight: tmc-etr: Fix updating buffer in not-snapshot mode Mathieu Poirier
2019-08-29 20:28 ` [PATCH 14/17] coresight: tmc-etr: Fix perf_data check Mathieu Poirier
2019-08-29 20:28 ` Mathieu Poirier [this message]
2019-08-29 20:28 ` [PATCH 16/17] coresight: tmc-etr: Decouple buffer sync and barrier packet insertion Mathieu Poirier
2019-08-29 20:28 ` [PATCH 17/17] coresight: tmc-etr: Add barrier packets when moving offset forward Mathieu Poirier
2019-09-03 20:02 ` [PATCH 00/17] coresight: next v5.3-rc6 Greg KH
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