* [PATCH 0/3] Fix sdhci-of-esdhc DMA coherency
@ 2019-09-22 10:23 Russell King - ARM Linux admin
2019-09-22 10:27 ` [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent Russell King
0 siblings, 1 reply; 8+ messages in thread
From: Russell King - ARM Linux admin @ 2019-09-22 10:23 UTC (permalink / raw)
To: Robin Murphy, dann frazier, Will Deacon, Nicolin Chen, Y.b. Lu,
Christoph Hellwig
Cc: Mark Rutland, devicetree, Ulf Hansson, linux-mmc, Adrian Hunter,
Li Yang, Rob Herring, Shawn Guo, linux-arm-kernel
Hi,
The following patch set is a result of looking at the ADMA errors
observed on SolidRun's LX2160A board, caused by coherency mismatch
between DT and hardware.
The first patch improves the debugging by dumping the ADMA table
using the DMA address, which can be compared with the DMA address
reported in the register dump. It also prints the interrupt status
that we read, whereas the register dump contains the _cleared_
interrupt status.
The second patch modifies sdhci-of-esdhc to set the DMA snoop bit
depending on whether DT marks the device as coherent or not. With
this patch applied, driver will now set the hardware to match the
contents of DT, rather than always DMA snooping. As explained by
Robin, if the hardware snoops the CPU caches, but the DMA API layer
does not expect this, the hardware can read stale data. The hardware
state and the DMA API must always agree wrt this, for the sake of
data integrity. Mismatch risks substantial filesystem corruption.
The third patch marks the LX2160A esdhc devices as dma-coherent.
Other users of the driver are not touched; I do not have the
information to know whether DMA snooping (coherency) is available
on other SoCs using this driver. However, given the risk of
filesystem corruption, it is important no matter what that the
DMA API layer and the hardware agree - even if it means defaulting
to being non-coherent.
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++
drivers/mmc/host/sdhci-of-esdhc.c | 7 ++++++-
drivers/mmc/host/sdhci.c | 15 ++++++++++-----
3 files changed, 18 insertions(+), 6 deletions(-)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent
2019-09-22 10:23 [PATCH 0/3] Fix sdhci-of-esdhc DMA coherency Russell King - ARM Linux admin
@ 2019-09-22 10:27 ` Russell King
2019-09-23 16:00 ` Li Yang
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Russell King @ 2019-09-22 10:27 UTC (permalink / raw)
To: Robin Murphy, dann frazier, Will Deacon, Nicolin Chen, Y.b. Lu,
Christoph Hellwig
Cc: Mark Rutland, devicetree, Li Yang, Rob Herring, Shawn Guo,
linux-arm-kernel
The LX2160A esdhc controllers are setup by the driver to be DMA
coherent, but without marking them as such in DT, Linux thinks they
are not. This can lead to random sporadic DMA errors, even to the
extent of preventing boot, such as:
mmc0: ADMA error
mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00002202
mmc0: sdhci: Blk size: 0x00000008 | Blk cnt: 0x00000001
mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013
mmc0: sdhci: Present: 0x01f50008 | Host ctl: 0x00000038
mmc0: sdhci: Power: 0x00000003 | Blk gap: 0x00000000
mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x000040d8
mmc0: sdhci: Timeout: 0x00000003 | Int stat: 0x00000001
mmc0: sdhci: Int enab: 0x037f108f | Sig enab: 0x037f108b
mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00002202
mmc0: sdhci: Caps: 0x35fa0000 | Caps_1: 0x0000af00
mmc0: sdhci: Cmd: 0x0000333a | Max curr: 0x00000000
mmc0: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x001d8a33
mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x3f400e00
mmc0: sdhci: Host ctl2: 0x00000000
mmc0: sdhci: ADMA Err: 0x00000009 | ADMA Ptr: 0x000000236d43820c
mmc0: sdhci: ============================================
mmc0: error -5 whilst initialising SD card
These are caused by the device's descriptor fetch hitting speculatively
loaded CPU cache lines that the CPU does not see through the normal,
non-cacheable DMA coherent mapping that it uses for non-coherent
devices.
DT and the device must agree wrt whether the device is DMA coherent or
not.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 36b153e3da47..508af23edef0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -593,6 +593,7 @@
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <0 28 0x4>; /* Level high type */
clocks = <&clockgen 4 1>;
+ dma-coherent;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
@@ -605,6 +606,7 @@
reg = <0x0 0x2150000 0x0 0x10000>;
interrupts = <0 63 0x4>; /* Level high type */
clocks = <&clockgen 4 1>;
+ dma-coherent;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
broken-cd;
--
2.7.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent
2019-09-22 10:27 ` [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent Russell King
@ 2019-09-23 16:00 ` Li Yang
2019-09-23 21:26 ` Ulf Hansson
2019-10-07 12:42 ` Shawn Guo
2 siblings, 0 replies; 8+ messages in thread
From: Li Yang @ 2019-09-23 16:00 UTC (permalink / raw)
To: Russell King
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
dann frazier, Will Deacon, Nicolin Chen, Rob Herring, Y.b. Lu,
Shawn Guo, Robin Murphy, Christoph Hellwig,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Sun, Sep 22, 2019 at 2:26 PM Russell King <rmk+kernel@armlinux.org.uk> wrote:
>
> The LX2160A esdhc controllers are setup by the driver to be DMA
> coherent, but without marking them as such in DT, Linux thinks they
> are not. This can lead to random sporadic DMA errors, even to the
> extent of preventing boot, such as:
>
> mmc0: ADMA error
> mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
> mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00002202
> mmc0: sdhci: Blk size: 0x00000008 | Blk cnt: 0x00000001
> mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013
> mmc0: sdhci: Present: 0x01f50008 | Host ctl: 0x00000038
> mmc0: sdhci: Power: 0x00000003 | Blk gap: 0x00000000
> mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x000040d8
> mmc0: sdhci: Timeout: 0x00000003 | Int stat: 0x00000001
> mmc0: sdhci: Int enab: 0x037f108f | Sig enab: 0x037f108b
> mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00002202
> mmc0: sdhci: Caps: 0x35fa0000 | Caps_1: 0x0000af00
> mmc0: sdhci: Cmd: 0x0000333a | Max curr: 0x00000000
> mmc0: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x001d8a33
> mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x3f400e00
> mmc0: sdhci: Host ctl2: 0x00000000
> mmc0: sdhci: ADMA Err: 0x00000009 | ADMA Ptr: 0x000000236d43820c
> mmc0: sdhci: ============================================
> mmc0: error -5 whilst initialising SD card
>
> These are caused by the device's descriptor fetch hitting speculatively
> loaded CPU cache lines that the CPU does not see through the normal,
> non-cacheable DMA coherent mapping that it uses for non-coherent
> devices.
>
> DT and the device must agree wrt whether the device is DMA coherent or
> not.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Li Yang <leoyang.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 36b153e3da47..508af23edef0 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -593,6 +593,7 @@
> reg = <0x0 0x2140000 0x0 0x10000>;
> interrupts = <0 28 0x4>; /* Level high type */
> clocks = <&clockgen 4 1>;
> + dma-coherent;
> voltage-ranges = <1800 1800 3300 3300>;
> sdhci,auto-cmd12;
> little-endian;
> @@ -605,6 +606,7 @@
> reg = <0x0 0x2150000 0x0 0x10000>;
> interrupts = <0 63 0x4>; /* Level high type */
> clocks = <&clockgen 4 1>;
> + dma-coherent;
> voltage-ranges = <1800 1800 3300 3300>;
> sdhci,auto-cmd12;
> broken-cd;
> --
> 2.7.4
>
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent
2019-09-22 10:27 ` [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent Russell King
2019-09-23 16:00 ` Li Yang
@ 2019-09-23 21:26 ` Ulf Hansson
2019-09-24 3:41 ` Leo Li
2019-10-07 12:42 ` Shawn Guo
2 siblings, 1 reply; 8+ messages in thread
From: Ulf Hansson @ 2019-09-23 21:26 UTC (permalink / raw)
To: Russell King
Cc: Mark Rutland, DTML, dann frazier, Will Deacon, Li Yang,
Nicolin Chen, Rob Herring, Y.b. Lu, Shawn Guo, Robin Murphy,
Christoph Hellwig, Linux ARM
On Sun, 22 Sep 2019 at 12:29, Russell King <rmk+kernel@armlinux.org.uk> wrote:
>
> The LX2160A esdhc controllers are setup by the driver to be DMA
> coherent, but without marking them as such in DT, Linux thinks they
> are not. This can lead to random sporadic DMA errors, even to the
> extent of preventing boot, such as:
>
> mmc0: ADMA error
> mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
> mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00002202
> mmc0: sdhci: Blk size: 0x00000008 | Blk cnt: 0x00000001
> mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013
> mmc0: sdhci: Present: 0x01f50008 | Host ctl: 0x00000038
> mmc0: sdhci: Power: 0x00000003 | Blk gap: 0x00000000
> mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x000040d8
> mmc0: sdhci: Timeout: 0x00000003 | Int stat: 0x00000001
> mmc0: sdhci: Int enab: 0x037f108f | Sig enab: 0x037f108b
> mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00002202
> mmc0: sdhci: Caps: 0x35fa0000 | Caps_1: 0x0000af00
> mmc0: sdhci: Cmd: 0x0000333a | Max curr: 0x00000000
> mmc0: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x001d8a33
> mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x3f400e00
> mmc0: sdhci: Host ctl2: 0x00000000
> mmc0: sdhci: ADMA Err: 0x00000009 | ADMA Ptr: 0x000000236d43820c
> mmc0: sdhci: ============================================
> mmc0: error -5 whilst initialising SD card
>
> These are caused by the device's descriptor fetch hitting speculatively
> loaded CPU cache lines that the CPU does not see through the normal,
> non-cacheable DMA coherent mapping that it uses for non-coherent
> devices.
>
> DT and the device must agree wrt whether the device is DMA coherent or
> not.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
As I am picking up patch1 and patch2 from this series, I can also help
out and pick up this one, if that is okay by people?
Kind regards
Uffe
> ---
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 36b153e3da47..508af23edef0 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -593,6 +593,7 @@
> reg = <0x0 0x2140000 0x0 0x10000>;
> interrupts = <0 28 0x4>; /* Level high type */
> clocks = <&clockgen 4 1>;
> + dma-coherent;
> voltage-ranges = <1800 1800 3300 3300>;
> sdhci,auto-cmd12;
> little-endian;
> @@ -605,6 +606,7 @@
> reg = <0x0 0x2150000 0x0 0x10000>;
> interrupts = <0 63 0x4>; /* Level high type */
> clocks = <&clockgen 4 1>;
> + dma-coherent;
> voltage-ranges = <1800 1800 3300 3300>;
> sdhci,auto-cmd12;
> broken-cd;
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent
2019-09-23 21:26 ` Ulf Hansson
@ 2019-09-24 3:41 ` Leo Li
2019-09-24 18:04 ` Robin Murphy
0 siblings, 1 reply; 8+ messages in thread
From: Leo Li @ 2019-09-24 3:41 UTC (permalink / raw)
To: Ulf Hansson, Russell King
Cc: Mark Rutland, DTML, dann frazier, Will Deacon, Nicolin Chen,
Rob Herring, Y.b. Lu, Shawn Guo, Robin Murphy, Christoph Hellwig,
Linux ARM
> -----Original Message-----
> From: Ulf Hansson <ulf.hansson@linaro.org>
> Sent: Monday, September 23, 2019 4:27 PM
> To: Russell King <rmk+kernel@armlinux.org.uk>
> Cc: Robin Murphy <robin.murphy@arm.com>; dann frazier
> <dann.frazier@canonical.com>; Will Deacon <will.deacon@arm.com>;
> Nicolin Chen <nicoleotsuka@gmail.com>; Y.b. Lu <yangbo.lu@nxp.com>;
> Christoph Hellwig <hch@lst.de>; Mark Rutland <mark.rutland@arm.com>;
> DTML <devicetree@vger.kernel.org>; Leo Li <leoyang.li@nxp.com>; Rob
> Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Linux
> ARM <linux-arm-kernel@lists.infradead.org>
> Subject: Re: [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma
> coherent
>
> On Sun, 22 Sep 2019 at 12:29, Russell King <rmk+kernel@armlinux.org.uk>
> wrote:
> >
> > The LX2160A esdhc controllers are setup by the driver to be DMA
> > coherent, but without marking them as such in DT, Linux thinks they
> > are not. This can lead to random sporadic DMA errors, even to the
> > extent of preventing boot, such as:
> >
> > mmc0: ADMA error
> > mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
> > mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00002202
> > mmc0: sdhci: Blk size: 0x00000008 | Blk cnt: 0x00000001
> > mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013
> > mmc0: sdhci: Present: 0x01f50008 | Host ctl: 0x00000038
> > mmc0: sdhci: Power: 0x00000003 | Blk gap: 0x00000000
> > mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x000040d8
> > mmc0: sdhci: Timeout: 0x00000003 | Int stat: 0x00000001
> > mmc0: sdhci: Int enab: 0x037f108f | Sig enab: 0x037f108b
> > mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00002202
> > mmc0: sdhci: Caps: 0x35fa0000 | Caps_1: 0x0000af00
> > mmc0: sdhci: Cmd: 0x0000333a | Max curr: 0x00000000
> > mmc0: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x001d8a33
> > mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x3f400e00
> > mmc0: sdhci: Host ctl2: 0x00000000
> > mmc0: sdhci: ADMA Err: 0x00000009 | ADMA Ptr: 0x000000236d43820c
> > mmc0: sdhci: ============================================
> > mmc0: error -5 whilst initialising SD card
> >
> > These are caused by the device's descriptor fetch hitting
> > speculatively loaded CPU cache lines that the CPU does not see through
> > the normal, non-cacheable DMA coherent mapping that it uses for
> > non-coherent devices.
> >
> > DT and the device must agree wrt whether the device is DMA coherent or
> > not.
> >
> > Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
>
> As I am picking up patch1 and patch2 from this series, I can also help out and
> pick up this one, if that is okay by people?
There is some concern recently from linux-next maintainer about this causing potential conflicts. https://lkml.org/lkml/2019/9/15/225
Regards,
Leo
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent
2019-09-24 3:41 ` Leo Li
@ 2019-09-24 18:04 ` Robin Murphy
2019-09-27 18:35 ` Ulf Hansson
0 siblings, 1 reply; 8+ messages in thread
From: Robin Murphy @ 2019-09-24 18:04 UTC (permalink / raw)
To: Leo Li, Ulf Hansson, Russell King
Cc: Mark Rutland, DTML, dann frazier, Will Deacon, Nicolin Chen,
Rob Herring, Y.b. Lu, Shawn Guo, Christoph Hellwig, Linux ARM
On 24/09/2019 04:41, Leo Li wrote:
>
>
>> -----Original Message-----
>> From: Ulf Hansson <ulf.hansson@linaro.org>
>> Sent: Monday, September 23, 2019 4:27 PM
>> To: Russell King <rmk+kernel@armlinux.org.uk>
>> Cc: Robin Murphy <robin.murphy@arm.com>; dann frazier
>> <dann.frazier@canonical.com>; Will Deacon <will.deacon@arm.com>;
>> Nicolin Chen <nicoleotsuka@gmail.com>; Y.b. Lu <yangbo.lu@nxp.com>;
>> Christoph Hellwig <hch@lst.de>; Mark Rutland <mark.rutland@arm.com>;
>> DTML <devicetree@vger.kernel.org>; Leo Li <leoyang.li@nxp.com>; Rob
>> Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Linux
>> ARM <linux-arm-kernel@lists.infradead.org>
>> Subject: Re: [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma
>> coherent
>>
>> On Sun, 22 Sep 2019 at 12:29, Russell King <rmk+kernel@armlinux.org.uk>
>> wrote:
>>>
>>> The LX2160A esdhc controllers are setup by the driver to be DMA
>>> coherent, but without marking them as such in DT, Linux thinks they
>>> are not. This can lead to random sporadic DMA errors, even to the
>>> extent of preventing boot, such as:
>>>
>>> mmc0: ADMA error
>>> mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
>>> mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00002202
>>> mmc0: sdhci: Blk size: 0x00000008 | Blk cnt: 0x00000001
>>> mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013
>>> mmc0: sdhci: Present: 0x01f50008 | Host ctl: 0x00000038
>>> mmc0: sdhci: Power: 0x00000003 | Blk gap: 0x00000000
>>> mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x000040d8
>>> mmc0: sdhci: Timeout: 0x00000003 | Int stat: 0x00000001
>>> mmc0: sdhci: Int enab: 0x037f108f | Sig enab: 0x037f108b
>>> mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00002202
>>> mmc0: sdhci: Caps: 0x35fa0000 | Caps_1: 0x0000af00
>>> mmc0: sdhci: Cmd: 0x0000333a | Max curr: 0x00000000
>>> mmc0: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x001d8a33
>>> mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x3f400e00
>>> mmc0: sdhci: Host ctl2: 0x00000000
>>> mmc0: sdhci: ADMA Err: 0x00000009 | ADMA Ptr: 0x000000236d43820c
>>> mmc0: sdhci: ============================================
>>> mmc0: error -5 whilst initialising SD card
>>>
>>> These are caused by the device's descriptor fetch hitting
>>> speculatively loaded CPU cache lines that the CPU does not see through
>>> the normal, non-cacheable DMA coherent mapping that it uses for
>>> non-coherent devices.
>>>
>>> DT and the device must agree wrt whether the device is DMA coherent or
>>> not.
>>>
>>> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
>>
>> As I am picking up patch1 and patch2 from this series, I can also help out and
>> pick up this one, if that is okay by people?
>
> There is some concern recently from linux-next maintainer about this causing potential conflicts. https://lkml.org/lkml/2019/9/15/225
In principle, it should be fine for #2 and #3 to go via separate trees -
#3 aligns the DT with the existing behaviour of the driver, while #2
will make the driver behave correctly whichever state the DT is in.
Robin.
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent
2019-09-24 18:04 ` Robin Murphy
@ 2019-09-27 18:35 ` Ulf Hansson
0 siblings, 0 replies; 8+ messages in thread
From: Ulf Hansson @ 2019-09-27 18:35 UTC (permalink / raw)
To: Robin Murphy
Cc: Mark Rutland, DTML, dann frazier, Will Deacon, Leo Li,
Nicolin Chen, Russell King, Rob Herring, Y.b. Lu, Shawn Guo,
Christoph Hellwig, Linux ARM
On Tue, 24 Sep 2019 at 20:04, Robin Murphy <robin.murphy@arm.com> wrote:
>
> On 24/09/2019 04:41, Leo Li wrote:
> >
> >
> >> -----Original Message-----
> >> From: Ulf Hansson <ulf.hansson@linaro.org>
> >> Sent: Monday, September 23, 2019 4:27 PM
> >> To: Russell King <rmk+kernel@armlinux.org.uk>
> >> Cc: Robin Murphy <robin.murphy@arm.com>; dann frazier
> >> <dann.frazier@canonical.com>; Will Deacon <will.deacon@arm.com>;
> >> Nicolin Chen <nicoleotsuka@gmail.com>; Y.b. Lu <yangbo.lu@nxp.com>;
> >> Christoph Hellwig <hch@lst.de>; Mark Rutland <mark.rutland@arm.com>;
> >> DTML <devicetree@vger.kernel.org>; Leo Li <leoyang.li@nxp.com>; Rob
> >> Herring <robh+dt@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Linux
> >> ARM <linux-arm-kernel@lists.infradead.org>
> >> Subject: Re: [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma
> >> coherent
> >>
> >> On Sun, 22 Sep 2019 at 12:29, Russell King <rmk+kernel@armlinux.org.uk>
> >> wrote:
> >>>
> >>> The LX2160A esdhc controllers are setup by the driver to be DMA
> >>> coherent, but without marking them as such in DT, Linux thinks they
> >>> are not. This can lead to random sporadic DMA errors, even to the
> >>> extent of preventing boot, such as:
> >>>
> >>> mmc0: ADMA error
> >>> mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
> >>> mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00002202
> >>> mmc0: sdhci: Blk size: 0x00000008 | Blk cnt: 0x00000001
> >>> mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013
> >>> mmc0: sdhci: Present: 0x01f50008 | Host ctl: 0x00000038
> >>> mmc0: sdhci: Power: 0x00000003 | Blk gap: 0x00000000
> >>> mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x000040d8
> >>> mmc0: sdhci: Timeout: 0x00000003 | Int stat: 0x00000001
> >>> mmc0: sdhci: Int enab: 0x037f108f | Sig enab: 0x037f108b
> >>> mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00002202
> >>> mmc0: sdhci: Caps: 0x35fa0000 | Caps_1: 0x0000af00
> >>> mmc0: sdhci: Cmd: 0x0000333a | Max curr: 0x00000000
> >>> mmc0: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x001d8a33
> >>> mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x3f400e00
> >>> mmc0: sdhci: Host ctl2: 0x00000000
> >>> mmc0: sdhci: ADMA Err: 0x00000009 | ADMA Ptr: 0x000000236d43820c
> >>> mmc0: sdhci: ============================================
> >>> mmc0: error -5 whilst initialising SD card
> >>>
> >>> These are caused by the device's descriptor fetch hitting
> >>> speculatively loaded CPU cache lines that the CPU does not see through
> >>> the normal, non-cacheable DMA coherent mapping that it uses for
> >>> non-coherent devices.
> >>>
> >>> DT and the device must agree wrt whether the device is DMA coherent or
> >>> not.
> >>>
> >>> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> >>
> >> As I am picking up patch1 and patch2 from this series, I can also help out and
> >> pick up this one, if that is okay by people?
> >
> > There is some concern recently from linux-next maintainer about this causing potential conflicts. https://lkml.org/lkml/2019/9/15/225
>
> In principle, it should be fine for #2 and #3 to go via separate trees -
> #3 aligns the DT with the existing behaviour of the driver, while #2
> will make the driver behave correctly whichever state the DT is in.
>
> Robin.
That's right, so I am leaving this patch for arm-soc people to pick up then.
Kind regards
Uffe
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent
2019-09-22 10:27 ` [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent Russell King
2019-09-23 16:00 ` Li Yang
2019-09-23 21:26 ` Ulf Hansson
@ 2019-10-07 12:42 ` Shawn Guo
2 siblings, 0 replies; 8+ messages in thread
From: Shawn Guo @ 2019-10-07 12:42 UTC (permalink / raw)
To: Russell King
Cc: Mark Rutland, devicetree, dann frazier, Will Deacon, Li Yang,
Nicolin Chen, Rob Herring, Y.b. Lu, Robin Murphy,
Christoph Hellwig, linux-arm-kernel
On Sun, Sep 22, 2019 at 11:27:03AM +0100, Russell King wrote:
> The LX2160A esdhc controllers are setup by the driver to be DMA
> coherent, but without marking them as such in DT, Linux thinks they
> are not. This can lead to random sporadic DMA errors, even to the
> extent of preventing boot, such as:
>
> mmc0: ADMA error
> mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
> mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00002202
> mmc0: sdhci: Blk size: 0x00000008 | Blk cnt: 0x00000001
> mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013
> mmc0: sdhci: Present: 0x01f50008 | Host ctl: 0x00000038
> mmc0: sdhci: Power: 0x00000003 | Blk gap: 0x00000000
> mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x000040d8
> mmc0: sdhci: Timeout: 0x00000003 | Int stat: 0x00000001
> mmc0: sdhci: Int enab: 0x037f108f | Sig enab: 0x037f108b
> mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00002202
> mmc0: sdhci: Caps: 0x35fa0000 | Caps_1: 0x0000af00
> mmc0: sdhci: Cmd: 0x0000333a | Max curr: 0x00000000
> mmc0: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x001d8a33
> mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x3f400e00
> mmc0: sdhci: Host ctl2: 0x00000000
> mmc0: sdhci: ADMA Err: 0x00000009 | ADMA Ptr: 0x000000236d43820c
> mmc0: sdhci: ============================================
> mmc0: error -5 whilst initialising SD card
>
> These are caused by the device's descriptor fetch hitting speculatively
> loaded CPU cache lines that the CPU does not see through the normal,
> non-cacheable DMA coherent mapping that it uses for non-coherent
> devices.
>
> DT and the device must agree wrt whether the device is DMA coherent or
> not.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Applied, thanks.
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-10-07 12:42 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-22 10:23 [PATCH 0/3] Fix sdhci-of-esdhc DMA coherency Russell King - ARM Linux admin
2019-09-22 10:27 ` [PATCH 3/3] arm64: dts: mark lx2160a esdhc controllers dma coherent Russell King
2019-09-23 16:00 ` Li Yang
2019-09-23 21:26 ` Ulf Hansson
2019-09-24 3:41 ` Leo Li
2019-09-24 18:04 ` Robin Murphy
2019-09-27 18:35 ` Ulf Hansson
2019-10-07 12:42 ` Shawn Guo
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