* Regression: Cortex-M w/ XIP not booting @ 2019-10-02 6:16 afzal mohammed 2019-10-02 11:55 ` Vladimir Murzin 0 siblings, 1 reply; 4+ messages in thread From: afzal mohammed @ 2019-10-02 6:16 UTC (permalink / raw) To: Vladimir Murzin, Russell King Cc: Maxime Coquelin, linux-arm-kernel, Alexandre Torgue Hi Vladimir, After, 72cd4064fcca "NOMMU: Toggle only bits in EXC_RETURN we are really care of", the no-MMU Vybrid Cortex-M4 is not booting, relevant logs at the end. Looks like any Cortex-M with XIP enabled Kernel would have this issue, i.e. all STM32 Cortex-M baords (STM32 maintainers CC'ed) as well as. In the above commit, lr value is saved in data section in __v7m_setup, but the data section is setup only later in __mmap_switched on an XIP kernel, where it will overwrite the saved value of lr. This causes reserved EXC_RETURN value resulting in the below. Reverting the above change fixes the issue. Regards afzal [ 0.801928] Run /init as init process [ 0.829364] [ 0.829364] Unhandled exception: IPSR = 00000006 LR = fffffff1 [ 0.836750] CPU: 0 PID: 1 Comm: init Not tainted 5.2.0-00002-gb5fa138a4b0d-dirty #41 [ 0.844523] Hardware name: Freescale Vybrid VF5xx/VF6xx (Device Tree) [ 0.851001] PC is at 0x0 [ 0.853559] LR is at 0x0 [ 0.856127] pc : [<00000000>] lr : [<00000000>] psr: 4000000b [ 0.862434] sp : 8e82dff8 ip : 8e82dfe0 fp : 00000000 [ 0.867697] r10: 8eb4ae40 r9 : 00000000 r8 : 00000000 [ 0.872958] r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000 [ 0.879523] r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 00000000 [ 0.886076] xPSR: 4000000b [ 0.888836] CPU: 0 PID: 1 Comm: init Not tainted 5.2.0-00002-gb5fa138a4b0d-dirty #41 [ 0.896612] Hardware name: Freescale Vybrid VF5xx/VF6xx (Device Tree) [ 0.903177] [<0f0042d5>] (unwind_backtrace) from [<0f00354f>] (show_stack+0xb/0xc) [ 0.910851] [<0f00354f>] (show_stack) from [<0f003d0f>] (__invalid_entry+0x4b/0x4c) _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Regression: Cortex-M w/ XIP not booting 2019-10-02 6:16 Regression: Cortex-M w/ XIP not booting afzal mohammed @ 2019-10-02 11:55 ` Vladimir Murzin 2019-10-03 0:04 ` afzal mohammed 0 siblings, 1 reply; 4+ messages in thread From: Vladimir Murzin @ 2019-10-02 11:55 UTC (permalink / raw) To: afzal mohammed, Russell King Cc: Maxime Coquelin, linux-arm-kernel, Alexandre Torgue Hi Afzal, On 10/2/19 7:16 AM, afzal mohammed wrote: > Hi Vladimir, > > After, > > 72cd4064fcca "NOMMU: Toggle only bits in EXC_RETURN we are really care of", > > the no-MMU Vybrid Cortex-M4 is not booting, relevant logs at the end. > > Looks like any Cortex-M with XIP enabled Kernel would have this issue, > i.e. all STM32 Cortex-M baords (STM32 maintainers CC'ed) as well as. > > In the above commit, lr value is saved in data section in __v7m_setup, > but the data section is setup only later in __mmap_switched on an XIP > kernel, where it will overwrite the saved value of lr. This causes > reserved EXC_RETURN value resulting in the below. > > Reverting the above change fixes the issue. Thanks for report! It is pity it was not caught while patch submission... Can you try diff bellow? I do not have XIP target, but non-XIP seems to stay happy... diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index a7810be..4a39828 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -68,7 +68,7 @@ ENDPROC(__vet_atags) * The following fragment of code is executed with the MMU on in MMU mode, * and uses absolute addresses; this is not position independent. * - * r0 = cp#15 control register + * r0 = cp#15 control register (exc_ret for M-class) * r1 = machine ID * r2 = atags/dtb pointer * r9 = processor ID @@ -137,7 +137,8 @@ __mmap_switched_data: #ifdef CONFIG_CPU_CP15 .long cr_alignment @ r3 #else - .long 0 @ r3 +M_CLASS(.long exc_ret) @ r3 +AR_CLASS(.long 0) @ r3 #endif .size __mmap_switched_data, . - __mmap_switched_data diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index afa350f..0fc814b 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -201,6 +201,8 @@ M_CLASS(streq r3, [r12, #PMSAv8_MAIR1]) bic r0, r0, #V7M_SCB_CCR_IC #endif str r0, [r12, V7M_SCB_CCR] + /* Pass exc_ret to __mmap_switched */ + mov r0, r10 #endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */ ret lr ENDPROC(__after_proc_init) diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 1448f14..efebf41 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -136,9 +136,8 @@ __v7m_setup_cont: cpsie i svc #0 1: cpsid i - ldr r0, =exc_ret - orr lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK - str lr, [r0] + /* Calculate exc_ret */ + orr r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK ldmia sp, {r0-r3, r12} str r5, [r12, #11 * 4] @ restore the original SVC vector entry mov lr, r6 @ restore LR Cheers Vladimir _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: Regression: Cortex-M w/ XIP not booting 2019-10-02 11:55 ` Vladimir Murzin @ 2019-10-03 0:04 ` afzal mohammed 2019-10-03 11:43 ` Vladimir Murzin 0 siblings, 1 reply; 4+ messages in thread From: afzal mohammed @ 2019-10-03 0:04 UTC (permalink / raw) To: Vladimir Murzin Cc: Maxime Coquelin, Russell King, linux-arm-kernel, Alexandre Torgue Hi Vladimir, On Wed, Oct 02, 2019 at 12:55:55PM +0100, Vladimir Murzin wrote: > Can you try diff bellow? I do not have XIP target, but non-XIP seems to > stay happy... Thanks, it fixes the issue. Regards afzal > > > diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S > index a7810be..4a39828 100644 > --- a/arch/arm/kernel/head-common.S > +++ b/arch/arm/kernel/head-common.S > @@ -68,7 +68,7 @@ ENDPROC(__vet_atags) > * The following fragment of code is executed with the MMU on in MMU mode, > * and uses absolute addresses; this is not position independent. > * > - * r0 = cp#15 control register > + * r0 = cp#15 control register (exc_ret for M-class) > * r1 = machine ID > * r2 = atags/dtb pointer > * r9 = processor ID > @@ -137,7 +137,8 @@ __mmap_switched_data: > #ifdef CONFIG_CPU_CP15 > .long cr_alignment @ r3 > #else > - .long 0 @ r3 > +M_CLASS(.long exc_ret) @ r3 > +AR_CLASS(.long 0) @ r3 > #endif > .size __mmap_switched_data, . - __mmap_switched_data > > diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S > index afa350f..0fc814b 100644 > --- a/arch/arm/kernel/head-nommu.S > +++ b/arch/arm/kernel/head-nommu.S > @@ -201,6 +201,8 @@ M_CLASS(streq r3, [r12, #PMSAv8_MAIR1]) > bic r0, r0, #V7M_SCB_CCR_IC > #endif > str r0, [r12, V7M_SCB_CCR] > + /* Pass exc_ret to __mmap_switched */ > + mov r0, r10 > #endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */ > ret lr > ENDPROC(__after_proc_init) > diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S > index 1448f14..efebf41 100644 > --- a/arch/arm/mm/proc-v7m.S > +++ b/arch/arm/mm/proc-v7m.S > @@ -136,9 +136,8 @@ __v7m_setup_cont: > cpsie i > svc #0 > 1: cpsid i > - ldr r0, =exc_ret > - orr lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK > - str lr, [r0] > + /* Calculate exc_ret */ > + orr r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK > ldmia sp, {r0-r3, r12} > str r5, [r12, #11 * 4] @ restore the original SVC vector entry > mov lr, r6 @ restore LR > > Cheers > Vladimir _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Regression: Cortex-M w/ XIP not booting 2019-10-03 0:04 ` afzal mohammed @ 2019-10-03 11:43 ` Vladimir Murzin 0 siblings, 0 replies; 4+ messages in thread From: Vladimir Murzin @ 2019-10-03 11:43 UTC (permalink / raw) To: afzal mohammed Cc: Maxime Coquelin, Russell King, linux-arm-kernel, Alexandre Torgue Hi Afzal, On 10/3/19 1:04 AM, afzal mohammed wrote: > Hi Vladimir, > > On Wed, Oct 02, 2019 at 12:55:55PM +0100, Vladimir Murzin wrote: > >> Can you try diff bellow? I do not have XIP target, but non-XIP seems to >> stay happy... > > Thanks, it fixes the issue. Great thanks! I've just sent it as a proper patch. Vladimir > > Regards > afzal > >> >> >> diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S >> index a7810be..4a39828 100644 >> --- a/arch/arm/kernel/head-common.S >> +++ b/arch/arm/kernel/head-common.S >> @@ -68,7 +68,7 @@ ENDPROC(__vet_atags) >> * The following fragment of code is executed with the MMU on in MMU mode, >> * and uses absolute addresses; this is not position independent. >> * >> - * r0 = cp#15 control register >> + * r0 = cp#15 control register (exc_ret for M-class) >> * r1 = machine ID >> * r2 = atags/dtb pointer >> * r9 = processor ID >> @@ -137,7 +137,8 @@ __mmap_switched_data: >> #ifdef CONFIG_CPU_CP15 >> .long cr_alignment @ r3 >> #else >> - .long 0 @ r3 >> +M_CLASS(.long exc_ret) @ r3 >> +AR_CLASS(.long 0) @ r3 >> #endif >> .size __mmap_switched_data, . - __mmap_switched_data >> >> diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S >> index afa350f..0fc814b 100644 >> --- a/arch/arm/kernel/head-nommu.S >> +++ b/arch/arm/kernel/head-nommu.S >> @@ -201,6 +201,8 @@ M_CLASS(streq r3, [r12, #PMSAv8_MAIR1]) >> bic r0, r0, #V7M_SCB_CCR_IC >> #endif >> str r0, [r12, V7M_SCB_CCR] >> + /* Pass exc_ret to __mmap_switched */ >> + mov r0, r10 >> #endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */ >> ret lr >> ENDPROC(__after_proc_init) >> diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S >> index 1448f14..efebf41 100644 >> --- a/arch/arm/mm/proc-v7m.S >> +++ b/arch/arm/mm/proc-v7m.S >> @@ -136,9 +136,8 @@ __v7m_setup_cont: >> cpsie i >> svc #0 >> 1: cpsid i >> - ldr r0, =exc_ret >> - orr lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK >> - str lr, [r0] >> + /* Calculate exc_ret */ >> + orr r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK >> ldmia sp, {r0-r3, r12} >> str r5, [r12, #11 * 4] @ restore the original SVC vector entry >> mov lr, r6 @ restore LR >> >> Cheers >> Vladimir > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-10-03 11:43 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-10-02 6:16 Regression: Cortex-M w/ XIP not booting afzal mohammed 2019-10-02 11:55 ` Vladimir Murzin 2019-10-03 0:04 ` afzal mohammed 2019-10-03 11:43 ` Vladimir Murzin
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