From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Marc Zyngier <marc.zyngier@arm.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Will Deacon <will@kernel.org>,
stable@vger.kernel.org,
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [PATCH 4.19 103/114] arm64: Force SSBS on context switch
Date: Thu, 10 Oct 2019 10:36:50 +0200 [thread overview]
Message-ID: <20191010083613.664531794@linuxfoundation.org> (raw)
In-Reply-To: <20191010083544.711104709@linuxfoundation.org>
From: Marc Zyngier <marc.zyngier@arm.com>
[ Upstream commit cbdf8a189a66001c36007bf0f5c975d0376c5c3a ]
On a CPU that doesn't support SSBS, PSTATE[12] is RES0. In a system
where only some of the CPUs implement SSBS, we end-up losing track of
the SSBS bit across task migration.
To address this issue, let's force the SSBS bit on context switch.
Fixes: 8f04e8e6e29c ("arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3")
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[will: inverted logic and added comments]
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/arm64/include/asm/processor.h | 14 ++++++++++++--
arch/arm64/kernel/process.c | 29 ++++++++++++++++++++++++++++-
2 files changed, 40 insertions(+), 3 deletions(-)
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -177,6 +177,16 @@ static inline void start_thread_common(s
regs->pc = pc;
}
+static inline void set_ssbs_bit(struct pt_regs *regs)
+{
+ regs->pstate |= PSR_SSBS_BIT;
+}
+
+static inline void set_compat_ssbs_bit(struct pt_regs *regs)
+{
+ regs->pstate |= PSR_AA32_SSBS_BIT;
+}
+
static inline void start_thread(struct pt_regs *regs, unsigned long pc,
unsigned long sp)
{
@@ -184,7 +194,7 @@ static inline void start_thread(struct p
regs->pstate = PSR_MODE_EL0t;
if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
- regs->pstate |= PSR_SSBS_BIT;
+ set_ssbs_bit(regs);
regs->sp = sp;
}
@@ -203,7 +213,7 @@ static inline void compat_start_thread(s
#endif
if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE)
- regs->pstate |= PSR_AA32_SSBS_BIT;
+ set_compat_ssbs_bit(regs);
regs->compat_sp = sp;
}
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -360,7 +360,7 @@ int copy_thread(unsigned long clone_flag
childregs->pstate |= PSR_UAO_BIT;
if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE)
- childregs->pstate |= PSR_SSBS_BIT;
+ set_ssbs_bit(childregs);
p->thread.cpu_context.x19 = stack_start;
p->thread.cpu_context.x20 = stk_sz;
@@ -402,6 +402,32 @@ void uao_thread_switch(struct task_struc
}
/*
+ * Force SSBS state on context-switch, since it may be lost after migrating
+ * from a CPU which treats the bit as RES0 in a heterogeneous system.
+ */
+static void ssbs_thread_switch(struct task_struct *next)
+{
+ struct pt_regs *regs = task_pt_regs(next);
+
+ /*
+ * Nothing to do for kernel threads, but 'regs' may be junk
+ * (e.g. idle task) so check the flags and bail early.
+ */
+ if (unlikely(next->flags & PF_KTHREAD))
+ return;
+
+ /* If the mitigation is enabled, then we leave SSBS clear. */
+ if ((arm64_get_ssbd_state() == ARM64_SSBD_FORCE_ENABLE) ||
+ test_tsk_thread_flag(next, TIF_SSBD))
+ return;
+
+ if (compat_user_mode(regs))
+ set_compat_ssbs_bit(regs);
+ else if (user_mode(regs))
+ set_ssbs_bit(regs);
+}
+
+/*
* We store our current task in sp_el0, which is clobbered by userspace. Keep a
* shadow copy so that we can restore this upon entry from userspace.
*
@@ -429,6 +455,7 @@ __notrace_funcgraph struct task_struct *
contextidr_thread_switch(next);
entry_task_switch(next);
uao_thread_switch(next);
+ ssbs_thread_switch(next);
/*
* Complete any pending TLB or cache maintenance on this CPU in case
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prev parent reply other threads:[~2019-10-10 8:51 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20191010083544.711104709@linuxfoundation.org>
2019-10-10 8:36 ` [PATCH 4.19 089/114] arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3 Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 090/114] KVM: arm64: Set SCTLR_EL2.DSSBS if SSBD is forcefully disabled and !vhe Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 091/114] arm64: docs: Document SSBS HWCAP Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 092/114] arm64: fix SSBS sanitization Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 093/114] arm64: Add sysfs vulnerability show for spectre-v1 Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 094/114] arm64: add sysfs vulnerability show for meltdown Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 095/114] arm64: enable generic CPU vulnerabilites support Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 096/114] arm64: Always enable ssb vulnerability detection Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 097/114] arm64: Provide a command line to disable spectre_v2 mitigation Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 098/114] arm64: Advertise mitigation of Spectre-v2, or lack thereof Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 099/114] arm64: Always enable spectre-v2 vulnerability detection Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 100/114] arm64: add sysfs vulnerability show for spectre-v2 Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 101/114] arm64: add sysfs vulnerability show for speculative store bypass Greg Kroah-Hartman
2019-10-10 8:36 ` [PATCH 4.19 102/114] arm64: ssbs: Dont treat CPUs with SSBS as unaffected by SSB Greg Kroah-Hartman
2019-10-10 8:36 ` Greg Kroah-Hartman [this message]
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