* [PATCH v2 1/4] dt-bindings: Add bindings for USB3 phy on Allwinner H6
2019-10-24 10:54 [PATCH v2 0/4] Add USB 3 support for H6 and Orange Pi 3 Ondrej Jirman
@ 2019-10-24 10:54 ` Ondrej Jirman
2019-10-29 19:28 ` Rob Herring
2019-10-24 10:54 ` [PATCH v2 2/4] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC Ondrej Jirman
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Ondrej Jirman @ 2019-10-24 10:54 UTC (permalink / raw)
To: linux-sunxi, Kishon Vijay Abraham I, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai, Icenowy Zheng, Thomas Gleixner,
Arnd Bergmann
Cc: Ondrej Jirman, devicetree, Greg Kroah-Hartman, linux-kernel,
Paul Kocialkowski, linux-arm-kernel
The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
external USB3 pins of the SoC.
Add a device tree binding for the PHY.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
---
.../phy/allwinner,sun50i-h6-usb3-phy.yaml | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml
new file mode 100644
index 000000000000..e5922b427342
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Ondrej Jirman <megous@megous.com>
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Allwinner H6 USB3 PHY
+
+maintainers:
+ - Ondrej Jirman <megous@megous.com>
+
+properties:
+ compatible:
+ enum:
+ - allwinner,sun50i-h6-usb3-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - "#phy-cells"
+
+examples:
+ - |
+ #include <dt-bindings/clock/sun50i-h6-ccu.h>
+ #include <dt-bindings/reset/sun50i-h6-ccu.h>
+ phy@5210000 {
+ compatible = "allwinner,sun50i-h6-usb3-phy";
+ reg = <0x5210000 0x10000>;
+ clocks = <&ccu CLK_USB_PHY1>;
+ resets = <&ccu RST_USB_PHY1>;
+ #phy-cells = <0>;
+ };
--
2.23.0
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: Add bindings for USB3 phy on Allwinner H6
2019-10-24 10:54 ` [PATCH v2 1/4] dt-bindings: Add bindings for USB3 phy on Allwinner H6 Ondrej Jirman
@ 2019-10-29 19:28 ` Rob Herring
0 siblings, 0 replies; 7+ messages in thread
From: Rob Herring @ 2019-10-29 19:28 UTC (permalink / raw)
To: Ondrej Jirman
Cc: Ondrej Jirman, devicetree, Arnd Bergmann, Greg Kroah-Hartman,
Chen-Yu Tsai, Kishon Vijay Abraham I, Paul Kocialkowski,
linux-sunxi, linux-arm-kernel, Thomas Gleixner, linux-kernel,
Icenowy Zheng
On Thu, 24 Oct 2019 12:54:57 +0200, Ondrej Jirman wrote:
> The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
> external USB3 pins of the SoC.
>
> Add a device tree binding for the PHY.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Acked-by: Maxime Ripard <mripard@kernel.org>
> ---
> .../phy/allwinner,sun50i-h6-usb3-phy.yaml | 47 +++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/4] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
2019-10-24 10:54 [PATCH v2 0/4] Add USB 3 support for H6 and Orange Pi 3 Ondrej Jirman
2019-10-24 10:54 ` [PATCH v2 1/4] dt-bindings: Add bindings for USB3 phy on Allwinner H6 Ondrej Jirman
@ 2019-10-24 10:54 ` Ondrej Jirman
2019-10-25 11:45 ` Kishon Vijay Abraham I
2019-10-24 10:54 ` [PATCH v2 3/4] arm64: dts: allwinner: h6: add USB3 device nodes Ondrej Jirman
2019-10-24 10:55 ` [PATCH v2 4/4] arm64: dts: allwinner: orange-pi-3: Enable USB 3.0 host support Ondrej Jirman
3 siblings, 1 reply; 7+ messages in thread
From: Ondrej Jirman @ 2019-10-24 10:54 UTC (permalink / raw)
To: linux-sunxi, Kishon Vijay Abraham I, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai, Icenowy Zheng, Thomas Gleixner,
Arnd Bergmann
Cc: Ondrej Jirman, devicetree, Greg Kroah-Hartman, linux-kernel,
Paul Kocialkowski, linux-arm-kernel
From: Icenowy Zheng <icenowy@aosc.io>
Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
controlled).
Add a driver for it.
The register operations in this driver is mainly extracted from the BSP
USB3 driver.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
---
drivers/phy/allwinner/Kconfig | 12 ++
drivers/phy/allwinner/Makefile | 1 +
drivers/phy/allwinner/phy-sun50i-usb3.c | 195 ++++++++++++++++++++++++
3 files changed, 208 insertions(+)
create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c
diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
index 215425296c77..fcae35ddd430 100644
--- a/drivers/phy/allwinner/Kconfig
+++ b/drivers/phy/allwinner/Kconfig
@@ -45,3 +45,15 @@ config PHY_SUN9I_USB
sun9i SoCs.
This driver controls each individual USB 2 host PHY.
+
+config PHY_SUN50I_USB3
+ tristate "Allwinner sun50i SoC USB3 PHY driver"
+ depends on ARCH_SUNXI && HAS_IOMEM && OF
+ depends on RESET_CONTROLLER
+ select USB_COMMON
+ select GENERIC_PHY
+ help
+ Enable this to support the USB3.0-capable transceiver that is
+ part of some Allwinner sun50i SoCs.
+
+ This driver controls each individual USB 2+3 host PHY combo.
diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
index 799a65c0b58d..bd74901a1255 100644
--- a/drivers/phy/allwinner/Makefile
+++ b/drivers/phy/allwinner/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY) += phy-sun6i-mipi-dphy.o
obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o
+obj-$(CONFIG_PHY_SUN50I_USB3) += phy-sun50i-usb3.o
diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c
new file mode 100644
index 000000000000..8e170a4d0a11
--- /dev/null
+++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Allwinner sun50i(H6) USB 3.0 phy driver
+ *
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on phy-sun9i-usb.c, which is:
+ *
+ * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on code from Allwinner BSP, which is:
+ *
+ * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/usb/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+/* Interface Status and Control Registers */
+#define SUNXI_ISCR 0x00
+#define SUNXI_PIPE_CLOCK_CONTROL 0x14
+#define SUNXI_PHY_TUNE_LOW 0x18
+#define SUNXI_PHY_TUNE_HIGH 0x1c
+#define SUNXI_PHY_EXTERNAL_CONTROL 0x20
+
+/* USB2.0 Interface Status and Control Register */
+#define SUNXI_ISCR_FORCE_VBUS (3 << 12)
+
+/* PIPE Clock Control Register */
+#define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6)
+
+/* PHY External Control Register */
+#define SUNXI_PEC_EXTERN_VBUS (3 << 1)
+#define SUNXI_PEC_SSC_EN (1 << 24)
+#define SUNXI_PEC_REF_SSP_EN (1 << 26)
+
+/* PHY Tune High Register */
+#define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19)
+#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19)
+#define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13)
+#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13)
+#define SUNXI_TX_SWING_FULL(n) ((n) << 6)
+#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6)
+#define SUNXI_LOS_BIAS(n) ((n) << 3)
+#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)
+#define SUNXI_TXVBOOSTLVL(n) ((n) << 0)
+#define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2)
+
+struct sun50i_usb3_phy {
+ struct phy *phy;
+ void __iomem *regs;
+ struct reset_control *reset;
+ struct clk *clk;
+};
+
+static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
+{
+ u32 val;
+
+ val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
+ val |= SUNXI_PEC_EXTERN_VBUS;
+ val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
+ writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
+
+ val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
+ val |= SUNXI_PCC_PIPE_CLK_OPEN;
+ writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
+
+ val = readl(phy->regs + SUNXI_ISCR);
+ val |= SUNXI_ISCR_FORCE_VBUS;
+ writel(val, phy->regs + SUNXI_ISCR);
+
+ /*
+ * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
+ * registers are directly taken from the BSP USB3 driver from
+ * Allwiner.
+ */
+ writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
+
+ val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
+ val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
+ SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
+ SUNXI_TX_DEEMPH_3P5DB_MASK);
+ val |= SUNXI_TXVBOOSTLVL(0x7);
+ val |= SUNXI_LOS_BIAS(0x7);
+ val |= SUNXI_TX_SWING_FULL(0x55);
+ val |= SUNXI_TX_DEEMPH_6DB(0x20);
+ val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
+ writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
+}
+
+static int sun50i_usb3_phy_init(struct phy *_phy)
+{
+ struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
+ int ret;
+
+ ret = clk_prepare_enable(phy->clk);
+ if (ret)
+ goto err_clk;
+
+ ret = reset_control_deassert(phy->reset);
+ if (ret)
+ goto err_reset;
+
+ sun50i_usb3_phy_open(phy);
+ return 0;
+
+err_reset:
+ clk_disable_unprepare(phy->clk);
+
+err_clk:
+ return ret;
+}
+
+static int sun50i_usb3_phy_exit(struct phy *_phy)
+{
+ struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
+
+ reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk);
+
+ return 0;
+}
+
+static const struct phy_ops sun50i_usb3_phy_ops = {
+ .init = sun50i_usb3_phy_init,
+ .exit = sun50i_usb3_phy_exit,
+ .owner = THIS_MODULE,
+};
+
+static int sun50i_usb3_phy_probe(struct platform_device *pdev)
+{
+ struct sun50i_usb3_phy *phy;
+ struct device *dev = &pdev->dev;
+ struct phy_provider *phy_provider;
+ struct resource *res;
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ phy->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(phy->clk)) {
+ if (PTR_ERR(phy->clk) != -EPROBE_DEFER)
+ dev_err(dev, "failed to get phy clock\n");
+ return PTR_ERR(phy->clk);
+ }
+
+ phy->reset = devm_reset_control_get(dev, NULL);
+ if (IS_ERR(phy->reset)) {
+ dev_err(dev, "failed to get reset control\n");
+ return PTR_ERR(phy->reset);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ phy->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(phy->regs))
+ return PTR_ERR(phy->regs);
+
+ phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops);
+ if (IS_ERR(phy->phy)) {
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(phy->phy);
+ }
+
+ phy_set_drvdata(phy->phy, phy);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id sun50i_usb3_phy_of_match[] = {
+ { .compatible = "allwinner,sun50i-h6-usb3-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match);
+
+static struct platform_driver sun50i_usb3_phy_driver = {
+ .probe = sun50i_usb3_phy_probe,
+ .driver = {
+ .of_match_table = sun50i_usb3_phy_of_match,
+ .name = "sun50i-usb3-phy",
+ }
+};
+module_platform_driver(sun50i_usb3_phy_driver);
+
+MODULE_DESCRIPTION("Allwinner sun50i USB 3.0 phy driver");
+MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
+MODULE_LICENSE("GPL");
--
2.23.0
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/4] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
2019-10-24 10:54 ` [PATCH v2 2/4] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC Ondrej Jirman
@ 2019-10-25 11:45 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 7+ messages in thread
From: Kishon Vijay Abraham I @ 2019-10-25 11:45 UTC (permalink / raw)
To: Ondrej Jirman, linux-sunxi, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai, Icenowy Zheng, Thomas Gleixner,
Arnd Bergmann
Cc: devicetree, Greg Kroah-Hartman, linux-kernel,
Kishon Vijay Abraham I, Paul Kocialkowski, linux-arm-kernel
Hi,
On 24/10/19 4:24 PM, Ondrej Jirman wrote:
> From: Icenowy Zheng <icenowy@aosc.io>
>
> Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> controlled).
>
> Add a driver for it.
>
> The register operations in this driver is mainly extracted from the BSP
> USB3 driver.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> Acked-by: Maxime Ripard <mripard@kernel.org>
> ---
> drivers/phy/allwinner/Kconfig | 12 ++
> drivers/phy/allwinner/Makefile | 1 +
> drivers/phy/allwinner/phy-sun50i-usb3.c | 195 ++++++++++++++++++++++++
> 3 files changed, 208 insertions(+)
> create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c
>
> diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
> index 215425296c77..fcae35ddd430 100644
> --- a/drivers/phy/allwinner/Kconfig
> +++ b/drivers/phy/allwinner/Kconfig
> @@ -45,3 +45,15 @@ config PHY_SUN9I_USB
> sun9i SoCs.
>
> This driver controls each individual USB 2 host PHY.
> +
> +config PHY_SUN50I_USB3
> + tristate "Allwinner sun50i SoC USB3 PHY driver"
> + depends on ARCH_SUNXI && HAS_IOMEM && OF
> + depends on RESET_CONTROLLER
> + select USB_COMMON
Looks like USB_COMMON is not required here.
> + select GENERIC_PHY
> + help
> + Enable this to support the USB3.0-capable transceiver that is
> + part of some Allwinner sun50i SoCs.
> +
> + This driver controls each individual USB 2+3 host PHY combo.
> diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
> index 799a65c0b58d..bd74901a1255 100644
> --- a/drivers/phy/allwinner/Makefile
> +++ b/drivers/phy/allwinner/Makefile
> @@ -2,3 +2,4 @@
> obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
> obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY) += phy-sun6i-mipi-dphy.o
> obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o
> +obj-$(CONFIG_PHY_SUN50I_USB3) += phy-sun50i-usb3.o
> diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c
> new file mode 100644
> index 000000000000..8e170a4d0a11
> --- /dev/null
> +++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
> @@ -0,0 +1,195 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Allwinner sun50i(H6) USB 3.0 phy driver
> + *
> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> + *
> + * Based on phy-sun9i-usb.c, which is:
> + *
> + * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
> + *
> + * Based on code from Allwinner BSP, which is:
> + *
> + * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/usb/of.h>
this too..
Thanks
Kishon
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/4] arm64: dts: allwinner: h6: add USB3 device nodes
2019-10-24 10:54 [PATCH v2 0/4] Add USB 3 support for H6 and Orange Pi 3 Ondrej Jirman
2019-10-24 10:54 ` [PATCH v2 1/4] dt-bindings: Add bindings for USB3 phy on Allwinner H6 Ondrej Jirman
2019-10-24 10:54 ` [PATCH v2 2/4] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC Ondrej Jirman
@ 2019-10-24 10:54 ` Ondrej Jirman
2019-10-24 10:55 ` [PATCH v2 4/4] arm64: dts: allwinner: orange-pi-3: Enable USB 3.0 host support Ondrej Jirman
3 siblings, 0 replies; 7+ messages in thread
From: Ondrej Jirman @ 2019-10-24 10:54 UTC (permalink / raw)
To: linux-sunxi, Kishon Vijay Abraham I, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai, Icenowy Zheng, Thomas Gleixner,
Arnd Bergmann
Cc: Ondrej Jirman, devicetree, Greg Kroah-Hartman, linux-kernel,
Paul Kocialkowski, linux-arm-kernel
From: Icenowy Zheng <icenowy@aosc.io>
Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
a custom PHY.
Add device tree nodes for them.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 32 ++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 0d5ea19336a1..80233db478e6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -537,6 +537,38 @@
status = "disabled";
};
+ dwc3: dwc3@5200000 {
+ compatible = "snps,dwc3";
+ reg = <0x05200000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_XHCI>,
+ <&ccu CLK_BUS_XHCI>,
+ <&rtc 0>;
+ clock-names = "ref", "bus_early", "suspend";
+ resets = <&ccu RST_BUS_XHCI>;
+ /*
+ * The datasheet of the chip doesn't declare the
+ * peripheral function, and there's no boards known
+ * to have a USB Type-B port routed to the port.
+ * In addition, no one has tested the peripheral
+ * function yet.
+ * So set the dr_mode to "host" in the DTSI file.
+ */
+ dr_mode = "host";
+ phys = <&usb3phy>;
+ phy-names = "usb3-phy";
+ status = "disabled";
+ };
+
+ usb3phy: phy@5210000 {
+ compatible = "allwinner,sun50i-h6-usb3-phy";
+ reg = <0x5210000 0x10000>;
+ clocks = <&ccu CLK_USB_PHY1>;
+ resets = <&ccu RST_USB_PHY1>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
ehci3: usb@5311000 {
compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
reg = <0x05311000 0x100>;
--
2.23.0
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* [PATCH v2 4/4] arm64: dts: allwinner: orange-pi-3: Enable USB 3.0 host support
2019-10-24 10:54 [PATCH v2 0/4] Add USB 3 support for H6 and Orange Pi 3 Ondrej Jirman
` (2 preceding siblings ...)
2019-10-24 10:54 ` [PATCH v2 3/4] arm64: dts: allwinner: h6: add USB3 device nodes Ondrej Jirman
@ 2019-10-24 10:55 ` Ondrej Jirman
3 siblings, 0 replies; 7+ messages in thread
From: Ondrej Jirman @ 2019-10-24 10:55 UTC (permalink / raw)
To: linux-sunxi, Kishon Vijay Abraham I, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai, Icenowy Zheng, Thomas Gleixner,
Arnd Bergmann
Cc: Ondrej Jirman, devicetree, Greg Kroah-Hartman, linux-kernel,
Paul Kocialkowski, linux-arm-kernel
Enable Allwinner's USB 3.0 phy and the host controller. Orange Pi 3
board has GL3510 USB 3.0 4-port hub connected to the SoC's USB 3.0
port. All four ports are exposed via USB3-A connectors. VBUS is
always on, since it's powered directly from DCIN (VCC-5V) and
not switchable.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index eb379cd402ac..259af5b0f1a7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -94,6 +94,10 @@
status = "okay";
};
+&dwc3 {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -285,3 +289,7 @@
usb3_vbus-supply = <®_vcc5v>;
status = "okay";
};
+
+&usb3phy {
+ status = "okay";
+};
--
2.23.0
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