From: Nishanth Menon <nm@ti.com>
To: Peter Rosin <peda@axentia.se>
Cc: devicetree@vger.kernel.org, nsekhar@ti.com,
linux-kernel@vger.kernel.org, kishon@ti.com, t-kristo@ti.com,
robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
Roger Quadros <rogerq@ti.com>
Subject: Re: [PATCH v3 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines
Date: Wed, 16 Sep 2020 10:45:36 -0500 [thread overview]
Message-ID: <20200916154536.m552ft2jzfsaeokr@akan> (raw)
In-Reply-To: <e28e98a0-f3fc-29bd-d7a6-cc45f3a69ede@axentia.se>
On 06:52-20200916, Peter Rosin wrote:
> Hi,
>
> Sorry for the delay.
>
> On 2020-09-15 13:20, Roger Quadros wrote:
> > Each SERDES lane mux can select upto 4 different IPs.
> > There are 4 lanes in each J7200 SERDES. Define all
> > the possible functions in this file.
> >
> > Cc: Peter Rosin <peda@axentia.se>
> > Signed-off-by: Roger Quadros <rogerq@ti.com>
> > ---
> > include/dt-bindings/mux/mux-j7200-wiz.h | 29 +++++++++++++++++++++++++
> > 1 file changed, 29 insertions(+)
> > create mode 100644 include/dt-bindings/mux/mux-j7200-wiz.h
> >
> > diff --git a/include/dt-bindings/mux/mux-j7200-wiz.h b/include/dt-bindings/mux/mux-j7200-wiz.h
> > new file mode 100644
> > index 000000000000..b091b1185a36
> > --- /dev/null
> > +++ b/include/dt-bindings/mux/mux-j7200-wiz.h
> > @@ -0,0 +1,29 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * This header provides constants for J7200 WIZ.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_J7200_WIZ
> > +#define _DT_BINDINGS_J7200_WIZ
> > +
> > +#define SERDES0_LANE0_QSGMII_LANE3 0x0
> > +#define SERDES0_LANE0_PCIE1_LANE0 0x1
> > +#define SERDES0_LANE0_IP3_UNUSED 0x2
> > +#define SERDES0_LANE0_IP4_UNUSED 0x3
> > +
> > +#define SERDES0_LANE1_QSGMII_LANE4 0x0
> > +#define SERDES0_LANE1_PCIE1_LANE1 0x1
> > +#define SERDES0_LANE1_IP3_UNUSED 0x2
> > +#define SERDES0_LANE1_IP4_UNUSED 0x3
> > +
> > +#define SERDES0_LANE2_QSGMII_LANE1 0x0
> > +#define SERDES0_LANE2_PCIE1_LANE2 0x1
> > +#define SERDES0_LANE2_IP3_UNUSED 0x2
> > +#define SERDES0_LANE2_IP4_UNUSED 0x3
> > +
> > +#define SERDES0_LANE3_QSGMII_LANE2 0x0
> > +#define SERDES0_LANE3_PCIE1_LANE3 0x1
> > +#define SERDES0_LANE3_USB 0x2
> > +#define SERDES0_LANE3_IP4_UNUSED 0x3
> > +
> > +#endif /* _DT_BINDINGS_J7200_WIZ */
>
> Should not the defines start with J7200_WIZ? SERDES0 seems like a too
> generic prefix, at least to me.
Thanks, good point. I am not sure if WIZ should even be used.. It is
a TI internal prefix for various serdes solutions, but I agree that
SERDES0 is too generic a terminology. That said, we should cleanup
include/dt-bindings/mux/mux-j721e-wiz.h as well, prior to introducing
j7200 changes.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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next prev parent reply other threads:[~2020-09-16 15:47 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-15 11:20 [PATCH v3 0/6] arm64: dts: ti: Add USB support for J7200 EVM Roger Quadros
2020-09-15 11:20 ` [PATCH v3 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines Roger Quadros
2020-09-16 4:52 ` Peter Rosin
2020-09-16 15:45 ` Nishanth Menon [this message]
2020-09-17 9:45 ` Peter Rosin
2020-09-17 12:27 ` Nishanth Menon
2020-09-17 12:53 ` Peter Rosin
2020-09-17 13:00 ` Nishanth Menon
2020-09-17 10:17 ` Kishon Vijay Abraham I
2020-09-17 12:36 ` Nishanth Menon
2020-09-17 12:00 ` Roger Quadros
2020-09-17 12:14 ` Nishanth Menon
2020-09-17 12:37 ` Peter Rosin
2020-09-17 12:51 ` Nishanth Menon
2020-09-15 11:20 ` [PATCH v3 2/6] arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux Roger Quadros
2020-09-15 11:20 ` [PATCH v3 3/6] arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX Roger Quadros
2020-09-15 11:20 ` [PATCH v3 4/6] arm64: dts: ti: k3-j7200-main: Add USB controller Roger Quadros
2020-09-15 11:20 ` [PATCH v3 5/6] arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function Roger Quadros
2020-09-15 11:20 ` [PATCH v3 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Add USB support Roger Quadros
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